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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / usb / musb / musb_gadget.c
blob98519c5d8b5cc23e5407dac87a521004d8885f59
1 /*
2 * MUSB OTG driver peripheral support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
47
48 #include "musb_core.h"
49
50
51 /* MUSB PERIPHERAL status 3-mar-2006:
52 *
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
54 * Minor glitches:
55 *
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
60 * clearing SENDSTALL?
61 *
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
65 * required.
66 *
67 * - TX/IN
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
73 *
74 * - RX/OUT
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
80 *
81 * - ISO not tested ... might work, but only weakly isochronous
82 *
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
86 *
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
91 */
92
93 /* ----------------------------------------------------------------------- */
94
95 #define is_buffer_mapped(req) (is_dma_capable() && \
96 (req->map_state != UN_MAPPED))
97
98 /* Maps the buffer to dma */
99
100 static inline void map_dma_buffer(struct musb_request *request,
101 struct musb *musb, struct musb_ep *musb_ep)
102 {
103 int compatible = true;
104 struct dma_controller *dma = musb->dma_controller;
105
106 request->map_state = UN_MAPPED;
107
108 if (!is_dma_capable() || !musb_ep->dma)
109 return;
110
111 /* Check if DMA engine can handle this request.
112 * DMA code must reject the USB request explicitly.
113 * Default behaviour is to map the request.
114 */
115 if (dma->is_compatible)
116 compatible = dma->is_compatible(musb_ep->dma,
117 musb_ep->packet_sz, request->request.buf,
118 request->request.length);
119 if (!compatible)
120 return;
121
122 if (request->request.dma == DMA_ADDR_INVALID) {
123 request->request.dma = dma_map_single(
124 musb->controller,
125 request->request.buf,
126 request->request.length,
127 request->tx
128 ? DMA_TO_DEVICE
129 : DMA_FROM_DEVICE);
130 request->map_state = MUSB_MAPPED;
131 } else {
132 dma_sync_single_for_device(musb->controller,
133 request->request.dma,
134 request->request.length,
135 request->tx
136 ? DMA_TO_DEVICE
137 : DMA_FROM_DEVICE);
138 request->map_state = PRE_MAPPED;
139 }
140 }
141
142 /* Unmap the buffer from dma and maps it back to cpu */
143 static inline void unmap_dma_buffer(struct musb_request *request,
144 struct musb *musb)
145 {
146 if (!is_buffer_mapped(request))
147 return;
148
149 if (request->request.dma == DMA_ADDR_INVALID) {
150 DBG(20, "not unmapping a never mapped buffer\n");
151 return;
152 }
153 if (request->map_state == MUSB_MAPPED) {
154 dma_unmap_single(musb->controller,
155 request->request.dma,
156 request->request.length,
157 request->tx
158 ? DMA_TO_DEVICE
159 : DMA_FROM_DEVICE);
160 request->request.dma = DMA_ADDR_INVALID;
161 } else { /* PRE_MAPPED */
162 dma_sync_single_for_cpu(musb->controller,
163 request->request.dma,
164 request->request.length,
165 request->tx
166 ? DMA_TO_DEVICE
167 : DMA_FROM_DEVICE);
168 }
169 request->map_state = UN_MAPPED;
170 }
171
172 /*
173 * Immediately complete a request.
174 *
175 * @param request the request to complete
176 * @param status the status to complete the request with
177 * Context: controller locked, IRQs blocked.
178 */
179 void musb_g_giveback(
180 struct musb_ep *ep,
181 struct usb_request *request,
182 int status)
183 __releases(ep->musb->lock)
184 __acquires(ep->musb->lock)
185 {
186 struct musb_request *req;
187 struct musb *musb;
188 int busy = ep->busy;
189
190 req = to_musb_request(request);
191
192 list_del(&req->list);
193 if (req->request.status == -EINPROGRESS)
194 req->request.status = status;
195 musb = req->musb;
196
197 ep->busy = 1;
198 spin_unlock(&musb->lock);
199 unmap_dma_buffer(req, musb);
200 if (request->status == 0)
201 DBG(5, "%s done request %p, %d/%d\n",
202 ep->end_point.name, request,
203 req->request.actual, req->request.length);
204 else
205 DBG(2, "%s request %p, %d/%d fault %d\n",
206 ep->end_point.name, request,
207 req->request.actual, req->request.length,
208 request->status);
209 req->request.complete(&req->ep->end_point, &req->request);
210 spin_lock(&musb->lock);
211 ep->busy = busy;
212 }
213
214 /* ----------------------------------------------------------------------- */
215
216 /*
217 * Abort requests queued to an endpoint using the status. Synchronous.
218 * caller locked controller and blocked irqs, and selected this ep.
219 */
220 static void nuke(struct musb_ep *ep, const int status)
221 {
222 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
224
225 ep->busy = 1;
226
227 if (is_dma_capable() && ep->dma) {
228 struct dma_controller *c = ep->musb->dma_controller;
229 int value;
230
231 if (ep->is_in) {
232 /*
233 * The programming guide says that we must not clear
234 * the DMAMODE bit before DMAENAB, so we only
235 * clear it in the second write...
236 */
237 musb_writew(epio, MUSB_TXCSR,
238 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
239 musb_writew(epio, MUSB_TXCSR,
240 0 | MUSB_TXCSR_FLUSHFIFO);
241 } else {
242 musb_writew(epio, MUSB_RXCSR,
243 0 | MUSB_RXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_RXCSR,
245 0 | MUSB_RXCSR_FLUSHFIFO);
246 }
247
248 value = c->channel_abort(ep->dma);
249 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
250 c->channel_release(ep->dma);
251 ep->dma = NULL;
252 }
253
254 while (!list_empty(&ep->req_list)) {
255 req = list_first_entry(&ep->req_list, struct musb_request, list);
256 musb_g_giveback(ep, &req->request, status);
257 }
258 }
259
260 /* ----------------------------------------------------------------------- */
261
262 /* Data transfers - pure PIO, pure DMA, or mixed mode */
263
264 /*
265 * This assumes the separate CPPI engine is responding to DMA requests
266 * from the usb core ... sequenced a bit differently from mentor dma.
267 */
268
269 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
270 {
271 if (can_bulk_split(musb, ep->type))
272 return ep->hw_ep->max_packet_sz_tx;
273 else
274 return ep->packet_sz;
275 }
276
277
278 #ifdef CONFIG_USB_INVENTRA_DMA
279
280 /* Peripheral tx (IN) using Mentor DMA works as follows:
281 Only mode 0 is used for transfers <= wPktSize,
282 mode 1 is used for larger transfers,
283
284 One of the following happens:
285 - Host sends IN token which causes an endpoint interrupt
286 -> TxAvail
287 -> if DMA is currently busy, exit.
288 -> if queue is non-empty, txstate().
289
290 - Request is queued by the gadget driver.
291 -> if queue was previously empty, txstate()
292
293 txstate()
294 -> start
295 /\ -> setup DMA
296 | (data is transferred to the FIFO, then sent out when
297 | IN token(s) are recd from Host.
298 | -> DMA interrupt on completion
299 | calls TxAvail.
300 | -> stop DMA, ~DMAENAB,
301 | -> set TxPktRdy for last short pkt or zlp
302 | -> Complete Request
303 | -> Continue next request (call txstate)
304 |___________________________________|
305
306 * Non-Mentor DMA engines can of course work differently, such as by
307 * upleveling from irq-per-packet to irq-per-buffer.
308 */
309
310 #endif
311
312 /*
313 * An endpoint is transmitting data. This can be called either from
314 * the IRQ routine or from ep.queue() to kickstart a request on an
315 * endpoint.
316 *
317 * Context: controller locked, IRQs blocked, endpoint selected
318 */
319 static void txstate(struct musb *musb, struct musb_request *req)
320 {
321 u8 epnum = req->epnum;
322 struct musb_ep *musb_ep;
323 void __iomem *epio = musb->endpoints[epnum].regs;
324 struct usb_request *request;
325 u16 fifo_count = 0, csr;
326 int use_dma = 0;
327
328 musb_ep = req->ep;
329
330 /* we shouldn't get here while DMA is active ... but we do ... */
331 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
332 DBG(4, "dma pending...\n");
333 return;
334 }
335
336 /* read TXCSR before */
337 csr = musb_readw(epio, MUSB_TXCSR);
338
339 request = &req->request;
340 fifo_count = min(max_ep_writesize(musb, musb_ep),
341 (int)(request->length - request->actual));
342
343 if (csr & MUSB_TXCSR_TXPKTRDY) {
344 DBG(5, "%s old packet still ready , txcsr %03x\n",
345 musb_ep->end_point.name, csr);
346 return;
347 }
348
349 if (csr & MUSB_TXCSR_P_SENDSTALL) {
350 DBG(5, "%s stalling, txcsr %03x\n",
351 musb_ep->end_point.name, csr);
352 return;
353 }
354
355 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
356 epnum, musb_ep->packet_sz, fifo_count,
357 csr);
358
359 #ifndef CONFIG_MUSB_PIO_ONLY
360 if (is_buffer_mapped(req)) {
361 struct dma_controller *c = musb->dma_controller;
362 size_t request_size;
363
364 /* setup DMA, then program endpoint CSR */
365 request_size = min_t(size_t, request->length - request->actual,
366 musb_ep->dma->max_len);
367
368 use_dma = (request->dma != DMA_ADDR_INVALID);
369
370 /* MUSB_TXCSR_P_ISO is still set correctly */
371
372 #ifdef CONFIG_USB_INVENTRA_DMA
373 {
374 if (request_size < musb_ep->packet_sz)
375 musb_ep->dma->desired_mode = 0;
376 else
377 musb_ep->dma->desired_mode = 1;
378
379 use_dma = use_dma && c->channel_program(
380 musb_ep->dma, musb_ep->packet_sz,
381 musb_ep->dma->desired_mode,
382 request->dma + request->actual, request_size);
383 if (use_dma) {
384 if (musb_ep->dma->desired_mode == 0) {
385 /*
386 * We must not clear the DMAMODE bit
387 * before the DMAENAB bit -- and the
388 * latter doesn't always get cleared
389 * before we get here...
390 */
391 csr &= ~(MUSB_TXCSR_AUTOSET
392 | MUSB_TXCSR_DMAENAB);
393 musb_writew(epio, MUSB_TXCSR, csr
394 | MUSB_TXCSR_P_WZC_BITS);
395 csr &= ~MUSB_TXCSR_DMAMODE;
396 csr |= (MUSB_TXCSR_DMAENAB |
397 MUSB_TXCSR_MODE);
398 /* against programming guide */
399 } else {
400 csr |= (MUSB_TXCSR_DMAENAB
401 | MUSB_TXCSR_DMAMODE
402 | MUSB_TXCSR_MODE);
403 if (!musb_ep->hb_mult)
404 csr |= MUSB_TXCSR_AUTOSET;
405 }
406 csr &= ~MUSB_TXCSR_P_UNDERRUN;
407
408 musb_writew(epio, MUSB_TXCSR, csr);
409 }
410 }
411
412 #elif defined(CONFIG_USB_TI_CPPI_DMA)
413 /* program endpoint CSR first, then setup DMA */
414 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
415 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
416 MUSB_TXCSR_MODE;
417 musb_writew(epio, MUSB_TXCSR,
418 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
419 | csr);
420
421 /* ensure writebuffer is empty */
422 csr = musb_readw(epio, MUSB_TXCSR);
423
424 /* NOTE host side sets DMAENAB later than this; both are
425 * OK since the transfer dma glue (between CPPI and Mentor
426 * fifos) just tells CPPI it could start. Data only moves
427 * to the USB TX fifo when both fifos are ready.
428 */
429
430 /* "mode" is irrelevant here; handle terminating ZLPs like
431 * PIO does, since the hardware RNDIS mode seems unreliable
432 * except for the last-packet-is-already-short case.
433 */
434 use_dma = use_dma && c->channel_program(
435 musb_ep->dma, musb_ep->packet_sz,
436 0,
437 request->dma + request->actual,
438 request_size);
439 if (!use_dma) {
440 c->channel_release(musb_ep->dma);
441 musb_ep->dma = NULL;
442 csr &= ~MUSB_TXCSR_DMAENAB;
443 musb_writew(epio, MUSB_TXCSR, csr);
444 /* invariant: prequest->buf is non-null */
445 }
446 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
447 use_dma = use_dma && c->channel_program(
448 musb_ep->dma, musb_ep->packet_sz,
449 request->zero,
450 request->dma + request->actual,
451 request_size);
452 #endif
453 }
454 #endif
455
456 if (!use_dma) {
457 /*
458 * Unmap the dma buffer back to cpu if dma channel
459 * programming fails
460 */
461 unmap_dma_buffer(req, musb);
462
463 musb_write_fifo(musb_ep->hw_ep, fifo_count,
464 (u8 *) (request->buf + request->actual));
465 request->actual += fifo_count;
466 csr |= MUSB_TXCSR_TXPKTRDY;
467 csr &= ~MUSB_TXCSR_P_UNDERRUN;
468 musb_writew(epio, MUSB_TXCSR, csr);
469 }
470
471 /* host may already have the data when this message shows... */
472 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
473 musb_ep->end_point.name, use_dma ? "dma" : "pio",
474 request->actual, request->length,
475 musb_readw(epio, MUSB_TXCSR),
476 fifo_count,
477 musb_readw(epio, MUSB_TXMAXP));
478 }
479
480 /*
481 * FIFO state update (e.g. data ready).
482 * Called from IRQ, with controller locked.
483 */
484 void musb_g_tx(struct musb *musb, u8 epnum)
485 {
486 u16 csr;
487 struct musb_request *req;
488 struct usb_request *request;
489 u8 __iomem *mbase = musb->mregs;
490 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
491 void __iomem *epio = musb->endpoints[epnum].regs;
492 struct dma_channel *dma;
493
494 musb_ep_select(mbase, epnum);
495 req = next_request(musb_ep);
496 request = &req->request;
497
498 csr = musb_readw(epio, MUSB_TXCSR);
499 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
500
501 dma = is_dma_capable() ? musb_ep->dma : NULL;
502
503 /*
504 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
505 * probably rates reporting as a host error.
506 */
507 if (csr & MUSB_TXCSR_P_SENTSTALL) {
508 csr |= MUSB_TXCSR_P_WZC_BITS;
509 csr &= ~MUSB_TXCSR_P_SENTSTALL;
510 musb_writew(epio, MUSB_TXCSR, csr);
511 return;
512 }
513
514 if (csr & MUSB_TXCSR_P_UNDERRUN) {
515 /* We NAKed, no big deal... little reason to care. */
516 csr |= MUSB_TXCSR_P_WZC_BITS;
517 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
518 musb_writew(epio, MUSB_TXCSR, csr);
519 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
520 }
521
522 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
523 /*
524 * SHOULD NOT HAPPEN... has with CPPI though, after
525 * changing SENDSTALL (and other cases); harmless?
526 */
527 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
528 return;
529 }
530
531 if (request) {
532 u8 is_dma = 0;
533
534 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
535 is_dma = 1;
536 csr |= MUSB_TXCSR_P_WZC_BITS;
537 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
538 MUSB_TXCSR_TXPKTRDY);
539 musb_writew(epio, MUSB_TXCSR, csr);
540 /* Ensure writebuffer is empty. */
541 csr = musb_readw(epio, MUSB_TXCSR);
542 request->actual += musb_ep->dma->actual_len;
543 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
544 epnum, csr, musb_ep->dma->actual_len, request);
545 }
546
547 /*
548 * First, maybe a terminating short packet. Some DMA
549 * engines might handle this by themselves.
550 */
551 if ((request->zero && request->length
552 && (request->length % musb_ep->packet_sz == 0)
553 && (request->actual == request->length))
554 #ifdef CONFIG_USB_INVENTRA_DMA
555 || (is_dma && (!dma->desired_mode ||
556 (request->actual &
557 (musb_ep->packet_sz - 1))))
558 #endif
559 ) {
560 /*
561 * On DMA completion, FIFO may not be
562 * available yet...
563 */
564 if (csr & MUSB_TXCSR_TXPKTRDY)
565 return;
566
567 DBG(4, "sending zero pkt\n");
568 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
569 | MUSB_TXCSR_TXPKTRDY);
570 request->zero = 0;
571 }
572
573 if (request->actual == request->length) {
574 musb_g_giveback(musb_ep, request, 0);
575 req = musb_ep->desc ? next_request(musb_ep) : NULL;
576 if (!req) {
577 DBG(4, "%s idle now\n",
578 musb_ep->end_point.name);
579 return;
580 }
581 }
582
583 txstate(musb, req);
584 }
585 }
586
587 /* ------------------------------------------------------------ */
588
589 #ifdef CONFIG_USB_INVENTRA_DMA
590
591 /* Peripheral rx (OUT) using Mentor DMA works as follows:
592 - Only mode 0 is used.
593
594 - Request is queued by the gadget class driver.
595 -> if queue was previously empty, rxstate()
596
597 - Host sends OUT token which causes an endpoint interrupt
598 /\ -> RxReady
599 | -> if request queued, call rxstate
600 | /\ -> setup DMA
601 | | -> DMA interrupt on completion
602 | | -> RxReady
603 | | -> stop DMA
604 | | -> ack the read
605 | | -> if data recd = max expected
606 | | by the request, or host
607 | | sent a short packet,
608 | | complete the request,
609 | | and start the next one.
610 | |_____________________________________|
611 | else just wait for the host
612 | to send the next OUT token.
613 |__________________________________________________|
614
615 * Non-Mentor DMA engines can of course work differently.
616 */
617
618 #endif
619
620 /*
621 * Context: controller locked, IRQs blocked, endpoint selected
622 */
623 static void rxstate(struct musb *musb, struct musb_request *req)
624 {
625 const u8 epnum = req->epnum;
626 struct usb_request *request = &req->request;
627 struct musb_ep *musb_ep;
628 void __iomem *epio = musb->endpoints[epnum].regs;
629 unsigned fifo_count = 0;
630 u16 len;
631 u16 csr = musb_readw(epio, MUSB_RXCSR);
632 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
633
634 if (hw_ep->is_shared_fifo)
635 musb_ep = &hw_ep->ep_in;
636 else
637 musb_ep = &hw_ep->ep_out;
638
639 len = musb_ep->packet_sz;
640
641 /* We shouldn't get here while DMA is active, but we do... */
642 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
643 DBG(4, "DMA pending...\n");
644 return;
645 }
646
647 if (csr & MUSB_RXCSR_P_SENDSTALL) {
648 DBG(5, "%s stalling, RXCSR %04x\n",
649 musb_ep->end_point.name, csr);
650 return;
651 }
652
653 if (is_cppi_enabled() && is_buffer_mapped(req)) {
654 struct dma_controller *c = musb->dma_controller;
655 struct dma_channel *channel = musb_ep->dma;
656
657 /* NOTE: CPPI won't actually stop advancing the DMA
658 * queue after short packet transfers, so this is almost
659 * always going to run as IRQ-per-packet DMA so that
660 * faults will be handled correctly.
661 */
662 if (c->channel_program(channel,
663 musb_ep->packet_sz,
664 !request->short_not_ok,
665 request->dma + request->actual,
666 request->length - request->actual)) {
667
668 /* make sure that if an rxpkt arrived after the irq,
669 * the cppi engine will be ready to take it as soon
670 * as DMA is enabled
671 */
672 csr &= ~(MUSB_RXCSR_AUTOCLEAR
673 | MUSB_RXCSR_DMAMODE);
674 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
675 musb_writew(epio, MUSB_RXCSR, csr);
676 return;
677 }
678 }
679
680 if (csr & MUSB_RXCSR_RXPKTRDY) {
681 len = musb_readw(epio, MUSB_RXCOUNT);
682 if (request->actual < request->length) {
683 #ifdef CONFIG_USB_INVENTRA_DMA
684 if (is_buffer_mapped(req)) {
685 struct dma_controller *c;
686 struct dma_channel *channel;
687 int use_dma = 0;
688
689 c = musb->dma_controller;
690 channel = musb_ep->dma;
691
692 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
693 * mode 0 only. So we do not get endpoint interrupts due to DMA
694 * completion. We only get interrupts from DMA controller.
695 *
696 * We could operate in DMA mode 1 if we knew the size of the tranfer
697 * in advance. For mass storage class, request->length = what the host
698 * sends, so that'd work. But for pretty much everything else,
699 * request->length is routinely more than what the host sends. For
700 * most these gadgets, end of is signified either by a short packet,
701 * or filling the last byte of the buffer. (Sending extra data in
702 * that last pckate should trigger an overflow fault.) But in mode 1,
703 * we don't get DMA completion interrrupt for short packets.
704 *
705 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
706 * to get endpoint interrupt on every DMA req, but that didn't seem
707 * to work reliably.
708 *
709 * REVISIT an updated g_file_storage can set req->short_not_ok, which
710 * then becomes usable as a runtime "use mode 1" hint...
711 */
712
713 csr |= MUSB_RXCSR_DMAENAB;
714 #ifdef USE_MODE1
715 csr |= MUSB_RXCSR_AUTOCLEAR;
716 /* csr |= MUSB_RXCSR_DMAMODE; */
717
718 /* this special sequence (enabling and then
719 * disabling MUSB_RXCSR_DMAMODE) is required
720 * to get DMAReq to activate
721 */
722 musb_writew(epio, MUSB_RXCSR,
723 csr | MUSB_RXCSR_DMAMODE);
724 #else
725 if (!musb_ep->hb_mult &&
726 musb_ep->hw_ep->rx_double_buffered)
727 csr |= MUSB_RXCSR_AUTOCLEAR;
728 #endif
729 musb_writew(epio, MUSB_RXCSR, csr);
730
731 if (request->actual < request->length) {
732 int transfer_size = 0;
733 #ifdef USE_MODE1
734 transfer_size = min(request->length - request->actual,
735 channel->max_len);
736 #else
737 transfer_size = min(request->length - request->actual,
738 (unsigned)len);
739 #endif
740 if (transfer_size <= musb_ep->packet_sz)
741 musb_ep->dma->desired_mode = 0;
742 else
743 musb_ep->dma->desired_mode = 1;
744
745 use_dma = c->channel_program(
746 channel,
747 musb_ep->packet_sz,
748 channel->desired_mode,
749 request->dma
750 + request->actual,
751 transfer_size);
752 }
753
754 if (use_dma)
755 return;
756 }
757 #endif /* Mentor's DMA */
758
759 fifo_count = request->length - request->actual;
760 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
761 musb_ep->end_point.name,
762 len, fifo_count,
763 musb_ep->packet_sz);
764
765 fifo_count = min_t(unsigned, len, fifo_count);
766
767 #ifdef CONFIG_USB_TUSB_OMAP_DMA
768 if (tusb_dma_omap() && is_buffer_mapped(req)) {
769 struct dma_controller *c = musb->dma_controller;
770 struct dma_channel *channel = musb_ep->dma;
771 u32 dma_addr = request->dma + request->actual;
772 int ret;
773
774 ret = c->channel_program(channel,
775 musb_ep->packet_sz,
776 channel->desired_mode,
777 dma_addr,
778 fifo_count);
779 if (ret)
780 return;
781 }
782 #endif
783 /*
784 * Unmap the dma buffer back to cpu if dma channel
785 * programming fails. This buffer is mapped if the
786 * channel allocation is successful
787 */
788 if (is_buffer_mapped(req)) {
789 unmap_dma_buffer(req, musb);
790
791 /*
792 * Clear DMAENAB and AUTOCLEAR for the
793 * PIO mode transfer
794 */
795 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
796 musb_writew(epio, MUSB_RXCSR, csr);
797 }
798
799 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
800 (request->buf + request->actual));
801 request->actual += fifo_count;
802
803 /* REVISIT if we left anything in the fifo, flush
804 * it and report -EOVERFLOW
805 */
806
807 /* ack the read! */
808 csr |= MUSB_RXCSR_P_WZC_BITS;
809 csr &= ~MUSB_RXCSR_RXPKTRDY;
810 musb_writew(epio, MUSB_RXCSR, csr);
811 }
812 }
813
814 /* reach the end or short packet detected */
815 if (request->actual == request->length || len < musb_ep->packet_sz)
816 musb_g_giveback(musb_ep, request, 0);
817 }
818
819 /*
820 * Data ready for a request; called from IRQ
821 */
822 void musb_g_rx(struct musb *musb, u8 epnum)
823 {
824 u16 csr;
825 struct musb_request *req;
826 struct usb_request *request;
827 void __iomem *mbase = musb->mregs;
828 struct musb_ep *musb_ep;
829 void __iomem *epio = musb->endpoints[epnum].regs;
830 struct dma_channel *dma;
831 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
832
833 if (hw_ep->is_shared_fifo)
834 musb_ep = &hw_ep->ep_in;
835 else
836 musb_ep = &hw_ep->ep_out;
837
838 musb_ep_select(mbase, epnum);
839
840 req = next_request(musb_ep);
841 if (!req)
842 return;
843
844 request = &req->request;
845
846 csr = musb_readw(epio, MUSB_RXCSR);
847 dma = is_dma_capable() ? musb_ep->dma : NULL;
848
849 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
850 csr, dma ? " (dma)" : "", request);
851
852 if (csr & MUSB_RXCSR_P_SENTSTALL) {
853 csr |= MUSB_RXCSR_P_WZC_BITS;
854 csr &= ~MUSB_RXCSR_P_SENTSTALL;
855 musb_writew(epio, MUSB_RXCSR, csr);
856 return;
857 }
858
859 if (csr & MUSB_RXCSR_P_OVERRUN) {
860 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
861 csr &= ~MUSB_RXCSR_P_OVERRUN;
862 musb_writew(epio, MUSB_RXCSR, csr);
863
864 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
865 if (request->status == -EINPROGRESS)
866 request->status = -EOVERFLOW;
867 }
868 if (csr & MUSB_RXCSR_INCOMPRX) {
869 /* REVISIT not necessarily an error */
870 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
871 }
872
873 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
874 /* "should not happen"; likely RXPKTRDY pending for DMA */
875 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
876 "%s busy, csr %04x\n",
877 musb_ep->end_point.name, csr);
878 return;
879 }
880
881 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
882 csr &= ~(MUSB_RXCSR_AUTOCLEAR
883 | MUSB_RXCSR_DMAENAB
884 | MUSB_RXCSR_DMAMODE);
885 musb_writew(epio, MUSB_RXCSR,
886 MUSB_RXCSR_P_WZC_BITS | csr);
887
888 request->actual += musb_ep->dma->actual_len;
889
890 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
891 epnum, csr,
892 musb_readw(epio, MUSB_RXCSR),
893 musb_ep->dma->actual_len, request);
894
895 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
896 /* Autoclear doesn't clear RxPktRdy for short packets */
897 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
898 || (dma->actual_len
899 & (musb_ep->packet_sz - 1))) {
900 /* ack the read! */
901 csr &= ~MUSB_RXCSR_RXPKTRDY;
902 musb_writew(epio, MUSB_RXCSR, csr);
903 }
904
905 /* incomplete, and not short? wait for next IN packet */
906 if ((request->actual < request->length)
907 && (musb_ep->dma->actual_len
908 == musb_ep->packet_sz)) {
909 /* In double buffer case, continue to unload fifo if
910 * there is Rx packet in FIFO.
911 **/
912 csr = musb_readw(epio, MUSB_RXCSR);
913 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
914 hw_ep->rx_double_buffered)
915 goto exit;
916 return;
917 }
918 #endif
919 musb_g_giveback(musb_ep, request, 0);
920
921 req = next_request(musb_ep);
922 if (!req)
923 return;
924 }
925 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
926 exit:
927 #endif
928 /* Analyze request */
929 rxstate(musb, req);
930 }
931
932 /* ------------------------------------------------------------ */
933
934 static int musb_gadget_enable(struct usb_ep *ep,
935 const struct usb_endpoint_descriptor *desc)
936 {
937 unsigned long flags;
938 struct musb_ep *musb_ep;
939 struct musb_hw_ep *hw_ep;
940 void __iomem *regs;
941 struct musb *musb;
942 void __iomem *mbase;
943 u8 epnum;
944 u16 csr;
945 unsigned tmp;
946 int status = -EINVAL;
947
948 if (!ep || !desc)
949 return -EINVAL;
950
951 musb_ep = to_musb_ep(ep);
952 hw_ep = musb_ep->hw_ep;
953 regs = hw_ep->regs;
954 musb = musb_ep->musb;
955 mbase = musb->mregs;
956 epnum = musb_ep->current_epnum;
957
958 spin_lock_irqsave(&musb->lock, flags);
959
960 if (musb_ep->desc) {
961 status = -EBUSY;
962 goto fail;
963 }
964 musb_ep->type = usb_endpoint_type(desc);
965
966 /* check direction and (later) maxpacket size against endpoint */
967 if (usb_endpoint_num(desc) != epnum)
968 goto fail;
969
970 /* REVISIT this rules out high bandwidth periodic transfers */
971 tmp = le16_to_cpu(desc->wMaxPacketSize);
972 if (tmp & ~0x07ff) {
973 int ok;
974
975 if (usb_endpoint_dir_in(desc))
976 ok = musb->hb_iso_tx;
977 else
978 ok = musb->hb_iso_rx;
979
980 if (!ok) {
981 DBG(4, "no support for high bandwidth ISO\n");
982 goto fail;
983 }
984 musb_ep->hb_mult = (tmp >> 11) & 3;
985 } else {
986 musb_ep->hb_mult = 0;
987 }
988
989 musb_ep->packet_sz = tmp & 0x7ff;
990 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
991
992 /* enable the interrupts for the endpoint, set the endpoint
993 * packet size (or fail), set the mode, clear the fifo
994 */
995 musb_ep_select(mbase, epnum);
996 if (usb_endpoint_dir_in(desc)) {
997 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
998
999 if (hw_ep->is_shared_fifo)
1000 musb_ep->is_in = 1;
1001 if (!musb_ep->is_in)
1002 goto fail;
1003
1004 if (tmp > hw_ep->max_packet_sz_tx) {
1005 DBG(4, "packet size beyond hardware FIFO size\n");
1006 goto fail;
1007 }
1008
1009 int_txe |= (1 << epnum);
1010 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1011
1012 /* REVISIT if can_bulk_split(), use by updating "tmp";
1013 * likewise high bandwidth periodic tx
1014 */
1015 /* Set TXMAXP with the FIFO size of the endpoint
1016 * to disable double buffering mode.
1017 */
1018 if (musb->double_buffer_not_ok)
1019 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1020 else
1021 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1022 | (musb_ep->hb_mult << 11));
1023
1024 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1025 if (musb_readw(regs, MUSB_TXCSR)
1026 & MUSB_TXCSR_FIFONOTEMPTY)
1027 csr |= MUSB_TXCSR_FLUSHFIFO;
1028 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1029 csr |= MUSB_TXCSR_P_ISO;
1030
1031 /* set twice in case of double buffering */
1032 musb_writew(regs, MUSB_TXCSR, csr);
1033 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1034 musb_writew(regs, MUSB_TXCSR, csr);
1035
1036 } else {
1037 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1038
1039 if (hw_ep->is_shared_fifo)
1040 musb_ep->is_in = 0;
1041 if (musb_ep->is_in)
1042 goto fail;
1043
1044 if (tmp > hw_ep->max_packet_sz_rx) {
1045 DBG(4, "packet size beyond hardware FIFO size\n");
1046 goto fail;
1047 }
1048
1049 int_rxe |= (1 << epnum);
1050 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1051
1052 /* REVISIT if can_bulk_combine() use by updating "tmp"
1053 * likewise high bandwidth periodic rx
1054 */
1055 /* Set RXMAXP with the FIFO size of the endpoint
1056 * to disable double buffering mode.
1057 */
1058 if (musb->double_buffer_not_ok)
1059 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1060 else
1061 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1062 | (musb_ep->hb_mult << 11));
1063
1064 /* force shared fifo to OUT-only mode */
1065 if (hw_ep->is_shared_fifo) {
1066 csr = musb_readw(regs, MUSB_TXCSR);
1067 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1068 musb_writew(regs, MUSB_TXCSR, csr);
1069 }
1070
1071 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1072 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1073 csr |= MUSB_RXCSR_P_ISO;
1074 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1075 csr |= MUSB_RXCSR_DISNYET;
1076
1077 /* set twice in case of double buffering */
1078 musb_writew(regs, MUSB_RXCSR, csr);
1079 musb_writew(regs, MUSB_RXCSR, csr);
1080 }
1081
1082 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1083 * for some reason you run out of channels here.
1084 */
1085 if (is_dma_capable() && musb->dma_controller) {
1086 struct dma_controller *c = musb->dma_controller;
1087
1088 musb_ep->dma = c->channel_alloc(c, hw_ep,
1089 (desc->bEndpointAddress & USB_DIR_IN));
1090 } else
1091 musb_ep->dma = NULL;
1092
1093 musb_ep->desc = desc;
1094 musb_ep->busy = 0;
1095 musb_ep->wedged = 0;
1096 status = 0;
1097
1098 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1099 musb_driver_name, musb_ep->end_point.name,
1100 ({ char *s; switch (musb_ep->type) {
1101 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1102 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1103 default: s = "iso"; break;
1104 }; s; }),
1105 musb_ep->is_in ? "IN" : "OUT",
1106 musb_ep->dma ? "dma, " : "",
1107 musb_ep->packet_sz);
1108
1109 schedule_work(&musb->irq_work);
1110
1111 fail:
1112 spin_unlock_irqrestore(&musb->lock, flags);
1113 return status;
1114 }
1115
1116 /*
1117 * Disable an endpoint flushing all requests queued.
1118 */
1119 static int musb_gadget_disable(struct usb_ep *ep)
1120 {
1121 unsigned long flags;
1122 struct musb *musb;
1123 u8 epnum;
1124 struct musb_ep *musb_ep;
1125 void __iomem *epio;
1126 int status = 0;
1127
1128 musb_ep = to_musb_ep(ep);
1129 musb = musb_ep->musb;
1130 epnum = musb_ep->current_epnum;
1131 epio = musb->endpoints[epnum].regs;
1132
1133 spin_lock_irqsave(&musb->lock, flags);
1134 musb_ep_select(musb->mregs, epnum);
1135
1136 /* zero the endpoint sizes */
1137 if (musb_ep->is_in) {
1138 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1139 int_txe &= ~(1 << epnum);
1140 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1141 musb_writew(epio, MUSB_TXMAXP, 0);
1142 } else {
1143 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1144 int_rxe &= ~(1 << epnum);
1145 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1146 musb_writew(epio, MUSB_RXMAXP, 0);
1147 }
1148
1149 musb_ep->desc = NULL;
1150
1151 /* abort all pending DMA and requests */
1152 nuke(musb_ep, -ESHUTDOWN);
1153
1154 schedule_work(&musb->irq_work);
1155
1156 spin_unlock_irqrestore(&(musb->lock), flags);
1157
1158 DBG(2, "%s\n", musb_ep->end_point.name);
1159
1160 return status;
1161 }
1162
1163 /*
1164 * Allocate a request for an endpoint.
1165 * Reused by ep0 code.
1166 */
1167 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1168 {
1169 struct musb_ep *musb_ep = to_musb_ep(ep);
1170 struct musb_request *request = NULL;
1171
1172 request = kzalloc(sizeof *request, gfp_flags);
1173 if (!request) {
1174 DBG(4, "not enough memory\n");
1175 return NULL;
1176 }
1177
1178 request->request.dma = DMA_ADDR_INVALID;
1179 request->epnum = musb_ep->current_epnum;
1180 request->ep = musb_ep;
1181
1182 return &request->request;
1183 }
1184
1185 /*
1186 * Free a request
1187 * Reused by ep0 code.
1188 */
1189 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1190 {
1191 kfree(to_musb_request(req));
1192 }
1193
1194 static LIST_HEAD(buffers);
1195
1196 struct free_record {
1197 struct list_head list;
1198 struct device *dev;
1199 unsigned bytes;
1200 dma_addr_t dma;
1201 };
1202
1203 /*
1204 * Context: controller locked, IRQs blocked.
1205 */
1206 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1207 {
1208 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1209 req->tx ? "TX/IN" : "RX/OUT",
1210 &req->request, req->request.length, req->epnum);
1211
1212 musb_ep_select(musb->mregs, req->epnum);
1213 if (req->tx)
1214 txstate(musb, req);
1215 else
1216 rxstate(musb, req);
1217 }
1218
1219 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1220 gfp_t gfp_flags)
1221 {
1222 struct musb_ep *musb_ep;
1223 struct musb_request *request;
1224 struct musb *musb;
1225 int status = 0;
1226 unsigned long lockflags;
1227
1228 if (!ep || !req)
1229 return -EINVAL;
1230 if (!req->buf)
1231 return -ENODATA;
1232
1233 musb_ep = to_musb_ep(ep);
1234 musb = musb_ep->musb;
1235
1236 request = to_musb_request(req);
1237 request->musb = musb;
1238
1239 if (request->ep != musb_ep)
1240 return -EINVAL;
1241
1242 DBG(4, "<== to %s request=%p\n", ep->name, req);
1243
1244 /* request is mine now... */
1245 request->request.actual = 0;
1246 request->request.status = -EINPROGRESS;
1247 request->epnum = musb_ep->current_epnum;
1248 request->tx = musb_ep->is_in;
1249
1250 map_dma_buffer(request, musb, musb_ep);
1251
1252 spin_lock_irqsave(&musb->lock, lockflags);
1253
1254 /* don't queue if the ep is down */
1255 if (!musb_ep->desc) {
1256 DBG(4, "req %p queued to %s while ep %s\n",
1257 req, ep->name, "disabled");
1258 status = -ESHUTDOWN;
1259 goto cleanup;
1260 }
1261
1262 /* add request to the list */
1263 list_add_tail(&request->list, &musb_ep->req_list);
1264
1265 /* it this is the head of the queue, start i/o ... */
1266 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1267 musb_ep_restart(musb, request);
1268
1269 cleanup:
1270 spin_unlock_irqrestore(&musb->lock, lockflags);
1271 return status;
1272 }
1273
1274 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1275 {
1276 struct musb_ep *musb_ep = to_musb_ep(ep);
1277 struct musb_request *req = to_musb_request(request);
1278 struct musb_request *r;
1279 unsigned long flags;
1280 int status = 0;
1281 struct musb *musb = musb_ep->musb;
1282
1283 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1284 return -EINVAL;
1285
1286 spin_lock_irqsave(&musb->lock, flags);
1287
1288 list_for_each_entry(r, &musb_ep->req_list, list) {
1289 if (r == req)
1290 break;
1291 }
1292 if (r != req) {
1293 DBG(3, "request %p not queued to %s\n", request, ep->name);
1294 status = -EINVAL;
1295 goto done;
1296 }
1297
1298 /* if the hardware doesn't have the request, easy ... */
1299 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1300 musb_g_giveback(musb_ep, request, -ECONNRESET);
1301
1302 /* ... else abort the dma transfer ... */
1303 else if (is_dma_capable() && musb_ep->dma) {
1304 struct dma_controller *c = musb->dma_controller;
1305
1306 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1307 if (c->channel_abort)
1308 status = c->channel_abort(musb_ep->dma);
1309 else
1310 status = -EBUSY;
1311 if (status == 0)
1312 musb_g_giveback(musb_ep, request, -ECONNRESET);
1313 } else {
1314 /* NOTE: by sticking to easily tested hardware/driver states,
1315 * we leave counting of in-flight packets imprecise.
1316 */
1317 musb_g_giveback(musb_ep, request, -ECONNRESET);
1318 }
1319
1320 done:
1321 spin_unlock_irqrestore(&musb->lock, flags);
1322 return status;
1323 }
1324
1325 /*
1326 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1327 * data but will queue requests.
1328 *
1329 * exported to ep0 code
1330 */
1331 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1332 {
1333 struct musb_ep *musb_ep = to_musb_ep(ep);
1334 u8 epnum = musb_ep->current_epnum;
1335 struct musb *musb = musb_ep->musb;
1336 void __iomem *epio = musb->endpoints[epnum].regs;
1337 void __iomem *mbase;
1338 unsigned long flags;
1339 u16 csr;
1340 struct musb_request *request;
1341 int status = 0;
1342
1343 if (!ep)
1344 return -EINVAL;
1345 mbase = musb->mregs;
1346
1347 spin_lock_irqsave(&musb->lock, flags);
1348
1349 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1350 status = -EINVAL;
1351 goto done;
1352 }
1353
1354 musb_ep_select(mbase, epnum);
1355
1356 request = next_request(musb_ep);
1357 if (value) {
1358 if (request) {
1359 DBG(3, "request in progress, cannot halt %s\n",
1360 ep->name);
1361 status = -EAGAIN;
1362 goto done;
1363 }
1364 /* Cannot portably stall with non-empty FIFO */
1365 if (musb_ep->is_in) {
1366 csr = musb_readw(epio, MUSB_TXCSR);
1367 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1368 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1369 status = -EAGAIN;
1370 goto done;
1371 }
1372 }
1373 } else
1374 musb_ep->wedged = 0;
1375
1376 /* set/clear the stall and toggle bits */
1377 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1378 if (musb_ep->is_in) {
1379 csr = musb_readw(epio, MUSB_TXCSR);
1380 csr |= MUSB_TXCSR_P_WZC_BITS
1381 | MUSB_TXCSR_CLRDATATOG;
1382 if (value)
1383 csr |= MUSB_TXCSR_P_SENDSTALL;
1384 else
1385 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1386 | MUSB_TXCSR_P_SENTSTALL);
1387 csr &= ~MUSB_TXCSR_TXPKTRDY;
1388 musb_writew(epio, MUSB_TXCSR, csr);
1389 } else {
1390 csr = musb_readw(epio, MUSB_RXCSR);
1391 csr |= MUSB_RXCSR_P_WZC_BITS
1392 | MUSB_RXCSR_FLUSHFIFO
1393 | MUSB_RXCSR_CLRDATATOG;
1394 if (value)
1395 csr |= MUSB_RXCSR_P_SENDSTALL;
1396 else
1397 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1398 | MUSB_RXCSR_P_SENTSTALL);
1399 musb_writew(epio, MUSB_RXCSR, csr);
1400 }
1401
1402 /* maybe start the first request in the queue */
1403 if (!musb_ep->busy && !value && request) {
1404 DBG(3, "restarting the request\n");
1405 musb_ep_restart(musb, request);
1406 }
1407
1408 done:
1409 spin_unlock_irqrestore(&musb->lock, flags);
1410 return status;
1411 }
1412
1413 /*
1414 * Sets the halt feature with the clear requests ignored
1415 */
1416 static int musb_gadget_set_wedge(struct usb_ep *ep)
1417 {
1418 struct musb_ep *musb_ep = to_musb_ep(ep);
1419
1420 if (!ep)
1421 return -EINVAL;
1422
1423 musb_ep->wedged = 1;
1424
1425 return usb_ep_set_halt(ep);
1426 }
1427
1428 static int musb_gadget_fifo_status(struct usb_ep *ep)
1429 {
1430 struct musb_ep *musb_ep = to_musb_ep(ep);
1431 void __iomem *epio = musb_ep->hw_ep->regs;
1432 int retval = -EINVAL;
1433
1434 if (musb_ep->desc && !musb_ep->is_in) {
1435 struct musb *musb = musb_ep->musb;
1436 int epnum = musb_ep->current_epnum;
1437 void __iomem *mbase = musb->mregs;
1438 unsigned long flags;
1439
1440 spin_lock_irqsave(&musb->lock, flags);
1441
1442 musb_ep_select(mbase, epnum);
1443 /* FIXME return zero unless RXPKTRDY is set */
1444 retval = musb_readw(epio, MUSB_RXCOUNT);
1445
1446 spin_unlock_irqrestore(&musb->lock, flags);
1447 }
1448 return retval;
1449 }
1450
1451 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1452 {
1453 struct musb_ep *musb_ep = to_musb_ep(ep);
1454 struct musb *musb = musb_ep->musb;
1455 u8 epnum = musb_ep->current_epnum;
1456 void __iomem *epio = musb->endpoints[epnum].regs;
1457 void __iomem *mbase;
1458 unsigned long flags;
1459 u16 csr, int_txe;
1460
1461 mbase = musb->mregs;
1462
1463 spin_lock_irqsave(&musb->lock, flags);
1464 musb_ep_select(mbase, (u8) epnum);
1465
1466 /* disable interrupts */
1467 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1468 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1469
1470 if (musb_ep->is_in) {
1471 csr = musb_readw(epio, MUSB_TXCSR);
1472 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1473 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1474 musb_writew(epio, MUSB_TXCSR, csr);
1475 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1476 musb_writew(epio, MUSB_TXCSR, csr);
1477 }
1478 } else {
1479 csr = musb_readw(epio, MUSB_RXCSR);
1480 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1481 musb_writew(epio, MUSB_RXCSR, csr);
1482 musb_writew(epio, MUSB_RXCSR, csr);
1483 }
1484
1485 /* re-enable interrupt */
1486 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1487 spin_unlock_irqrestore(&musb->lock, flags);
1488 }
1489
1490 static const struct usb_ep_ops musb_ep_ops = {
1491 .enable = musb_gadget_enable,
1492 .disable = musb_gadget_disable,
1493 .alloc_request = musb_alloc_request,
1494 .free_request = musb_free_request,
1495 .queue = musb_gadget_queue,
1496 .dequeue = musb_gadget_dequeue,
1497 .set_halt = musb_gadget_set_halt,
1498 .set_wedge = musb_gadget_set_wedge,
1499 .fifo_status = musb_gadget_fifo_status,
1500 .fifo_flush = musb_gadget_fifo_flush
1501 };
1502
1503 /* ----------------------------------------------------------------------- */
1504
1505 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1506 {
1507 struct musb *musb = gadget_to_musb(gadget);
1508
1509 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1510 }
1511
1512 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1513 {
1514 struct musb *musb = gadget_to_musb(gadget);
1515 void __iomem *mregs = musb->mregs;
1516 unsigned long flags;
1517 int status = -EINVAL;
1518 u8 power, devctl;
1519 int retries;
1520
1521 spin_lock_irqsave(&musb->lock, flags);
1522
1523 switch (musb->xceiv->state) {
1524 case OTG_STATE_B_PERIPHERAL:
1525 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1526 * that's part of the standard usb 1.1 state machine, and
1527 * doesn't affect OTG transitions.
1528 */
1529 if (musb->may_wakeup && musb->is_suspended)
1530 break;
1531 goto done;
1532 case OTG_STATE_B_IDLE:
1533 /* Start SRP ... OTG not required. */
1534 devctl = musb_readb(mregs, MUSB_DEVCTL);
1535 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1536 devctl |= MUSB_DEVCTL_SESSION;
1537 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1538 devctl = musb_readb(mregs, MUSB_DEVCTL);
1539 retries = 100;
1540 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1541 devctl = musb_readb(mregs, MUSB_DEVCTL);
1542 if (retries-- < 1)
1543 break;
1544 }
1545 retries = 10000;
1546 while (devctl & MUSB_DEVCTL_SESSION) {
1547 devctl = musb_readb(mregs, MUSB_DEVCTL);
1548 if (retries-- < 1)
1549 break;
1550 }
1551
1552 /* Block idling for at least 1s */
1553 musb_platform_try_idle(musb,
1554 jiffies + msecs_to_jiffies(1 * HZ));
1555
1556 status = 0;
1557 goto done;
1558 default:
1559 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1560 goto done;
1561 }
1562
1563 status = 0;
1564
1565 power = musb_readb(mregs, MUSB_POWER);
1566 power |= MUSB_POWER_RESUME;
1567 musb_writeb(mregs, MUSB_POWER, power);
1568 DBG(2, "issue wakeup\n");
1569
1570 /* FIXME do this next chunk in a timer callback, no udelay */
1571 mdelay(2);
1572
1573 power = musb_readb(mregs, MUSB_POWER);
1574 power &= ~MUSB_POWER_RESUME;
1575 musb_writeb(mregs, MUSB_POWER, power);
1576 done:
1577 spin_unlock_irqrestore(&musb->lock, flags);
1578 return status;
1579 }
1580
1581 static int
1582 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1583 {
1584 struct musb *musb = gadget_to_musb(gadget);
1585
1586 musb->is_self_powered = !!is_selfpowered;
1587 return 0;
1588 }
1589
1590 static void musb_pullup(struct musb *musb, int is_on)
1591 {
1592 u8 power;
1593
1594 power = musb_readb(musb->mregs, MUSB_POWER);
1595 if (is_on)
1596 power |= MUSB_POWER_SOFTCONN;
1597 else
1598 power &= ~MUSB_POWER_SOFTCONN;
1599
1600 /* FIXME if on, HdrcStart; if off, HdrcStop */
1601
1602 DBG(3, "gadget %s D+ pullup %s\n",
1603 musb->gadget_driver->function, is_on ? "on" : "off");
1604 musb_writeb(musb->mregs, MUSB_POWER, power);
1605 }
1606
1607 #if 0
1608 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1609 {
1610 DBG(2, "<= %s =>\n", __func__);
1611
1612 /*
1613 * FIXME iff driver's softconnect flag is set (as it is during probe,
1614 * though that can clear it), just musb_pullup().
1615 */
1616
1617 return -EINVAL;
1618 }
1619 #endif
1620
1621 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1622 {
1623 struct musb *musb = gadget_to_musb(gadget);
1624
1625 if (!musb->xceiv->set_power)
1626 return -EOPNOTSUPP;
1627 return otg_set_power(musb->xceiv, mA);
1628 }
1629
1630 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1631 {
1632 struct musb *musb = gadget_to_musb(gadget);
1633 unsigned long flags;
1634
1635 is_on = !!is_on;
1636
1637 /* NOTE: this assumes we are sensing vbus; we'd rather
1638 * not pullup unless the B-session is active.
1639 */
1640 spin_lock_irqsave(&musb->lock, flags);
1641 if (is_on != musb->softconnect) {
1642 musb->softconnect = is_on;
1643 musb_pullup(musb, is_on);
1644 }
1645 spin_unlock_irqrestore(&musb->lock, flags);
1646 return 0;
1647 }
1648
1649 static const struct usb_gadget_ops musb_gadget_operations = {
1650 .get_frame = musb_gadget_get_frame,
1651 .wakeup = musb_gadget_wakeup,
1652 .set_selfpowered = musb_gadget_set_self_powered,
1653 /* .vbus_session = musb_gadget_vbus_session, */
1654 .vbus_draw = musb_gadget_vbus_draw,
1655 .pullup = musb_gadget_pullup,
1656 };
1657
1658 /* ----------------------------------------------------------------------- */
1659
1660 /* Registration */
1661
1662 /* Only this registration code "knows" the rule (from USB standards)
1663 * about there being only one external upstream port. It assumes
1664 * all peripheral ports are external...
1665 */
1666 static struct musb *the_gadget;
1667
1668 static void musb_gadget_release(struct device *dev)
1669 {
1670 /* kref_put(WHAT) */
1671 dev_dbg(dev, "%s\n", __func__);
1672 }
1673
1674
1675 static void __init
1676 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1677 {
1678 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1679
1680 memset(ep, 0, sizeof *ep);
1681
1682 ep->current_epnum = epnum;
1683 ep->musb = musb;
1684 ep->hw_ep = hw_ep;
1685 ep->is_in = is_in;
1686
1687 INIT_LIST_HEAD(&ep->req_list);
1688
1689 sprintf(ep->name, "ep%d%s", epnum,
1690 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1691 is_in ? "in" : "out"));
1692 ep->end_point.name = ep->name;
1693 INIT_LIST_HEAD(&ep->end_point.ep_list);
1694 if (!epnum) {
1695 ep->end_point.maxpacket = 64;
1696 ep->end_point.ops = &musb_g_ep0_ops;
1697 musb->g.ep0 = &ep->end_point;
1698 } else {
1699 if (is_in)
1700 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1701 else
1702 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1703 ep->end_point.ops = &musb_ep_ops;
1704 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1705 }
1706 }
1707
1708 /*
1709 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1710 * to the rest of the driver state.
1711 */
1712 static inline void __init musb_g_init_endpoints(struct musb *musb)
1713 {
1714 u8 epnum;
1715 struct musb_hw_ep *hw_ep;
1716 unsigned count = 0;
1717
1718 /* initialize endpoint list just once */
1719 INIT_LIST_HEAD(&(musb->g.ep_list));
1720
1721 for (epnum = 0, hw_ep = musb->endpoints;
1722 epnum < musb->nr_endpoints;
1723 epnum++, hw_ep++) {
1724 if (hw_ep->is_shared_fifo /* || !epnum */) {
1725 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1726 count++;
1727 } else {
1728 if (hw_ep->max_packet_sz_tx) {
1729 init_peripheral_ep(musb, &hw_ep->ep_in,
1730 epnum, 1);
1731 count++;
1732 }
1733 if (hw_ep->max_packet_sz_rx) {
1734 init_peripheral_ep(musb, &hw_ep->ep_out,
1735 epnum, 0);
1736 count++;
1737 }
1738 }
1739 }
1740 }
1741
1742 /* called once during driver setup to initialize and link into
1743 * the driver model; memory is zeroed.
1744 */
1745 int __init musb_gadget_setup(struct musb *musb)
1746 {
1747 int status;
1748
1749 /* REVISIT minor race: if (erroneously) setting up two
1750 * musb peripherals at the same time, only the bus lock
1751 * is probably held.
1752 */
1753 if (the_gadget)
1754 return -EBUSY;
1755 the_gadget = musb;
1756
1757 musb->g.ops = &musb_gadget_operations;
1758 musb->g.is_dualspeed = 1;
1759 musb->g.speed = USB_SPEED_UNKNOWN;
1760
1761 /* this "gadget" abstracts/virtualizes the controller */
1762 dev_set_name(&musb->g.dev, "gadget");
1763 musb->g.dev.parent = musb->controller;
1764 musb->g.dev.dma_mask = musb->controller->dma_mask;
1765 musb->g.dev.release = musb_gadget_release;
1766 musb->g.name = musb_driver_name;
1767
1768 if (is_otg_enabled(musb))
1769 musb->g.is_otg = 1;
1770
1771 musb_g_init_endpoints(musb);
1772
1773 musb->is_active = 0;
1774 musb_platform_try_idle(musb, 0);
1775
1776 status = device_register(&musb->g.dev);
1777 if (status != 0) {
1778 put_device(&musb->g.dev);
1779 the_gadget = NULL;
1780 }
1781 return status;
1782 }
1783
1784 void musb_gadget_cleanup(struct musb *musb)
1785 {
1786 if (musb != the_gadget)
1787 return;
1788
1789 device_unregister(&musb->g.dev);
1790 the_gadget = NULL;
1791 }
1792
1793 /*
1794 * Register the gadget driver. Used by gadget drivers when
1795 * registering themselves with the controller.
1796 *
1797 * -EINVAL something went wrong (not driver)
1798 * -EBUSY another gadget is already using the controller
1799 * -ENOMEM no memory to perform the operation
1800 *
1801 * @param driver the gadget driver
1802 * @param bind the driver's bind function
1803 * @return <0 if error, 0 if everything is fine
1804 */
1805 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1806 int (*bind)(struct usb_gadget *))
1807 {
1808 struct musb *musb = the_gadget;
1809 unsigned long flags;
1810 int retval = -EINVAL;
1811
1812 if (!driver
1813 || driver->speed != USB_SPEED_HIGH
1814 || !bind || !driver->setup)
1815 goto err0;
1816
1817 /* driver must be initialized to support peripheral mode */
1818 if (!musb) {
1819 DBG(1, "no dev??\n");
1820 retval = -ENODEV;
1821 goto err0;
1822 }
1823
1824 pm_runtime_get_sync(musb->controller);
1825
1826 DBG(3, "registering driver %s\n", driver->function);
1827
1828 if (musb->gadget_driver) {
1829 DBG(1, "%s is already bound to %s\n",
1830 musb_driver_name,
1831 musb->gadget_driver->driver.name);
1832 retval = -EBUSY;
1833 goto err0;
1834 }
1835
1836 spin_lock_irqsave(&musb->lock, flags);
1837 musb->gadget_driver = driver;
1838 musb->g.dev.driver = &driver->driver;
1839 driver->driver.bus = NULL;
1840 musb->softconnect = 1;
1841 spin_unlock_irqrestore(&musb->lock, flags);
1842
1843 retval = bind(&musb->g);
1844 if (retval) {
1845 DBG(3, "bind to driver %s failed --> %d\n",
1846 driver->driver.name, retval);
1847 goto err1;
1848 }
1849
1850 spin_lock_irqsave(&musb->lock, flags);
1851
1852 otg_set_peripheral(musb->xceiv, &musb->g);
1853 musb->xceiv->state = OTG_STATE_B_IDLE;
1854 musb->is_active = 1;
1855
1856 /*
1857 * FIXME this ignores the softconnect flag. Drivers are
1858 * allowed hold the peripheral inactive until for example
1859 * userspace hooks up printer hardware or DSP codecs, so
1860 * hosts only see fully functional devices.
1861 */
1862
1863 if (!is_otg_enabled(musb))
1864 musb_start(musb);
1865
1866 otg_set_peripheral(musb->xceiv, &musb->g);
1867
1868 spin_unlock_irqrestore(&musb->lock, flags);
1869
1870 if (is_otg_enabled(musb)) {
1871 struct usb_hcd *hcd = musb_to_hcd(musb);
1872
1873 DBG(3, "OTG startup...\n");
1874
1875 /* REVISIT: funcall to other code, which also
1876 * handles power budgeting ... this way also
1877 * ensures HdrcStart is indirectly called.
1878 */
1879 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1880 if (retval < 0) {
1881 DBG(1, "add_hcd failed, %d\n", retval);
1882 goto err2;
1883 }
1884
1885 if ((musb->xceiv->last_event == USB_EVENT_ID)
1886 && musb->xceiv->set_vbus)
1887 otg_set_vbus(musb->xceiv, 1);
1888
1889 hcd->self.uses_pio_for_control = 1;
1890
1891 if (musb->xceiv->last_event == USB_EVENT_NONE)
1892 pm_runtime_put(musb->controller);
1893
1894 }
1895
1896 return 0;
1897
1898 err2:
1899 if (!is_otg_enabled(musb))
1900 musb_stop(musb);
1901
1902 err1:
1903 musb->gadget_driver = NULL;
1904 musb->g.dev.driver = NULL;
1905
1906 err0:
1907 return retval;
1908 }
1909 EXPORT_SYMBOL(usb_gadget_probe_driver);
1910
1911 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1912 {
1913 int i;
1914 struct musb_hw_ep *hw_ep;
1915
1916 /* don't disconnect if it's not connected */
1917 if (musb->g.speed == USB_SPEED_UNKNOWN)
1918 driver = NULL;
1919 else
1920 musb->g.speed = USB_SPEED_UNKNOWN;
1921
1922 /* deactivate the hardware */
1923 if (musb->softconnect) {
1924 musb->softconnect = 0;
1925 musb_pullup(musb, 0);
1926 }
1927 musb_stop(musb);
1928
1929 /* killing any outstanding requests will quiesce the driver;
1930 * then report disconnect
1931 */
1932 if (driver) {
1933 for (i = 0, hw_ep = musb->endpoints;
1934 i < musb->nr_endpoints;
1935 i++, hw_ep++) {
1936 musb_ep_select(musb->mregs, i);
1937 if (hw_ep->is_shared_fifo /* || !epnum */) {
1938 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1939 } else {
1940 if (hw_ep->max_packet_sz_tx)
1941 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1942 if (hw_ep->max_packet_sz_rx)
1943 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1944 }
1945 }
1946
1947 spin_unlock(&musb->lock);
1948 driver->disconnect(&musb->g);
1949 spin_lock(&musb->lock);
1950 }
1951 }
1952
1953 /*
1954 * Unregister the gadget driver. Used by gadget drivers when
1955 * unregistering themselves from the controller.
1956 *
1957 * @param driver the gadget driver to unregister
1958 */
1959 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1960 {
1961 struct musb *musb = the_gadget;
1962 unsigned long flags;
1963
1964 if (!driver || !driver->unbind || !musb)
1965 return -EINVAL;
1966
1967 if (!musb->gadget_driver)
1968 return -EINVAL;
1969
1970 if (musb->xceiv->last_event == USB_EVENT_NONE)
1971 pm_runtime_get_sync(musb->controller);
1972
1973 /*
1974 * REVISIT always use otg_set_peripheral() here too;
1975 * this needs to shut down the OTG engine.
1976 */
1977
1978 spin_lock_irqsave(&musb->lock, flags);
1979
1980 #ifdef CONFIG_USB_MUSB_OTG
1981 musb_hnp_stop(musb);
1982 #endif
1983
1984 (void) musb_gadget_vbus_draw(&musb->g, 0);
1985
1986 musb->xceiv->state = OTG_STATE_UNDEFINED;
1987 stop_activity(musb, driver);
1988 otg_set_peripheral(musb->xceiv, NULL);
1989
1990 DBG(3, "unregistering driver %s\n", driver->function);
1991
1992 spin_unlock_irqrestore(&musb->lock, flags);
1993 driver->unbind(&musb->g);
1994 spin_lock_irqsave(&musb->lock, flags);
1995
1996 musb->gadget_driver = NULL;
1997 musb->g.dev.driver = NULL;
1998
1999 musb->is_active = 0;
2000 musb_platform_try_idle(musb, 0);
2001 spin_unlock_irqrestore(&musb->lock, flags);
2002
2003 if (is_otg_enabled(musb)) {
2004 usb_remove_hcd(musb_to_hcd(musb));
2005 /* FIXME we need to be able to register another
2006 * gadget driver here and have everything work;
2007 * that currently misbehaves.
2008 */
2009 }
2010
2011 if (!is_otg_enabled(musb))
2012 musb_stop(musb);
2013
2014 pm_runtime_put(musb->controller);
2015
2016 return 0;
2017 }
2018 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2019
2020
2021 /* ----------------------------------------------------------------------- */
2022
2023 /* lifecycle operations called through plat_uds.c */
2024
2025 void musb_g_resume(struct musb *musb)
2026 {
2027 musb->is_suspended = 0;
2028 switch (musb->xceiv->state) {
2029 case OTG_STATE_B_IDLE:
2030 break;
2031 case OTG_STATE_B_WAIT_ACON:
2032 case OTG_STATE_B_PERIPHERAL:
2033 musb->is_active = 1;
2034 if (musb->gadget_driver && musb->gadget_driver->resume) {
2035 spin_unlock(&musb->lock);
2036 musb->gadget_driver->resume(&musb->g);
2037 spin_lock(&musb->lock);
2038 }
2039 break;
2040 default:
2041 WARNING("unhandled RESUME transition (%s)\n",
2042 otg_state_string(musb));
2043 }
2044 }
2045
2046 /* called when SOF packets stop for 3+ msec */
2047 void musb_g_suspend(struct musb *musb)
2048 {
2049 u8 devctl;
2050
2051 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2052 DBG(3, "devctl %02x\n", devctl);
2053
2054 switch (musb->xceiv->state) {
2055 case OTG_STATE_B_IDLE:
2056 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2057 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2058 break;
2059 case OTG_STATE_B_PERIPHERAL:
2060 musb->is_suspended = 1;
2061 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2062 spin_unlock(&musb->lock);
2063 musb->gadget_driver->suspend(&musb->g);
2064 spin_lock(&musb->lock);
2065 }
2066 break;
2067 default:
2068 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2069 * A_PERIPHERAL may need care too
2070 */
2071 WARNING("unhandled SUSPEND transition (%s)\n",
2072 otg_state_string(musb));
2073 }
2074 }
2075
2076 /* Called during SRP */
2077 void musb_g_wakeup(struct musb *musb)
2078 {
2079 musb_gadget_wakeup(&musb->g);
2080 }
2081
2082 /* called when VBUS drops below session threshold, and in other cases */
2083 void musb_g_disconnect(struct musb *musb)
2084 {
2085 void __iomem *mregs = musb->mregs;
2086 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2087
2088 DBG(3, "devctl %02x\n", devctl);
2089
2090 /* clear HR */
2091 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2092
2093 /* don't draw vbus until new b-default session */
2094 (void) musb_gadget_vbus_draw(&musb->g, 0);
2095
2096 musb->g.speed = USB_SPEED_UNKNOWN;
2097 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2098 spin_unlock(&musb->lock);
2099 musb->gadget_driver->disconnect(&musb->g);
2100 spin_lock(&musb->lock);
2101 }
2102
2103 switch (musb->xceiv->state) {
2104 default:
2105 #ifdef CONFIG_USB_MUSB_OTG
2106 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
2107 otg_state_string(musb));
2108 musb->xceiv->state = OTG_STATE_A_IDLE;
2109 MUSB_HST_MODE(musb);
2110 break;
2111 case OTG_STATE_A_PERIPHERAL:
2112 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2113 MUSB_HST_MODE(musb);
2114 break;
2115 case OTG_STATE_B_WAIT_ACON:
2116 case OTG_STATE_B_HOST:
2117 #endif
2118 case OTG_STATE_B_PERIPHERAL:
2119 case OTG_STATE_B_IDLE:
2120 musb->xceiv->state = OTG_STATE_B_IDLE;
2121 break;
2122 case OTG_STATE_B_SRP_INIT:
2123 break;
2124 }
2125
2126 musb->is_active = 0;
2127 }
2128
2129 void musb_g_reset(struct musb *musb)
2130 __releases(musb->lock)
2131 __acquires(musb->lock)
2132 {
2133 void __iomem *mbase = musb->mregs;
2134 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2135 u8 power;
2136
2137 DBG(3, "<== %s addr=%x driver '%s'\n",
2138 (devctl & MUSB_DEVCTL_BDEVICE)
2139 ? "B-Device" : "A-Device",
2140 musb_readb(mbase, MUSB_FADDR),
2141 musb->gadget_driver
2142 ? musb->gadget_driver->driver.name
2143 : NULL
2144 );
2145
2146 /* report disconnect, if we didn't already (flushing EP state) */
2147 if (musb->g.speed != USB_SPEED_UNKNOWN)
2148 musb_g_disconnect(musb);
2149
2150 /* clear HR */
2151 else if (devctl & MUSB_DEVCTL_HR)
2152 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2153
2154
2155 /* what speed did we negotiate? */
2156 power = musb_readb(mbase, MUSB_POWER);
2157 musb->g.speed = (power & MUSB_POWER_HSMODE)
2158 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2159
2160 /* start in USB_STATE_DEFAULT */
2161 musb->is_active = 1;
2162 musb->is_suspended = 0;
2163 MUSB_DEV_MODE(musb);
2164 musb->address = 0;
2165 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2166
2167 musb->may_wakeup = 0;
2168 musb->g.b_hnp_enable = 0;
2169 musb->g.a_alt_hnp_support = 0;
2170 musb->g.a_hnp_support = 0;
2171
2172 /* Normal reset, as B-Device;
2173 * or else after HNP, as A-Device
2174 */
2175 if (devctl & MUSB_DEVCTL_BDEVICE) {
2176 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2177 musb->g.is_a_peripheral = 0;
2178 } else if (is_otg_enabled(musb)) {
2179 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2180 musb->g.is_a_peripheral = 1;
2181 } else
2182 WARN_ON(1);
2183
2184 /* start with default limits on VBUS power draw */
2185 (void) musb_gadget_vbus_draw(&musb->g,
2186 is_otg_enabled(musb) ? 8 : 100);
2187 }