?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
OMAPDSS: VENC: fix NULL pointer dereference in DSS2 VENC sysfs debug attr on OMAP4
[zen-stable.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_link.c
blob2091e5dbbcdd9f50d0d0dec422cd2e1c3aac2d4f
1 /* Copyright 2008-2011 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
26
27 #include "bnx2x.h"
28 #include "bnx2x_cmn.h"
29
30 /********************************************************/
31 #define ETH_HLEN 14
32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34 #define ETH_MIN_PACKET_SIZE 60
35 #define ETH_MAX_PACKET_SIZE 1500
36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
37 #define MDIO_ACCESS_TIMEOUT 1000
38 #define BMAC_CONTROL_RX_ENABLE 2
39 #define WC_LANE_MAX 4
40 #define I2C_SWITCH_WIDTH 2
41 #define I2C_BSC0 0
42 #define I2C_BSC1 1
43 #define I2C_WA_RETRY_CNT 3
44 #define MCPR_IMC_COMMAND_READ_OP 1
45 #define MCPR_IMC_COMMAND_WRITE_OP 2
46
47 /* LED Blink rate that will achieve ~15.9Hz */
48 #define LED_BLINK_RATE_VAL_E3 354
49 #define LED_BLINK_RATE_VAL_E1X_E2 480
50 /***********************************************************/
51 /* Shortcut definitions */
52 /***********************************************************/
53
54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
55
56 #define NIG_STATUS_EMAC0_MI_INT \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
58 #define NIG_STATUS_XGXS0_LINK10G \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
60 #define NIG_STATUS_XGXS0_LINK_STATUS \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
64 #define NIG_STATUS_SERDES0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
66 #define NIG_MASK_MI_INT \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
68 #define NIG_MASK_XGXS0_LINK10G \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
70 #define NIG_MASK_XGXS0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
72 #define NIG_MASK_SERDES0_LINK_STATUS \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
74
75 #define MDIO_AN_CL73_OR_37_COMPLETE \
76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
78
79 #define XGXS_RESET_BITS \
80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
85
86 #define SERDES_RESET_BITS \
87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
91
92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
95 #define AUTONEG_PARALLEL \
96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
97 #define AUTONEG_SGMII_FIBER_AUTODET \
98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
100
101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
105 #define GP_STATUS_SPEED_MASK \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
113 #define GP_STATUS_10G_HIG \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
115 #define GP_STATUS_10G_CX4 \
116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
118 #define GP_STATUS_10G_KX4 \
119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
124 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
125 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
126 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
127 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
128 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
129 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
130 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
131 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
132 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
133 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
134 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
135 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
136 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
137 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
138 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
139
140
141
142 /* */
143 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
144 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
145 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
146
147
148 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
149 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
150 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
151 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152
153 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156
157 #define SFP_EEPROM_OPTIONS_ADDR 0x40
158 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
159 #define SFP_EEPROM_OPTIONS_SIZE 2
160
161 #define EDC_MODE_LINEAR 0x0022
162 #define EDC_MODE_LIMITING 0x0044
163 #define EDC_MODE_PASSIVE_DAC 0x0055
164
165 /* BRB default for class 0 E2 */
166 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
167 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
168 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
169 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
170
171 /* BRB thresholds for E2*/
172 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
173 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
174
175 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
176 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
177
178 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
179 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
180
181 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
182 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
183
184 /* BRB default for class 0 E3A0 */
185 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
186 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
187 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
188 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
189
190 /* BRB thresholds for E3A0 */
191 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
192 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
193
194 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
195 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
196
197 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
198 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
199
200 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
201 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
202
203 /* BRB default for E3B0 */
204 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
205 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
206 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
207 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
208
209 /* BRB thresholds for E3B0 2 port mode*/
210 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
211 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
212
213 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
214 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
215
216 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
217 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
218
219 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
220 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
221
222 /* only for E3B0*/
223 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
224 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
225
226 /* Lossy +Lossless GUARANTIED == GUART */
227 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
228 /* Lossless +Lossless*/
229 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
230 /* Lossy +Lossy*/
231 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
232
233 /* Lossy +Lossless*/
234 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
235 /* Lossless +Lossless*/
236 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
237 /* Lossy +Lossy*/
238 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
239 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
240
241 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
242 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
243
244 /* BRB thresholds for E3B0 4 port mode */
245 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
246 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
247
248 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
249 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
250
251 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
252 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
253
254 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
255 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
256
257 /* only for E3B0*/
258 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
259 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
260 #define PFC_E3B0_4P_LB_GUART 120
261
262 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
263 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
264
265 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
266 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
267
268 /* Pause defines*/
269 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
270 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
271 #define DEFAULT_E3B0_LB_GUART 40
272
273 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
274 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
275
276 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
277 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
278
279 /* ETS defines*/
280 #define DCBX_INVALID_COS (0xFF)
281
282 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
283 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
284 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
285 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
286 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
287
288 #define MAX_PACKET_SIZE (9700)
289 #define WC_UC_TIMEOUT 100
290 #define MAX_KR_LINK_RETRY 4
291
292 /**********************************************************/
293 /* INTERFACE */
294 /**********************************************************/
295
296 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
297 bnx2x_cl45_write(_bp, _phy, \
298 (_phy)->def_md_devad, \
299 (_bank + (_addr & 0xf)), \
300 _val)
301
302 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
303 bnx2x_cl45_read(_bp, _phy, \
304 (_phy)->def_md_devad, \
305 (_bank + (_addr & 0xf)), \
306 _val)
307
308 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
309 {
310 u32 val = REG_RD(bp, reg);
311
312 val |= bits;
313 REG_WR(bp, reg, val);
314 return val;
315 }
316
317 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
318 {
319 u32 val = REG_RD(bp, reg);
320
321 val &= ~bits;
322 REG_WR(bp, reg, val);
323 return val;
324 }
325
326 /******************************************************************/
327 /* EPIO/GPIO section */
328 /******************************************************************/
329 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
330 {
331 u32 epio_mask, gp_oenable;
332 *en = 0;
333 /* Sanity check */
334 if (epio_pin > 31) {
335 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
336 return;
337 }
338
339 epio_mask = 1 << epio_pin;
340 /* Set this EPIO to output */
341 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
342 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
343
344 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
345 }
346 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
347 {
348 u32 epio_mask, gp_output, gp_oenable;
349
350 /* Sanity check */
351 if (epio_pin > 31) {
352 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
353 return;
354 }
355 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
356 epio_mask = 1 << epio_pin;
357 /* Set this EPIO to output */
358 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
359 if (en)
360 gp_output |= epio_mask;
361 else
362 gp_output &= ~epio_mask;
363
364 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
365
366 /* Set the value for this EPIO */
367 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
368 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
369 }
370
371 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
372 {
373 if (pin_cfg == PIN_CFG_NA)
374 return;
375 if (pin_cfg >= PIN_CFG_EPIO0) {
376 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
377 } else {
378 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
379 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
380 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
381 }
382 }
383
384 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
385 {
386 if (pin_cfg == PIN_CFG_NA)
387 return -EINVAL;
388 if (pin_cfg >= PIN_CFG_EPIO0) {
389 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
390 } else {
391 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
392 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
393 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
394 }
395 return 0;
396
397 }
398 /******************************************************************/
399 /* ETS section */
400 /******************************************************************/
401 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
402 {
403 /* ETS disabled configuration*/
404 struct bnx2x *bp = params->bp;
405
406 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
407
408 /*
409 * mapping between entry priority to client number (0,1,2 -debug and
410 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
411 * 3bits client num.
412 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
413 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
414 */
415
416 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
417 /*
418 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
419 * as strict. Bits 0,1,2 - debug and management entries, 3 -
420 * COS0 entry, 4 - COS1 entry.
421 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
422 * bit4 bit3 bit2 bit1 bit0
423 * MCP and debug are strict
424 */
425
426 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
427 /* defines which entries (clients) are subjected to WFQ arbitration */
428 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
429 /*
430 * For strict priority entries defines the number of consecutive
431 * slots for the highest priority.
432 */
433 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
434 /*
435 * mapping between the CREDIT_WEIGHT registers and actual client
436 * numbers
437 */
438 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
439 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
440 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
441
442 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
443 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
444 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
445 /* ETS mode disable */
446 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
447 /*
448 * If ETS mode is enabled (there is no strict priority) defines a WFQ
449 * weight for COS0/COS1.
450 */
451 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
452 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
453 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
454 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
455 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
456 /* Defines the number of consecutive slots for the strict priority */
457 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
458 }
459 /******************************************************************************
460 * Description:
461 * Getting min_w_val will be set according to line speed .
462 *.
463 ******************************************************************************/
464 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
465 {
466 u32 min_w_val = 0;
467 /* Calculate min_w_val.*/
468 if (vars->link_up) {
469 if (vars->line_speed == SPEED_20000)
470 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
471 else
472 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
473 } else
474 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
475 /**
476 * If the link isn't up (static configuration for example ) The
477 * link will be according to 20GBPS.
478 */
479 return min_w_val;
480 }
481 /******************************************************************************
482 * Description:
483 * Getting credit upper bound form min_w_val.
484 *.
485 ******************************************************************************/
486 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
487 {
488 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
489 MAX_PACKET_SIZE);
490 return credit_upper_bound;
491 }
492 /******************************************************************************
493 * Description:
494 * Set credit upper bound for NIG.
495 *.
496 ******************************************************************************/
497 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
498 const struct link_params *params,
499 const u32 min_w_val)
500 {
501 struct bnx2x *bp = params->bp;
502 const u8 port = params->port;
503 const u32 credit_upper_bound =
504 bnx2x_ets_get_credit_upper_bound(min_w_val);
505
506 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
507 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
508 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
509 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
510 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
511 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
512 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
513 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
514 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
515 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
516 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
517 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
518
519 if (!port) {
520 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
521 credit_upper_bound);
522 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
523 credit_upper_bound);
524 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
525 credit_upper_bound);
526 }
527 }
528 /******************************************************************************
529 * Description:
530 * Will return the NIG ETS registers to init values.Except
531 * credit_upper_bound.
532 * That isn't used in this configuration (No WFQ is enabled) and will be
533 * configured acording to spec
534 *.
535 ******************************************************************************/
536 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
537 const struct link_vars *vars)
538 {
539 struct bnx2x *bp = params->bp;
540 const u8 port = params->port;
541 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
542 /**
543 * mapping between entry priority to client number (0,1,2 -debug and
544 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
545 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
546 * reset value or init tool
547 */
548 if (port) {
549 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
550 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
551 } else {
552 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
553 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
554 }
555 /**
556 * For strict priority entries defines the number of consecutive
557 * slots for the highest priority.
558 */
559 /* TODO_ETS - Should be done by reset value or init tool */
560 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
561 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
562 /**
563 * mapping between the CREDIT_WEIGHT registers and actual client
564 * numbers
565 */
566 /* TODO_ETS - Should be done by reset value or init tool */
567 if (port) {
568 /*Port 1 has 6 COS*/
569 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
570 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
571 } else {
572 /*Port 0 has 9 COS*/
573 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
574 0x43210876);
575 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
576 }
577
578 /**
579 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
580 * as strict. Bits 0,1,2 - debug and management entries, 3 -
581 * COS0 entry, 4 - COS1 entry.
582 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
583 * bit4 bit3 bit2 bit1 bit0
584 * MCP and debug are strict
585 */
586 if (port)
587 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
588 else
589 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
590 /* defines which entries (clients) are subjected to WFQ arbitration */
591 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
592 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
593
594 /**
595 * Please notice the register address are note continuous and a
596 * for here is note appropriate.In 2 port mode port0 only COS0-5
597 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
598 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
599 * are never used for WFQ
600 */
601 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
602 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
603 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
604 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
605 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
606 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
607 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
608 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
609 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
610 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
611 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
612 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
613 if (!port) {
614 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
615 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
616 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
617 }
618
619 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
620 }
621 /******************************************************************************
622 * Description:
623 * Set credit upper bound for PBF.
624 *.
625 ******************************************************************************/
626 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
627 const struct link_params *params,
628 const u32 min_w_val)
629 {
630 struct bnx2x *bp = params->bp;
631 const u32 credit_upper_bound =
632 bnx2x_ets_get_credit_upper_bound(min_w_val);
633 const u8 port = params->port;
634 u32 base_upper_bound = 0;
635 u8 max_cos = 0;
636 u8 i = 0;
637 /**
638 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
639 * port mode port1 has COS0-2 that can be used for WFQ.
640 */
641 if (!port) {
642 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
643 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
644 } else {
645 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
646 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
647 }
648
649 for (i = 0; i < max_cos; i++)
650 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
651 }
652
653 /******************************************************************************
654 * Description:
655 * Will return the PBF ETS registers to init values.Except
656 * credit_upper_bound.
657 * That isn't used in this configuration (No WFQ is enabled) and will be
658 * configured acording to spec
659 *.
660 ******************************************************************************/
661 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
662 {
663 struct bnx2x *bp = params->bp;
664 const u8 port = params->port;
665 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
666 u8 i = 0;
667 u32 base_weight = 0;
668 u8 max_cos = 0;
669
670 /**
671 * mapping between entry priority to client number 0 - COS0
672 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
673 * TODO_ETS - Should be done by reset value or init tool
674 */
675 if (port)
676 /* 0x688 (|011|0 10|00 1|000) */
677 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
678 else
679 /* (10 1|100 |011|0 10|00 1|000) */
680 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
681
682 /* TODO_ETS - Should be done by reset value or init tool */
683 if (port)
684 /* 0x688 (|011|0 10|00 1|000)*/
685 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
686 else
687 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
688 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
689
690 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
691 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
692
693
694 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
695 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
696
697 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
698 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
699 /**
700 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
701 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
702 */
703 if (!port) {
704 base_weight = PBF_REG_COS0_WEIGHT_P0;
705 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
706 } else {
707 base_weight = PBF_REG_COS0_WEIGHT_P1;
708 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
709 }
710
711 for (i = 0; i < max_cos; i++)
712 REG_WR(bp, base_weight + (0x4 * i), 0);
713
714 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
715 }
716 /******************************************************************************
717 * Description:
718 * E3B0 disable will return basicly the values to init values.
719 *.
720 ******************************************************************************/
721 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
722 const struct link_vars *vars)
723 {
724 struct bnx2x *bp = params->bp;
725
726 if (!CHIP_IS_E3B0(bp)) {
727 DP(NETIF_MSG_LINK,
728 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
729 return -EINVAL;
730 }
731
732 bnx2x_ets_e3b0_nig_disabled(params, vars);
733
734 bnx2x_ets_e3b0_pbf_disabled(params);
735
736 return 0;
737 }
738
739 /******************************************************************************
740 * Description:
741 * Disable will return basicly the values to init values.
742 *.
743 ******************************************************************************/
744 int bnx2x_ets_disabled(struct link_params *params,
745 struct link_vars *vars)
746 {
747 struct bnx2x *bp = params->bp;
748 int bnx2x_status = 0;
749
750 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
751 bnx2x_ets_e2e3a0_disabled(params);
752 else if (CHIP_IS_E3B0(bp))
753 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
754 else {
755 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
756 return -EINVAL;
757 }
758
759 return bnx2x_status;
760 }
761
762 /******************************************************************************
763 * Description
764 * Set the COS mappimg to SP and BW until this point all the COS are not
765 * set as SP or BW.
766 ******************************************************************************/
767 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
768 const struct bnx2x_ets_params *ets_params,
769 const u8 cos_sp_bitmap,
770 const u8 cos_bw_bitmap)
771 {
772 struct bnx2x *bp = params->bp;
773 const u8 port = params->port;
774 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
775 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
776 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
777 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
778
779 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
780 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
781
782 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
783 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
784
785 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
786 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
787 nig_cli_subject2wfq_bitmap);
788
789 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
790 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
791 pbf_cli_subject2wfq_bitmap);
792
793 return 0;
794 }
795
796 /******************************************************************************
797 * Description:
798 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
799 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
800 ******************************************************************************/
801 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
802 const u8 cos_entry,
803 const u32 min_w_val_nig,
804 const u32 min_w_val_pbf,
805 const u16 total_bw,
806 const u8 bw,
807 const u8 port)
808 {
809 u32 nig_reg_adress_crd_weight = 0;
810 u32 pbf_reg_adress_crd_weight = 0;
811 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
812 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
813 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
814
815 switch (cos_entry) {
816 case 0:
817 nig_reg_adress_crd_weight =
818 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
819 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
820 pbf_reg_adress_crd_weight = (port) ?
821 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
822 break;
823 case 1:
824 nig_reg_adress_crd_weight = (port) ?
825 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
826 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
827 pbf_reg_adress_crd_weight = (port) ?
828 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
829 break;
830 case 2:
831 nig_reg_adress_crd_weight = (port) ?
832 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
833 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
834
835 pbf_reg_adress_crd_weight = (port) ?
836 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
837 break;
838 case 3:
839 if (port)
840 return -EINVAL;
841 nig_reg_adress_crd_weight =
842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
843 pbf_reg_adress_crd_weight =
844 PBF_REG_COS3_WEIGHT_P0;
845 break;
846 case 4:
847 if (port)
848 return -EINVAL;
849 nig_reg_adress_crd_weight =
850 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
851 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
852 break;
853 case 5:
854 if (port)
855 return -EINVAL;
856 nig_reg_adress_crd_weight =
857 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
858 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
859 break;
860 }
861
862 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
863
864 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
865
866 return 0;
867 }
868 /******************************************************************************
869 * Description:
870 * Calculate the total BW.A value of 0 isn't legal.
871 *.
872 ******************************************************************************/
873 static int bnx2x_ets_e3b0_get_total_bw(
874 const struct link_params *params,
875 struct bnx2x_ets_params *ets_params,
876 u16 *total_bw)
877 {
878 struct bnx2x *bp = params->bp;
879 u8 cos_idx = 0;
880 u8 is_bw_cos_exist = 0;
881
882 *total_bw = 0 ;
883
884 /* Calculate total BW requested */
885 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
886 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
887 is_bw_cos_exist = 1;
888 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
889 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
890 "was set to 0\n");
891 /*
892 * This is to prevent a state when ramrods
893 * can't be sent
894 */
895 ets_params->cos[cos_idx].params.bw_params.bw
896 = 1;
897 }
898 *total_bw +=
899 ets_params->cos[cos_idx].params.bw_params.bw;
900 }
901 }
902
903 /* Check total BW is valid */
904 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
905 if (*total_bw == 0) {
906 DP(NETIF_MSG_LINK,
907 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
908 return -EINVAL;
909 }
910 DP(NETIF_MSG_LINK,
911 "bnx2x_ets_E3B0_config total BW should be 100\n");
912 /*
913 * We can handle a case whre the BW isn't 100 this can happen
914 * if the TC are joined.
915 */
916 }
917 return 0;
918 }
919
920 /******************************************************************************
921 * Description:
922 * Invalidate all the sp_pri_to_cos.
923 *.
924 ******************************************************************************/
925 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
926 {
927 u8 pri = 0;
928 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
929 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
930 }
931 /******************************************************************************
932 * Description:
933 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
934 * according to sp_pri_to_cos.
935 *.
936 ******************************************************************************/
937 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
938 u8 *sp_pri_to_cos, const u8 pri,
939 const u8 cos_entry)
940 {
941 struct bnx2x *bp = params->bp;
942 const u8 port = params->port;
943 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
944 DCBX_E3B0_MAX_NUM_COS_PORT0;
945
946 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
947 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
948 "parameter There can't be two COS's with "
949 "the same strict pri\n");
950 return -EINVAL;
951 }
952
953 if (pri > max_num_of_cos) {
954 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
955 "parameter Illegal strict priority\n");
956 return -EINVAL;
957 }
958
959 sp_pri_to_cos[pri] = cos_entry;
960 return 0;
961
962 }
963
964 /******************************************************************************
965 * Description:
966 * Returns the correct value according to COS and priority in
967 * the sp_pri_cli register.
968 *.
969 ******************************************************************************/
970 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
971 const u8 pri_set,
972 const u8 pri_offset,
973 const u8 entry_size)
974 {
975 u64 pri_cli_nig = 0;
976 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
977 (pri_set + pri_offset));
978
979 return pri_cli_nig;
980 }
981 /******************************************************************************
982 * Description:
983 * Returns the correct value according to COS and priority in the
984 * sp_pri_cli register for NIG.
985 *.
986 ******************************************************************************/
987 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
988 {
989 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
990 const u8 nig_cos_offset = 3;
991 const u8 nig_pri_offset = 3;
992
993 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
994 nig_pri_offset, 4);
995
996 }
997 /******************************************************************************
998 * Description:
999 * Returns the correct value according to COS and priority in the
1000 * sp_pri_cli register for PBF.
1001 *.
1002 ******************************************************************************/
1003 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1004 {
1005 const u8 pbf_cos_offset = 0;
1006 const u8 pbf_pri_offset = 0;
1007
1008 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1009 pbf_pri_offset, 3);
1010
1011 }
1012
1013 /******************************************************************************
1014 * Description:
1015 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1016 * according to sp_pri_to_cos.(which COS has higher priority)
1017 *.
1018 ******************************************************************************/
1019 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1020 u8 *sp_pri_to_cos)
1021 {
1022 struct bnx2x *bp = params->bp;
1023 u8 i = 0;
1024 const u8 port = params->port;
1025 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1026 u64 pri_cli_nig = 0x210;
1027 u32 pri_cli_pbf = 0x0;
1028 u8 pri_set = 0;
1029 u8 pri_bitmask = 0;
1030 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1031 DCBX_E3B0_MAX_NUM_COS_PORT0;
1032
1033 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1034
1035 /* Set all the strict priority first */
1036 for (i = 0; i < max_num_of_cos; i++) {
1037 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1038 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1039 DP(NETIF_MSG_LINK,
1040 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1041 "invalid cos entry\n");
1042 return -EINVAL;
1043 }
1044
1045 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1046 sp_pri_to_cos[i], pri_set);
1047
1048 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1049 sp_pri_to_cos[i], pri_set);
1050 pri_bitmask = 1 << sp_pri_to_cos[i];
1051 /* COS is used remove it from bitmap.*/
1052 if (!(pri_bitmask & cos_bit_to_set)) {
1053 DP(NETIF_MSG_LINK,
1054 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1055 "invalid There can't be two COS's with"
1056 " the same strict pri\n");
1057 return -EINVAL;
1058 }
1059 cos_bit_to_set &= ~pri_bitmask;
1060 pri_set++;
1061 }
1062 }
1063
1064 /* Set all the Non strict priority i= COS*/
1065 for (i = 0; i < max_num_of_cos; i++) {
1066 pri_bitmask = 1 << i;
1067 /* Check if COS was already used for SP */
1068 if (pri_bitmask & cos_bit_to_set) {
1069 /* COS wasn't used for SP */
1070 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1071 i, pri_set);
1072
1073 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1074 i, pri_set);
1075 /* COS is used remove it from bitmap.*/
1076 cos_bit_to_set &= ~pri_bitmask;
1077 pri_set++;
1078 }
1079 }
1080
1081 if (pri_set != max_num_of_cos) {
1082 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1083 "entries were set\n");
1084 return -EINVAL;
1085 }
1086
1087 if (port) {
1088 /* Only 6 usable clients*/
1089 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1090 (u32)pri_cli_nig);
1091
1092 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1093 } else {
1094 /* Only 9 usable clients*/
1095 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1096 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1097
1098 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1099 pri_cli_nig_lsb);
1100 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1101 pri_cli_nig_msb);
1102
1103 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1104 }
1105 return 0;
1106 }
1107
1108 /******************************************************************************
1109 * Description:
1110 * Configure the COS to ETS according to BW and SP settings.
1111 ******************************************************************************/
1112 int bnx2x_ets_e3b0_config(const struct link_params *params,
1113 const struct link_vars *vars,
1114 struct bnx2x_ets_params *ets_params)
1115 {
1116 struct bnx2x *bp = params->bp;
1117 int bnx2x_status = 0;
1118 const u8 port = params->port;
1119 u16 total_bw = 0;
1120 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1121 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1122 u8 cos_bw_bitmap = 0;
1123 u8 cos_sp_bitmap = 0;
1124 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1125 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1126 DCBX_E3B0_MAX_NUM_COS_PORT0;
1127 u8 cos_entry = 0;
1128
1129 if (!CHIP_IS_E3B0(bp)) {
1130 DP(NETIF_MSG_LINK,
1131 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1132 return -EINVAL;
1133 }
1134
1135 if ((ets_params->num_of_cos > max_num_of_cos)) {
1136 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1137 "isn't supported\n");
1138 return -EINVAL;
1139 }
1140
1141 /* Prepare sp strict priority parameters*/
1142 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1143
1144 /* Prepare BW parameters*/
1145 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1146 &total_bw);
1147 if (bnx2x_status) {
1148 DP(NETIF_MSG_LINK,
1149 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1150 return -EINVAL;
1151 }
1152
1153 /*
1154 * Upper bound is set according to current link speed (min_w_val
1155 * should be the same for upper bound and COS credit val).
1156 */
1157 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1158 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1159
1160
1161 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1162 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1163 cos_bw_bitmap |= (1 << cos_entry);
1164 /*
1165 * The function also sets the BW in HW(not the mappin
1166 * yet)
1167 */
1168 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1169 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1170 total_bw,
1171 ets_params->cos[cos_entry].params.bw_params.bw,
1172 port);
1173 } else if (bnx2x_cos_state_strict ==
1174 ets_params->cos[cos_entry].state){
1175 cos_sp_bitmap |= (1 << cos_entry);
1176
1177 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1178 params,
1179 sp_pri_to_cos,
1180 ets_params->cos[cos_entry].params.sp_params.pri,
1181 cos_entry);
1182
1183 } else {
1184 DP(NETIF_MSG_LINK,
1185 "bnx2x_ets_e3b0_config cos state not valid\n");
1186 return -EINVAL;
1187 }
1188 if (bnx2x_status) {
1189 DP(NETIF_MSG_LINK,
1190 "bnx2x_ets_e3b0_config set cos bw failed\n");
1191 return bnx2x_status;
1192 }
1193 }
1194
1195 /* Set SP register (which COS has higher priority) */
1196 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1197 sp_pri_to_cos);
1198
1199 if (bnx2x_status) {
1200 DP(NETIF_MSG_LINK,
1201 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1202 return bnx2x_status;
1203 }
1204
1205 /* Set client mapping of BW and strict */
1206 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1207 cos_sp_bitmap,
1208 cos_bw_bitmap);
1209
1210 if (bnx2x_status) {
1211 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1212 return bnx2x_status;
1213 }
1214 return 0;
1215 }
1216 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1217 {
1218 /* ETS disabled configuration */
1219 struct bnx2x *bp = params->bp;
1220 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1221 /*
1222 * defines which entries (clients) are subjected to WFQ arbitration
1223 * COS0 0x8
1224 * COS1 0x10
1225 */
1226 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1227 /*
1228 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1229 * client numbers (WEIGHT_0 does not actually have to represent
1230 * client 0)
1231 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1232 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1233 */
1234 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1235
1236 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1237 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1238 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1239 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1240
1241 /* ETS mode enabled*/
1242 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1243
1244 /* Defines the number of consecutive slots for the strict priority */
1245 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1246 /*
1247 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1248 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1249 * entry, 4 - COS1 entry.
1250 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1251 * bit4 bit3 bit2 bit1 bit0
1252 * MCP and debug are strict
1253 */
1254 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1255
1256 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1257 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1258 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1259 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1260 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1261 }
1262
1263 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1264 const u32 cos1_bw)
1265 {
1266 /* ETS disabled configuration*/
1267 struct bnx2x *bp = params->bp;
1268 const u32 total_bw = cos0_bw + cos1_bw;
1269 u32 cos0_credit_weight = 0;
1270 u32 cos1_credit_weight = 0;
1271
1272 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1273
1274 if ((!total_bw) ||
1275 (!cos0_bw) ||
1276 (!cos1_bw)) {
1277 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1278 return;
1279 }
1280
1281 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1282 total_bw;
1283 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1284 total_bw;
1285
1286 bnx2x_ets_bw_limit_common(params);
1287
1288 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1289 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1290
1291 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1292 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1293 }
1294
1295 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1296 {
1297 /* ETS disabled configuration*/
1298 struct bnx2x *bp = params->bp;
1299 u32 val = 0;
1300
1301 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1302 /*
1303 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1304 * as strict. Bits 0,1,2 - debug and management entries,
1305 * 3 - COS0 entry, 4 - COS1 entry.
1306 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1307 * bit4 bit3 bit2 bit1 bit0
1308 * MCP and debug are strict
1309 */
1310 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1311 /*
1312 * For strict priority entries defines the number of consecutive slots
1313 * for the highest priority.
1314 */
1315 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1316 /* ETS mode disable */
1317 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1318 /* Defines the number of consecutive slots for the strict priority */
1319 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1320
1321 /* Defines the number of consecutive slots for the strict priority */
1322 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1323
1324 /*
1325 * mapping between entry priority to client number (0,1,2 -debug and
1326 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1327 * 3bits client num.
1328 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1329 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1330 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1331 */
1332 val = (!strict_cos) ? 0x2318 : 0x22E0;
1333 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1334
1335 return 0;
1336 }
1337 /******************************************************************/
1338 /* PFC section */
1339 /******************************************************************/
1340 static void bnx2x_update_pfc_xmac(struct link_params *params,
1341 struct link_vars *vars,
1342 u8 is_lb)
1343 {
1344 struct bnx2x *bp = params->bp;
1345 u32 xmac_base;
1346 u32 pause_val, pfc0_val, pfc1_val;
1347
1348 /* XMAC base adrr */
1349 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1350
1351 /* Initialize pause and pfc registers */
1352 pause_val = 0x18000;
1353 pfc0_val = 0xFFFF8000;
1354 pfc1_val = 0x2;
1355
1356 /* No PFC support */
1357 if (!(params->feature_config_flags &
1358 FEATURE_CONFIG_PFC_ENABLED)) {
1359
1360 /*
1361 * RX flow control - Process pause frame in receive direction
1362 */
1363 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1364 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1365
1366 /*
1367 * TX flow control - Send pause packet when buffer is full
1368 */
1369 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1370 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1371 } else {/* PFC support */
1372 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1373 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1374 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1375 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1376 }
1377
1378 /* Write pause and PFC registers */
1379 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1380 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1381 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1382
1383
1384 /* Set MAC address for source TX Pause/PFC frames */
1385 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1386 ((params->mac_addr[2] << 24) |
1387 (params->mac_addr[3] << 16) |
1388 (params->mac_addr[4] << 8) |
1389 (params->mac_addr[5])));
1390 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1391 ((params->mac_addr[0] << 8) |
1392 (params->mac_addr[1])));
1393
1394 udelay(30);
1395 }
1396
1397
1398 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1399 u32 pfc_frames_sent[2],
1400 u32 pfc_frames_received[2])
1401 {
1402 /* Read pfc statistic */
1403 struct bnx2x *bp = params->bp;
1404 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1405 u32 val_xon = 0;
1406 u32 val_xoff = 0;
1407
1408 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1409
1410 /* PFC received frames */
1411 val_xoff = REG_RD(bp, emac_base +
1412 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1413 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1414 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1415 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1416
1417 pfc_frames_received[0] = val_xon + val_xoff;
1418
1419 /* PFC received sent */
1420 val_xoff = REG_RD(bp, emac_base +
1421 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1422 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1423 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1424 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1425
1426 pfc_frames_sent[0] = val_xon + val_xoff;
1427 }
1428
1429 /* Read pfc statistic*/
1430 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1431 u32 pfc_frames_sent[2],
1432 u32 pfc_frames_received[2])
1433 {
1434 /* Read pfc statistic */
1435 struct bnx2x *bp = params->bp;
1436
1437 DP(NETIF_MSG_LINK, "pfc statistic\n");
1438
1439 if (!vars->link_up)
1440 return;
1441
1442 if (vars->mac_type == MAC_TYPE_EMAC) {
1443 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1444 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1445 pfc_frames_received);
1446 }
1447 }
1448 /******************************************************************/
1449 /* MAC/PBF section */
1450 /******************************************************************/
1451 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1452 {
1453 u32 mode, emac_base;
1454 /**
1455 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1456 * (a value of 49==0x31) and make sure that the AUTO poll is off
1457 */
1458
1459 if (CHIP_IS_E2(bp))
1460 emac_base = GRCBASE_EMAC0;
1461 else
1462 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1463 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1464 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1465 EMAC_MDIO_MODE_CLOCK_CNT);
1466 if (USES_WARPCORE(bp))
1467 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1468 else
1469 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1470
1471 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1472 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1473
1474 udelay(40);
1475 }
1476 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1477 {
1478 u32 port4mode_ovwr_val;
1479 /* Check 4-port override enabled */
1480 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1481 if (port4mode_ovwr_val & (1<<0)) {
1482 /* Return 4-port mode override value */
1483 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1484 }
1485 /* Return 4-port mode from input pin */
1486 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1487 }
1488
1489 static void bnx2x_emac_init(struct link_params *params,
1490 struct link_vars *vars)
1491 {
1492 /* reset and unreset the emac core */
1493 struct bnx2x *bp = params->bp;
1494 u8 port = params->port;
1495 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1496 u32 val;
1497 u16 timeout;
1498
1499 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1500 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1501 udelay(5);
1502 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1503 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1504
1505 /* init emac - use read-modify-write */
1506 /* self clear reset */
1507 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1508 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1509
1510 timeout = 200;
1511 do {
1512 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1513 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1514 if (!timeout) {
1515 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1516 return;
1517 }
1518 timeout--;
1519 } while (val & EMAC_MODE_RESET);
1520 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1521 /* Set mac address */
1522 val = ((params->mac_addr[0] << 8) |
1523 params->mac_addr[1]);
1524 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1525
1526 val = ((params->mac_addr[2] << 24) |
1527 (params->mac_addr[3] << 16) |
1528 (params->mac_addr[4] << 8) |
1529 params->mac_addr[5]);
1530 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1531 }
1532
1533 static void bnx2x_set_xumac_nig(struct link_params *params,
1534 u16 tx_pause_en,
1535 u8 enable)
1536 {
1537 struct bnx2x *bp = params->bp;
1538
1539 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1540 enable);
1541 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1542 enable);
1543 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1544 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1545 }
1546
1547 static void bnx2x_umac_disable(struct link_params *params)
1548 {
1549 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1550 struct bnx2x *bp = params->bp;
1551 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1552 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1553 return;
1554
1555 /* Disable RX and TX */
1556 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1557 }
1558
1559 static void bnx2x_umac_enable(struct link_params *params,
1560 struct link_vars *vars, u8 lb)
1561 {
1562 u32 val;
1563 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1564 struct bnx2x *bp = params->bp;
1565 /* Reset UMAC */
1566 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1567 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1568 usleep_range(1000, 1000);
1569
1570 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1571 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1572
1573 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1574
1575 /**
1576 * This register determines on which events the MAC will assert
1577 * error on the i/f to the NIG along w/ EOP.
1578 */
1579
1580 /**
1581 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1582 * params->port*0x14, 0xfffff.
1583 */
1584 /* This register opens the gate for the UMAC despite its name */
1585 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1586
1587 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1588 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1589 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1590 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1591 switch (vars->line_speed) {
1592 case SPEED_10:
1593 val |= (0<<2);
1594 break;
1595 case SPEED_100:
1596 val |= (1<<2);
1597 break;
1598 case SPEED_1000:
1599 val |= (2<<2);
1600 break;
1601 case SPEED_2500:
1602 val |= (3<<2);
1603 break;
1604 default:
1605 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1606 vars->line_speed);
1607 break;
1608 }
1609 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1610 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1611
1612 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1613 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1614
1615 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1616 udelay(50);
1617
1618 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1619 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1620 ((params->mac_addr[2] << 24) |
1621 (params->mac_addr[3] << 16) |
1622 (params->mac_addr[4] << 8) |
1623 (params->mac_addr[5])));
1624 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1625 ((params->mac_addr[0] << 8) |
1626 (params->mac_addr[1])));
1627
1628 /* Enable RX and TX */
1629 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1630 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1631 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1632 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1633 udelay(50);
1634
1635 /* Remove SW Reset */
1636 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1637
1638 /* Check loopback mode */
1639 if (lb)
1640 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1641 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1642
1643 /*
1644 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1645 * length used by the MAC receive logic to check frames.
1646 */
1647 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1648 bnx2x_set_xumac_nig(params,
1649 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1650 vars->mac_type = MAC_TYPE_UMAC;
1651
1652 }
1653
1654 /* Define the XMAC mode */
1655 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1656 {
1657 struct bnx2x *bp = params->bp;
1658 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1659
1660 /*
1661 * In 4-port mode, need to set the mode only once, so if XMAC is
1662 * already out of reset, it means the mode has already been set,
1663 * and it must not* reset the XMAC again, since it controls both
1664 * ports of the path
1665 */
1666
1667 if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1668 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1669 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1670 DP(NETIF_MSG_LINK,
1671 "XMAC already out of reset in 4-port mode\n");
1672 return;
1673 }
1674
1675 /* Hard reset */
1676 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1677 MISC_REGISTERS_RESET_REG_2_XMAC);
1678 usleep_range(1000, 1000);
1679
1680 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1681 MISC_REGISTERS_RESET_REG_2_XMAC);
1682 if (is_port4mode) {
1683 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1684
1685 /* Set the number of ports on the system side to up to 2 */
1686 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1687
1688 /* Set the number of ports on the Warp Core to 10G */
1689 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1690 } else {
1691 /* Set the number of ports on the system side to 1 */
1692 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1693 if (max_speed == SPEED_10000) {
1694 DP(NETIF_MSG_LINK,
1695 "Init XMAC to 10G x 1 port per path\n");
1696 /* Set the number of ports on the Warp Core to 10G */
1697 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1698 } else {
1699 DP(NETIF_MSG_LINK,
1700 "Init XMAC to 20G x 2 ports per path\n");
1701 /* Set the number of ports on the Warp Core to 20G */
1702 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1703 }
1704 }
1705 /* Soft reset */
1706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1707 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1708 usleep_range(1000, 1000);
1709
1710 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1711 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1712
1713 }
1714
1715 static void bnx2x_xmac_disable(struct link_params *params)
1716 {
1717 u8 port = params->port;
1718 struct bnx2x *bp = params->bp;
1719 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1720
1721 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1722 MISC_REGISTERS_RESET_REG_2_XMAC) {
1723 /*
1724 * Send an indication to change the state in the NIG back to XON
1725 * Clearing this bit enables the next set of this bit to get
1726 * rising edge
1727 */
1728 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1729 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1730 (pfc_ctrl & ~(1<<1)));
1731 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1732 (pfc_ctrl | (1<<1)));
1733 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1734 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1735 }
1736 }
1737
1738 static int bnx2x_xmac_enable(struct link_params *params,
1739 struct link_vars *vars, u8 lb)
1740 {
1741 u32 val, xmac_base;
1742 struct bnx2x *bp = params->bp;
1743 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1744
1745 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1746
1747 bnx2x_xmac_init(params, vars->line_speed);
1748
1749 /*
1750 * This register determines on which events the MAC will assert
1751 * error on the i/f to the NIG along w/ EOP.
1752 */
1753
1754 /*
1755 * This register tells the NIG whether to send traffic to UMAC
1756 * or XMAC
1757 */
1758 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1759
1760 /* Set Max packet size */
1761 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1762
1763 /* CRC append for Tx packets */
1764 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1765
1766 /* update PFC */
1767 bnx2x_update_pfc_xmac(params, vars, 0);
1768
1769 /* Enable TX and RX */
1770 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1771
1772 /* Check loopback mode */
1773 if (lb)
1774 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1775 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1776 bnx2x_set_xumac_nig(params,
1777 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1778
1779 vars->mac_type = MAC_TYPE_XMAC;
1780
1781 return 0;
1782 }
1783
1784 static int bnx2x_emac_enable(struct link_params *params,
1785 struct link_vars *vars, u8 lb)
1786 {
1787 struct bnx2x *bp = params->bp;
1788 u8 port = params->port;
1789 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1790 u32 val;
1791
1792 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1793
1794 /* Disable BMAC */
1795 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1796 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1797
1798 /* enable emac and not bmac */
1799 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1800
1801 /* ASIC */
1802 if (vars->phy_flags & PHY_XGXS_FLAG) {
1803 u32 ser_lane = ((params->lane_config &
1804 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1805 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1806
1807 DP(NETIF_MSG_LINK, "XGXS\n");
1808 /* select the master lanes (out of 0-3) */
1809 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1810 /* select XGXS */
1811 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1812
1813 } else { /* SerDes */
1814 DP(NETIF_MSG_LINK, "SerDes\n");
1815 /* select SerDes */
1816 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1817 }
1818
1819 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1820 EMAC_RX_MODE_RESET);
1821 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1822 EMAC_TX_MODE_RESET);
1823
1824 if (CHIP_REV_IS_SLOW(bp)) {
1825 /* config GMII mode */
1826 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1827 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1828 } else { /* ASIC */
1829 /* pause enable/disable */
1830 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1831 EMAC_RX_MODE_FLOW_EN);
1832
1833 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1834 (EMAC_TX_MODE_EXT_PAUSE_EN |
1835 EMAC_TX_MODE_FLOW_EN));
1836 if (!(params->feature_config_flags &
1837 FEATURE_CONFIG_PFC_ENABLED)) {
1838 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1839 bnx2x_bits_en(bp, emac_base +
1840 EMAC_REG_EMAC_RX_MODE,
1841 EMAC_RX_MODE_FLOW_EN);
1842
1843 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1844 bnx2x_bits_en(bp, emac_base +
1845 EMAC_REG_EMAC_TX_MODE,
1846 (EMAC_TX_MODE_EXT_PAUSE_EN |
1847 EMAC_TX_MODE_FLOW_EN));
1848 } else
1849 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1850 EMAC_TX_MODE_FLOW_EN);
1851 }
1852
1853 /* KEEP_VLAN_TAG, promiscuous */
1854 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1855 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1856
1857 /*
1858 * Setting this bit causes MAC control frames (except for pause
1859 * frames) to be passed on for processing. This setting has no
1860 * affect on the operation of the pause frames. This bit effects
1861 * all packets regardless of RX Parser packet sorting logic.
1862 * Turn the PFC off to make sure we are in Xon state before
1863 * enabling it.
1864 */
1865 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1866 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1867 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1868 /* Enable PFC again */
1869 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1870 EMAC_REG_RX_PFC_MODE_RX_EN |
1871 EMAC_REG_RX_PFC_MODE_TX_EN |
1872 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1873
1874 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1875 ((0x0101 <<
1876 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1877 (0x00ff <<
1878 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1879 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1880 }
1881 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1882
1883 /* Set Loopback */
1884 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1885 if (lb)
1886 val |= 0x810;
1887 else
1888 val &= ~0x810;
1889 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1890
1891 /* enable emac */
1892 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1893
1894 /* enable emac for jumbo packets */
1895 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1896 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1897 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1898
1899 /* strip CRC */
1900 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1901
1902 /* disable the NIG in/out to the bmac */
1903 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1904 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1905 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1906
1907 /* enable the NIG in/out to the emac */
1908 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1909 val = 0;
1910 if ((params->feature_config_flags &
1911 FEATURE_CONFIG_PFC_ENABLED) ||
1912 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1913 val = 1;
1914
1915 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1916 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1917
1918 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1919
1920 vars->mac_type = MAC_TYPE_EMAC;
1921 return 0;
1922 }
1923
1924 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1925 struct link_vars *vars)
1926 {
1927 u32 wb_data[2];
1928 struct bnx2x *bp = params->bp;
1929 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1930 NIG_REG_INGRESS_BMAC0_MEM;
1931
1932 u32 val = 0x14;
1933 if ((!(params->feature_config_flags &
1934 FEATURE_CONFIG_PFC_ENABLED)) &&
1935 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1936 /* Enable BigMAC to react on received Pause packets */
1937 val |= (1<<5);
1938 wb_data[0] = val;
1939 wb_data[1] = 0;
1940 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1941
1942 /* tx control */
1943 val = 0xc0;
1944 if (!(params->feature_config_flags &
1945 FEATURE_CONFIG_PFC_ENABLED) &&
1946 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1947 val |= 0x800000;
1948 wb_data[0] = val;
1949 wb_data[1] = 0;
1950 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1951 }
1952
1953 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1954 struct link_vars *vars,
1955 u8 is_lb)
1956 {
1957 /*
1958 * Set rx control: Strip CRC and enable BigMAC to relay
1959 * control packets to the system as well
1960 */
1961 u32 wb_data[2];
1962 struct bnx2x *bp = params->bp;
1963 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1964 NIG_REG_INGRESS_BMAC0_MEM;
1965 u32 val = 0x14;
1966
1967 if ((!(params->feature_config_flags &
1968 FEATURE_CONFIG_PFC_ENABLED)) &&
1969 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1970 /* Enable BigMAC to react on received Pause packets */
1971 val |= (1<<5);
1972 wb_data[0] = val;
1973 wb_data[1] = 0;
1974 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1975 udelay(30);
1976
1977 /* Tx control */
1978 val = 0xc0;
1979 if (!(params->feature_config_flags &
1980 FEATURE_CONFIG_PFC_ENABLED) &&
1981 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1982 val |= 0x800000;
1983 wb_data[0] = val;
1984 wb_data[1] = 0;
1985 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1986
1987 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1988 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1989 /* Enable PFC RX & TX & STATS and set 8 COS */
1990 wb_data[0] = 0x0;
1991 wb_data[0] |= (1<<0); /* RX */
1992 wb_data[0] |= (1<<1); /* TX */
1993 wb_data[0] |= (1<<2); /* Force initial Xon */
1994 wb_data[0] |= (1<<3); /* 8 cos */
1995 wb_data[0] |= (1<<5); /* STATS */
1996 wb_data[1] = 0;
1997 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1998 wb_data, 2);
1999 /* Clear the force Xon */
2000 wb_data[0] &= ~(1<<2);
2001 } else {
2002 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2003 /* disable PFC RX & TX & STATS and set 8 COS */
2004 wb_data[0] = 0x8;
2005 wb_data[1] = 0;
2006 }
2007
2008 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2009
2010 /*
2011 * Set Time (based unit is 512 bit time) between automatic
2012 * re-sending of PP packets amd enable automatic re-send of
2013 * Per-Priroity Packet as long as pp_gen is asserted and
2014 * pp_disable is low.
2015 */
2016 val = 0x8000;
2017 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2018 val |= (1<<16); /* enable automatic re-send */
2019
2020 wb_data[0] = val;
2021 wb_data[1] = 0;
2022 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2023 wb_data, 2);
2024
2025 /* mac control */
2026 val = 0x3; /* Enable RX and TX */
2027 if (is_lb) {
2028 val |= 0x4; /* Local loopback */
2029 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2030 }
2031 /* When PFC enabled, Pass pause frames towards the NIG. */
2032 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2033 val |= ((1<<6)|(1<<5));
2034
2035 wb_data[0] = val;
2036 wb_data[1] = 0;
2037 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2038 }
2039
2040 /* PFC BRB internal port configuration params */
2041 struct bnx2x_pfc_brb_threshold_val {
2042 u32 pause_xoff;
2043 u32 pause_xon;
2044 u32 full_xoff;
2045 u32 full_xon;
2046 };
2047
2048 struct bnx2x_pfc_brb_e3b0_val {
2049 u32 per_class_guaranty_mode;
2050 u32 lb_guarantied_hyst;
2051 u32 full_lb_xoff_th;
2052 u32 full_lb_xon_threshold;
2053 u32 lb_guarantied;
2054 u32 mac_0_class_t_guarantied;
2055 u32 mac_0_class_t_guarantied_hyst;
2056 u32 mac_1_class_t_guarantied;
2057 u32 mac_1_class_t_guarantied_hyst;
2058 };
2059
2060 struct bnx2x_pfc_brb_th_val {
2061 struct bnx2x_pfc_brb_threshold_val pauseable_th;
2062 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2063 struct bnx2x_pfc_brb_threshold_val default_class0;
2064 struct bnx2x_pfc_brb_threshold_val default_class1;
2065
2066 };
2067 static int bnx2x_pfc_brb_get_config_params(
2068 struct link_params *params,
2069 struct bnx2x_pfc_brb_th_val *config_val)
2070 {
2071 struct bnx2x *bp = params->bp;
2072 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2073
2074 config_val->default_class1.pause_xoff = 0;
2075 config_val->default_class1.pause_xon = 0;
2076 config_val->default_class1.full_xoff = 0;
2077 config_val->default_class1.full_xon = 0;
2078
2079 if (CHIP_IS_E2(bp)) {
2080 /* class0 defaults */
2081 config_val->default_class0.pause_xoff =
2082 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2083 config_val->default_class0.pause_xon =
2084 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2085 config_val->default_class0.full_xoff =
2086 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2087 config_val->default_class0.full_xon =
2088 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2089 /* pause able*/
2090 config_val->pauseable_th.pause_xoff =
2091 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2092 config_val->pauseable_th.pause_xon =
2093 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2094 config_val->pauseable_th.full_xoff =
2095 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2096 config_val->pauseable_th.full_xon =
2097 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2098 /* non pause able*/
2099 config_val->non_pauseable_th.pause_xoff =
2100 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2101 config_val->non_pauseable_th.pause_xon =
2102 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2103 config_val->non_pauseable_th.full_xoff =
2104 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2105 config_val->non_pauseable_th.full_xon =
2106 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2107 } else if (CHIP_IS_E3A0(bp)) {
2108 /* class0 defaults */
2109 config_val->default_class0.pause_xoff =
2110 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2111 config_val->default_class0.pause_xon =
2112 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2113 config_val->default_class0.full_xoff =
2114 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2115 config_val->default_class0.full_xon =
2116 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2117 /* pause able */
2118 config_val->pauseable_th.pause_xoff =
2119 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2120 config_val->pauseable_th.pause_xon =
2121 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2122 config_val->pauseable_th.full_xoff =
2123 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2124 config_val->pauseable_th.full_xon =
2125 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2126 /* non pause able*/
2127 config_val->non_pauseable_th.pause_xoff =
2128 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2129 config_val->non_pauseable_th.pause_xon =
2130 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2131 config_val->non_pauseable_th.full_xoff =
2132 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2133 config_val->non_pauseable_th.full_xon =
2134 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2135 } else if (CHIP_IS_E3B0(bp)) {
2136 /* class0 defaults */
2137 config_val->default_class0.pause_xoff =
2138 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2139 config_val->default_class0.pause_xon =
2140 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2141 config_val->default_class0.full_xoff =
2142 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2143 config_val->default_class0.full_xon =
2144 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2145
2146 if (params->phy[INT_PHY].flags &
2147 FLAGS_4_PORT_MODE) {
2148 config_val->pauseable_th.pause_xoff =
2149 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2150 config_val->pauseable_th.pause_xon =
2151 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2152 config_val->pauseable_th.full_xoff =
2153 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2154 config_val->pauseable_th.full_xon =
2155 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2156 /* non pause able*/
2157 config_val->non_pauseable_th.pause_xoff =
2158 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2159 config_val->non_pauseable_th.pause_xon =
2160 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2161 config_val->non_pauseable_th.full_xoff =
2162 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2163 config_val->non_pauseable_th.full_xon =
2164 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2165 } else {
2166 config_val->pauseable_th.pause_xoff =
2167 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2168 config_val->pauseable_th.pause_xon =
2169 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2170 config_val->pauseable_th.full_xoff =
2171 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2172 config_val->pauseable_th.full_xon =
2173 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2174 /* non pause able*/
2175 config_val->non_pauseable_th.pause_xoff =
2176 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2177 config_val->non_pauseable_th.pause_xon =
2178 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2179 config_val->non_pauseable_th.full_xoff =
2180 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2181 config_val->non_pauseable_th.full_xon =
2182 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2183 }
2184 } else
2185 return -EINVAL;
2186
2187 return 0;
2188 }
2189
2190 static void bnx2x_pfc_brb_get_e3b0_config_params(
2191 struct link_params *params,
2192 struct bnx2x_pfc_brb_e3b0_val
2193 *e3b0_val,
2194 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2195 const u8 pfc_enabled)
2196 {
2197 if (pfc_enabled && pfc_params) {
2198 e3b0_val->per_class_guaranty_mode = 1;
2199 e3b0_val->lb_guarantied_hyst = 80;
2200
2201 if (params->phy[INT_PHY].flags &
2202 FLAGS_4_PORT_MODE) {
2203 e3b0_val->full_lb_xoff_th =
2204 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2205 e3b0_val->full_lb_xon_threshold =
2206 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2207 e3b0_val->lb_guarantied =
2208 PFC_E3B0_4P_LB_GUART;
2209 e3b0_val->mac_0_class_t_guarantied =
2210 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2211 e3b0_val->mac_0_class_t_guarantied_hyst =
2212 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2213 e3b0_val->mac_1_class_t_guarantied =
2214 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2215 e3b0_val->mac_1_class_t_guarantied_hyst =
2216 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2217 } else {
2218 e3b0_val->full_lb_xoff_th =
2219 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2220 e3b0_val->full_lb_xon_threshold =
2221 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2222 e3b0_val->mac_0_class_t_guarantied_hyst =
2223 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2224 e3b0_val->mac_1_class_t_guarantied =
2225 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2226 e3b0_val->mac_1_class_t_guarantied_hyst =
2227 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2228
2229 if (pfc_params->cos0_pauseable !=
2230 pfc_params->cos1_pauseable) {
2231 /* nonpauseable= Lossy + pauseable = Lossless*/
2232 e3b0_val->lb_guarantied =
2233 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2234 e3b0_val->mac_0_class_t_guarantied =
2235 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2236 } else if (pfc_params->cos0_pauseable) {
2237 /* Lossless +Lossless*/
2238 e3b0_val->lb_guarantied =
2239 PFC_E3B0_2P_PAUSE_LB_GUART;
2240 e3b0_val->mac_0_class_t_guarantied =
2241 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2242 } else {
2243 /* Lossy +Lossy*/
2244 e3b0_val->lb_guarantied =
2245 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2246 e3b0_val->mac_0_class_t_guarantied =
2247 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2248 }
2249 }
2250 } else {
2251 e3b0_val->per_class_guaranty_mode = 0;
2252 e3b0_val->lb_guarantied_hyst = 0;
2253 e3b0_val->full_lb_xoff_th =
2254 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2255 e3b0_val->full_lb_xon_threshold =
2256 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2257 e3b0_val->lb_guarantied =
2258 DEFAULT_E3B0_LB_GUART;
2259 e3b0_val->mac_0_class_t_guarantied =
2260 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2261 e3b0_val->mac_0_class_t_guarantied_hyst =
2262 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2263 e3b0_val->mac_1_class_t_guarantied =
2264 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2265 e3b0_val->mac_1_class_t_guarantied_hyst =
2266 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2267 }
2268 }
2269 static int bnx2x_update_pfc_brb(struct link_params *params,
2270 struct link_vars *vars,
2271 struct bnx2x_nig_brb_pfc_port_params
2272 *pfc_params)
2273 {
2274 struct bnx2x *bp = params->bp;
2275 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2276 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2277 &config_val.pauseable_th;
2278 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2279 const int set_pfc = params->feature_config_flags &
2280 FEATURE_CONFIG_PFC_ENABLED;
2281 const u8 pfc_enabled = (set_pfc && pfc_params);
2282 int bnx2x_status = 0;
2283 u8 port = params->port;
2284
2285 /* default - pause configuration */
2286 reg_th_config = &config_val.pauseable_th;
2287 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2288 if (bnx2x_status)
2289 return bnx2x_status;
2290
2291 if (pfc_enabled) {
2292 /* First COS */
2293 if (pfc_params->cos0_pauseable)
2294 reg_th_config = &config_val.pauseable_th;
2295 else
2296 reg_th_config = &config_val.non_pauseable_th;
2297 } else
2298 reg_th_config = &config_val.default_class0;
2299 /*
2300 * The number of free blocks below which the pause signal to class 0
2301 * of MAC #n is asserted. n=0,1
2302 */
2303 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2304 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2305 reg_th_config->pause_xoff);
2306 /*
2307 * The number of free blocks above which the pause signal to class 0
2308 * of MAC #n is de-asserted. n=0,1
2309 */
2310 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2311 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2312 /*
2313 * The number of free blocks below which the full signal to class 0
2314 * of MAC #n is asserted. n=0,1
2315 */
2316 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2317 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2318 /*
2319 * The number of free blocks above which the full signal to class 0
2320 * of MAC #n is de-asserted. n=0,1
2321 */
2322 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2323 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2324
2325 if (pfc_enabled) {
2326 /* Second COS */
2327 if (pfc_params->cos1_pauseable)
2328 reg_th_config = &config_val.pauseable_th;
2329 else
2330 reg_th_config = &config_val.non_pauseable_th;
2331 } else
2332 reg_th_config = &config_val.default_class1;
2333 /*
2334 * The number of free blocks below which the pause signal to
2335 * class 1 of MAC #n is asserted. n=0,1
2336 */
2337 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2338 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2339 reg_th_config->pause_xoff);
2340
2341 /*
2342 * The number of free blocks above which the pause signal to
2343 * class 1 of MAC #n is de-asserted. n=0,1
2344 */
2345 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2346 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2347 reg_th_config->pause_xon);
2348 /*
2349 * The number of free blocks below which the full signal to
2350 * class 1 of MAC #n is asserted. n=0,1
2351 */
2352 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2353 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2354 reg_th_config->full_xoff);
2355 /*
2356 * The number of free blocks above which the full signal to
2357 * class 1 of MAC #n is de-asserted. n=0,1
2358 */
2359 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2360 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2361 reg_th_config->full_xon);
2362
2363 if (CHIP_IS_E3B0(bp)) {
2364 bnx2x_pfc_brb_get_e3b0_config_params(
2365 params,
2366 &e3b0_val,
2367 pfc_params,
2368 pfc_enabled);
2369
2370 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2371 e3b0_val.per_class_guaranty_mode);
2372
2373 /*
2374 * The hysteresis on the guarantied buffer space for the Lb
2375 * port before signaling XON.
2376 */
2377 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2378 e3b0_val.lb_guarantied_hyst);
2379
2380 /*
2381 * The number of free blocks below which the full signal to the
2382 * LB port is asserted.
2383 */
2384 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2385 e3b0_val.full_lb_xoff_th);
2386 /*
2387 * The number of free blocks above which the full signal to the
2388 * LB port is de-asserted.
2389 */
2390 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2391 e3b0_val.full_lb_xon_threshold);
2392 /*
2393 * The number of blocks guarantied for the MAC #n port. n=0,1
2394 */
2395
2396 /* The number of blocks guarantied for the LB port.*/
2397 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2398 e3b0_val.lb_guarantied);
2399
2400 /*
2401 * The number of blocks guarantied for the MAC #n port.
2402 */
2403 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2404 2 * e3b0_val.mac_0_class_t_guarantied);
2405 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2406 2 * e3b0_val.mac_1_class_t_guarantied);
2407 /*
2408 * The number of blocks guarantied for class #t in MAC0. t=0,1
2409 */
2410 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2411 e3b0_val.mac_0_class_t_guarantied);
2412 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2413 e3b0_val.mac_0_class_t_guarantied);
2414 /*
2415 * The hysteresis on the guarantied buffer space for class in
2416 * MAC0. t=0,1
2417 */
2418 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2419 e3b0_val.mac_0_class_t_guarantied_hyst);
2420 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2421 e3b0_val.mac_0_class_t_guarantied_hyst);
2422
2423 /*
2424 * The number of blocks guarantied for class #t in MAC1.t=0,1
2425 */
2426 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2427 e3b0_val.mac_1_class_t_guarantied);
2428 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2429 e3b0_val.mac_1_class_t_guarantied);
2430 /*
2431 * The hysteresis on the guarantied buffer space for class #t
2432 * in MAC1. t=0,1
2433 */
2434 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2435 e3b0_val.mac_1_class_t_guarantied_hyst);
2436 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2437 e3b0_val.mac_1_class_t_guarantied_hyst);
2438 }
2439
2440 return bnx2x_status;
2441 }
2442
2443 /******************************************************************************
2444 * Description:
2445 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2446 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2447 ******************************************************************************/
2448 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2449 u8 cos_entry,
2450 u32 priority_mask, u8 port)
2451 {
2452 u32 nig_reg_rx_priority_mask_add = 0;
2453
2454 switch (cos_entry) {
2455 case 0:
2456 nig_reg_rx_priority_mask_add = (port) ?
2457 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2458 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2459 break;
2460 case 1:
2461 nig_reg_rx_priority_mask_add = (port) ?
2462 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2463 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2464 break;
2465 case 2:
2466 nig_reg_rx_priority_mask_add = (port) ?
2467 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2468 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2469 break;
2470 case 3:
2471 if (port)
2472 return -EINVAL;
2473 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2474 break;
2475 case 4:
2476 if (port)
2477 return -EINVAL;
2478 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2479 break;
2480 case 5:
2481 if (port)
2482 return -EINVAL;
2483 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2484 break;
2485 }
2486
2487 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2488
2489 return 0;
2490 }
2491 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2492 {
2493 struct bnx2x *bp = params->bp;
2494
2495 REG_WR(bp, params->shmem_base +
2496 offsetof(struct shmem_region,
2497 port_mb[params->port].link_status), link_status);
2498 }
2499
2500 static void bnx2x_update_pfc_nig(struct link_params *params,
2501 struct link_vars *vars,
2502 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2503 {
2504 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2505 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2506 u32 pkt_priority_to_cos = 0;
2507 struct bnx2x *bp = params->bp;
2508 u8 port = params->port;
2509
2510 int set_pfc = params->feature_config_flags &
2511 FEATURE_CONFIG_PFC_ENABLED;
2512 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2513
2514 /*
2515 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2516 * MAC control frames (that are not pause packets)
2517 * will be forwarded to the XCM.
2518 */
2519 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2520 NIG_REG_LLH0_XCM_MASK);
2521 /*
2522 * nig params will override non PFC params, since it's possible to
2523 * do transition from PFC to SAFC
2524 */
2525 if (set_pfc) {
2526 pause_enable = 0;
2527 llfc_out_en = 0;
2528 llfc_enable = 0;
2529 if (CHIP_IS_E3(bp))
2530 ppp_enable = 0;
2531 else
2532 ppp_enable = 1;
2533 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2534 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2535 xcm_out_en = 0;
2536 hwpfc_enable = 1;
2537 } else {
2538 if (nig_params) {
2539 llfc_out_en = nig_params->llfc_out_en;
2540 llfc_enable = nig_params->llfc_enable;
2541 pause_enable = nig_params->pause_enable;
2542 } else /*defaul non PFC mode - PAUSE */
2543 pause_enable = 1;
2544
2545 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2546 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2547 xcm_out_en = 1;
2548 }
2549
2550 if (CHIP_IS_E3(bp))
2551 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2552 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2553 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2554 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2555 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2556 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2557 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2558 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2559
2560 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2561 NIG_REG_PPP_ENABLE_0, ppp_enable);
2562
2563 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2564 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2565
2566 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2567 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2568
2569 /* output enable for RX_XCM # IF */
2570 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2571 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2572
2573 /* HW PFC TX enable */
2574 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2575 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2576
2577 if (nig_params) {
2578 u8 i = 0;
2579 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2580
2581 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2582 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2583 nig_params->rx_cos_priority_mask[i], port);
2584
2585 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2586 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2587 nig_params->llfc_high_priority_classes);
2588
2589 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2590 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2591 nig_params->llfc_low_priority_classes);
2592 }
2593 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2594 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2595 pkt_priority_to_cos);
2596 }
2597
2598 int bnx2x_update_pfc(struct link_params *params,
2599 struct link_vars *vars,
2600 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2601 {
2602 /*
2603 * The PFC and pause are orthogonal to one another, meaning when
2604 * PFC is enabled, the pause are disabled, and when PFC is
2605 * disabled, pause are set according to the pause result.
2606 */
2607 u32 val;
2608 struct bnx2x *bp = params->bp;
2609 int bnx2x_status = 0;
2610 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2611
2612 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2613 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2614 else
2615 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2616
2617 bnx2x_update_mng(params, vars->link_status);
2618
2619 /* update NIG params */
2620 bnx2x_update_pfc_nig(params, vars, pfc_params);
2621
2622 /* update BRB params */
2623 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2624 if (bnx2x_status)
2625 return bnx2x_status;
2626
2627 if (!vars->link_up)
2628 return bnx2x_status;
2629
2630 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2631 if (CHIP_IS_E3(bp))
2632 bnx2x_update_pfc_xmac(params, vars, 0);
2633 else {
2634 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2635 if ((val &
2636 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2637 == 0) {
2638 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2639 bnx2x_emac_enable(params, vars, 0);
2640 return bnx2x_status;
2641 }
2642 if (CHIP_IS_E2(bp))
2643 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2644 else
2645 bnx2x_update_pfc_bmac1(params, vars);
2646
2647 val = 0;
2648 if ((params->feature_config_flags &
2649 FEATURE_CONFIG_PFC_ENABLED) ||
2650 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2651 val = 1;
2652 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2653 }
2654 return bnx2x_status;
2655 }
2656
2657
2658 static int bnx2x_bmac1_enable(struct link_params *params,
2659 struct link_vars *vars,
2660 u8 is_lb)
2661 {
2662 struct bnx2x *bp = params->bp;
2663 u8 port = params->port;
2664 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2665 NIG_REG_INGRESS_BMAC0_MEM;
2666 u32 wb_data[2];
2667 u32 val;
2668
2669 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2670
2671 /* XGXS control */
2672 wb_data[0] = 0x3c;
2673 wb_data[1] = 0;
2674 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2675 wb_data, 2);
2676
2677 /* tx MAC SA */
2678 wb_data[0] = ((params->mac_addr[2] << 24) |
2679 (params->mac_addr[3] << 16) |
2680 (params->mac_addr[4] << 8) |
2681 params->mac_addr[5]);
2682 wb_data[1] = ((params->mac_addr[0] << 8) |
2683 params->mac_addr[1]);
2684 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2685
2686 /* mac control */
2687 val = 0x3;
2688 if (is_lb) {
2689 val |= 0x4;
2690 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2691 }
2692 wb_data[0] = val;
2693 wb_data[1] = 0;
2694 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2695
2696 /* set rx mtu */
2697 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2698 wb_data[1] = 0;
2699 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2700
2701 bnx2x_update_pfc_bmac1(params, vars);
2702
2703 /* set tx mtu */
2704 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2705 wb_data[1] = 0;
2706 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2707
2708 /* set cnt max size */
2709 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2710 wb_data[1] = 0;
2711 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2712
2713 /* configure safc */
2714 wb_data[0] = 0x1000200;
2715 wb_data[1] = 0;
2716 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2717 wb_data, 2);
2718
2719 return 0;
2720 }
2721
2722 static int bnx2x_bmac2_enable(struct link_params *params,
2723 struct link_vars *vars,
2724 u8 is_lb)
2725 {
2726 struct bnx2x *bp = params->bp;
2727 u8 port = params->port;
2728 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2729 NIG_REG_INGRESS_BMAC0_MEM;
2730 u32 wb_data[2];
2731
2732 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2733
2734 wb_data[0] = 0;
2735 wb_data[1] = 0;
2736 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2737 udelay(30);
2738
2739 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2740 wb_data[0] = 0x3c;
2741 wb_data[1] = 0;
2742 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2743 wb_data, 2);
2744
2745 udelay(30);
2746
2747 /* tx MAC SA */
2748 wb_data[0] = ((params->mac_addr[2] << 24) |
2749 (params->mac_addr[3] << 16) |
2750 (params->mac_addr[4] << 8) |
2751 params->mac_addr[5]);
2752 wb_data[1] = ((params->mac_addr[0] << 8) |
2753 params->mac_addr[1]);
2754 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2755 wb_data, 2);
2756
2757 udelay(30);
2758
2759 /* Configure SAFC */
2760 wb_data[0] = 0x1000200;
2761 wb_data[1] = 0;
2762 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2763 wb_data, 2);
2764 udelay(30);
2765
2766 /* set rx mtu */
2767 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2768 wb_data[1] = 0;
2769 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2770 udelay(30);
2771
2772 /* set tx mtu */
2773 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2774 wb_data[1] = 0;
2775 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2776 udelay(30);
2777 /* set cnt max size */
2778 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2779 wb_data[1] = 0;
2780 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2781 udelay(30);
2782 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2783
2784 return 0;
2785 }
2786
2787 static int bnx2x_bmac_enable(struct link_params *params,
2788 struct link_vars *vars,
2789 u8 is_lb)
2790 {
2791 int rc = 0;
2792 u8 port = params->port;
2793 struct bnx2x *bp = params->bp;
2794 u32 val;
2795 /* reset and unreset the BigMac */
2796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2797 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2798 msleep(1);
2799
2800 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2801 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2802
2803 /* enable access for bmac registers */
2804 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2805
2806 /* Enable BMAC according to BMAC type*/
2807 if (CHIP_IS_E2(bp))
2808 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2809 else
2810 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2811 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2812 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2813 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2814 val = 0;
2815 if ((params->feature_config_flags &
2816 FEATURE_CONFIG_PFC_ENABLED) ||
2817 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2818 val = 1;
2819 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2820 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2821 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2822 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2823 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2824 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2825
2826 vars->mac_type = MAC_TYPE_BMAC;
2827 return rc;
2828 }
2829
2830 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2831 {
2832 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2833 NIG_REG_INGRESS_BMAC0_MEM;
2834 u32 wb_data[2];
2835 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2836
2837 /* Only if the bmac is out of reset */
2838 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2839 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2840 nig_bmac_enable) {
2841
2842 if (CHIP_IS_E2(bp)) {
2843 /* Clear Rx Enable bit in BMAC_CONTROL register */
2844 REG_RD_DMAE(bp, bmac_addr +
2845 BIGMAC2_REGISTER_BMAC_CONTROL,
2846 wb_data, 2);
2847 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2848 REG_WR_DMAE(bp, bmac_addr +
2849 BIGMAC2_REGISTER_BMAC_CONTROL,
2850 wb_data, 2);
2851 } else {
2852 /* Clear Rx Enable bit in BMAC_CONTROL register */
2853 REG_RD_DMAE(bp, bmac_addr +
2854 BIGMAC_REGISTER_BMAC_CONTROL,
2855 wb_data, 2);
2856 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2857 REG_WR_DMAE(bp, bmac_addr +
2858 BIGMAC_REGISTER_BMAC_CONTROL,
2859 wb_data, 2);
2860 }
2861 msleep(1);
2862 }
2863 }
2864
2865 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2866 u32 line_speed)
2867 {
2868 struct bnx2x *bp = params->bp;
2869 u8 port = params->port;
2870 u32 init_crd, crd;
2871 u32 count = 1000;
2872
2873 /* disable port */
2874 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2875
2876 /* wait for init credit */
2877 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2878 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2879 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2880
2881 while ((init_crd != crd) && count) {
2882 msleep(5);
2883
2884 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2885 count--;
2886 }
2887 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2888 if (init_crd != crd) {
2889 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2890 init_crd, crd);
2891 return -EINVAL;
2892 }
2893
2894 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2895 line_speed == SPEED_10 ||
2896 line_speed == SPEED_100 ||
2897 line_speed == SPEED_1000 ||
2898 line_speed == SPEED_2500) {
2899 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2900 /* update threshold */
2901 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2902 /* update init credit */
2903 init_crd = 778; /* (800-18-4) */
2904
2905 } else {
2906 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2907 ETH_OVREHEAD)/16;
2908 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2909 /* update threshold */
2910 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2911 /* update init credit */
2912 switch (line_speed) {
2913 case SPEED_10000:
2914 init_crd = thresh + 553 - 22;
2915 break;
2916 default:
2917 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2918 line_speed);
2919 return -EINVAL;
2920 }
2921 }
2922 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2923 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2924 line_speed, init_crd);
2925
2926 /* probe the credit changes */
2927 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2928 msleep(5);
2929 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2930
2931 /* enable port */
2932 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2933 return 0;
2934 }
2935
2936 /**
2937 * bnx2x_get_emac_base - retrive emac base address
2938 *
2939 * @bp: driver handle
2940 * @mdc_mdio_access: access type
2941 * @port: port id
2942 *
2943 * This function selects the MDC/MDIO access (through emac0 or
2944 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2945 * phy has a default access mode, which could also be overridden
2946 * by nvram configuration. This parameter, whether this is the
2947 * default phy configuration, or the nvram overrun
2948 * configuration, is passed here as mdc_mdio_access and selects
2949 * the emac_base for the CL45 read/writes operations
2950 */
2951 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2952 u32 mdc_mdio_access, u8 port)
2953 {
2954 u32 emac_base = 0;
2955 switch (mdc_mdio_access) {
2956 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2957 break;
2958 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2959 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2960 emac_base = GRCBASE_EMAC1;
2961 else
2962 emac_base = GRCBASE_EMAC0;
2963 break;
2964 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2965 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2966 emac_base = GRCBASE_EMAC0;
2967 else
2968 emac_base = GRCBASE_EMAC1;
2969 break;
2970 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2971 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2972 break;
2973 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2974 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2975 break;
2976 default:
2977 break;
2978 }
2979 return emac_base;
2980
2981 }
2982
2983 /******************************************************************/
2984 /* CL22 access functions */
2985 /******************************************************************/
2986 static int bnx2x_cl22_write(struct bnx2x *bp,
2987 struct bnx2x_phy *phy,
2988 u16 reg, u16 val)
2989 {
2990 u32 tmp, mode;
2991 u8 i;
2992 int rc = 0;
2993 /* Switch to CL22 */
2994 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2995 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2996 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2997
2998 /* address */
2999 tmp = ((phy->addr << 21) | (reg << 16) | val |
3000 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3001 EMAC_MDIO_COMM_START_BUSY);
3002 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3003
3004 for (i = 0; i < 50; i++) {
3005 udelay(10);
3006
3007 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3008 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3009 udelay(5);
3010 break;
3011 }
3012 }
3013 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3014 DP(NETIF_MSG_LINK, "write phy register failed\n");
3015 rc = -EFAULT;
3016 }
3017 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3018 return rc;
3019 }
3020
3021 static int bnx2x_cl22_read(struct bnx2x *bp,
3022 struct bnx2x_phy *phy,
3023 u16 reg, u16 *ret_val)
3024 {
3025 u32 val, mode;
3026 u16 i;
3027 int rc = 0;
3028
3029 /* Switch to CL22 */
3030 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3031 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3032 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3033
3034 /* address */
3035 val = ((phy->addr << 21) | (reg << 16) |
3036 EMAC_MDIO_COMM_COMMAND_READ_22 |
3037 EMAC_MDIO_COMM_START_BUSY);
3038 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3039
3040 for (i = 0; i < 50; i++) {
3041 udelay(10);
3042
3043 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3044 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3045 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3046 udelay(5);
3047 break;
3048 }
3049 }
3050 if (val & EMAC_MDIO_COMM_START_BUSY) {
3051 DP(NETIF_MSG_LINK, "read phy register failed\n");
3052
3053 *ret_val = 0;
3054 rc = -EFAULT;
3055 }
3056 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3057 return rc;
3058 }
3059
3060 /******************************************************************/
3061 /* CL45 access functions */
3062 /******************************************************************/
3063 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3064 u8 devad, u16 reg, u16 *ret_val)
3065 {
3066 u32 val;
3067 u16 i;
3068 int rc = 0;
3069 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3070 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3071 EMAC_MDIO_STATUS_10MB);
3072 /* address */
3073 val = ((phy->addr << 21) | (devad << 16) | reg |
3074 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3075 EMAC_MDIO_COMM_START_BUSY);
3076 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3077
3078 for (i = 0; i < 50; i++) {
3079 udelay(10);
3080
3081 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3082 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3083 udelay(5);
3084 break;
3085 }
3086 }
3087 if (val & EMAC_MDIO_COMM_START_BUSY) {
3088 DP(NETIF_MSG_LINK, "read phy register failed\n");
3089 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3090 *ret_val = 0;
3091 rc = -EFAULT;
3092 } else {
3093 /* data */
3094 val = ((phy->addr << 21) | (devad << 16) |
3095 EMAC_MDIO_COMM_COMMAND_READ_45 |
3096 EMAC_MDIO_COMM_START_BUSY);
3097 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3098
3099 for (i = 0; i < 50; i++) {
3100 udelay(10);
3101
3102 val = REG_RD(bp, phy->mdio_ctrl +
3103 EMAC_REG_EMAC_MDIO_COMM);
3104 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3105 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3106 break;
3107 }
3108 }
3109 if (val & EMAC_MDIO_COMM_START_BUSY) {
3110 DP(NETIF_MSG_LINK, "read phy register failed\n");
3111 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3112 *ret_val = 0;
3113 rc = -EFAULT;
3114 }
3115 }
3116 /* Work around for E3 A0 */
3117 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3118 phy->flags ^= FLAGS_DUMMY_READ;
3119 if (phy->flags & FLAGS_DUMMY_READ) {
3120 u16 temp_val;
3121 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3122 }
3123 }
3124
3125 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3126 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3127 EMAC_MDIO_STATUS_10MB);
3128 return rc;
3129 }
3130
3131 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3132 u8 devad, u16 reg, u16 val)
3133 {
3134 u32 tmp;
3135 u8 i;
3136 int rc = 0;
3137 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3138 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3139 EMAC_MDIO_STATUS_10MB);
3140
3141 /* address */
3142
3143 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3144 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3145 EMAC_MDIO_COMM_START_BUSY);
3146 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3147
3148 for (i = 0; i < 50; i++) {
3149 udelay(10);
3150
3151 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3152 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3153 udelay(5);
3154 break;
3155 }
3156 }
3157 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3158 DP(NETIF_MSG_LINK, "write phy register failed\n");
3159 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3160 rc = -EFAULT;
3161 } else {
3162 /* data */
3163 tmp = ((phy->addr << 21) | (devad << 16) | val |
3164 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3165 EMAC_MDIO_COMM_START_BUSY);
3166 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3167
3168 for (i = 0; i < 50; i++) {
3169 udelay(10);
3170
3171 tmp = REG_RD(bp, phy->mdio_ctrl +
3172 EMAC_REG_EMAC_MDIO_COMM);
3173 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3174 udelay(5);
3175 break;
3176 }
3177 }
3178 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3179 DP(NETIF_MSG_LINK, "write phy register failed\n");
3180 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3181 rc = -EFAULT;
3182 }
3183 }
3184 /* Work around for E3 A0 */
3185 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3186 phy->flags ^= FLAGS_DUMMY_READ;
3187 if (phy->flags & FLAGS_DUMMY_READ) {
3188 u16 temp_val;
3189 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3190 }
3191 }
3192 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3193 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3194 EMAC_MDIO_STATUS_10MB);
3195 return rc;
3196 }
3197 /******************************************************************/
3198 /* BSC access functions from E3 */
3199 /******************************************************************/
3200 static void bnx2x_bsc_module_sel(struct link_params *params)
3201 {
3202 int idx;
3203 u32 board_cfg, sfp_ctrl;
3204 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3205 struct bnx2x *bp = params->bp;
3206 u8 port = params->port;
3207 /* Read I2C output PINs */
3208 board_cfg = REG_RD(bp, params->shmem_base +
3209 offsetof(struct shmem_region,
3210 dev_info.shared_hw_config.board));
3211 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3212 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3213 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3214
3215 /* Read I2C output value */
3216 sfp_ctrl = REG_RD(bp, params->shmem_base +
3217 offsetof(struct shmem_region,
3218 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3219 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3220 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3221 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3222 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3223 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3224 }
3225
3226 static int bnx2x_bsc_read(struct link_params *params,
3227 struct bnx2x_phy *phy,
3228 u8 sl_devid,
3229 u16 sl_addr,
3230 u8 lc_addr,
3231 u8 xfer_cnt,
3232 u32 *data_array)
3233 {
3234 u32 val, i;
3235 int rc = 0;
3236 struct bnx2x *bp = params->bp;
3237
3238 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3239 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3240 return -EINVAL;
3241 }
3242
3243 if (xfer_cnt > 16) {
3244 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3245 xfer_cnt);
3246 return -EINVAL;
3247 }
3248 bnx2x_bsc_module_sel(params);
3249
3250 xfer_cnt = 16 - lc_addr;
3251
3252 /* enable the engine */
3253 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3254 val |= MCPR_IMC_COMMAND_ENABLE;
3255 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3256
3257 /* program slave device ID */
3258 val = (sl_devid << 16) | sl_addr;
3259 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3260
3261 /* start xfer with 0 byte to update the address pointer ???*/
3262 val = (MCPR_IMC_COMMAND_ENABLE) |
3263 (MCPR_IMC_COMMAND_WRITE_OP <<
3264 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3265 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3266 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3267
3268 /* poll for completion */
3269 i = 0;
3270 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3271 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3272 udelay(10);
3273 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3274 if (i++ > 1000) {
3275 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3276 i);
3277 rc = -EFAULT;
3278 break;
3279 }
3280 }
3281 if (rc == -EFAULT)
3282 return rc;
3283
3284 /* start xfer with read op */
3285 val = (MCPR_IMC_COMMAND_ENABLE) |
3286 (MCPR_IMC_COMMAND_READ_OP <<
3287 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3288 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3289 (xfer_cnt);
3290 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3291
3292 /* poll for completion */
3293 i = 0;
3294 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3295 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3296 udelay(10);
3297 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3298 if (i++ > 1000) {
3299 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3300 rc = -EFAULT;
3301 break;
3302 }
3303 }
3304 if (rc == -EFAULT)
3305 return rc;
3306
3307 for (i = (lc_addr >> 2); i < 4; i++) {
3308 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3309 #ifdef __BIG_ENDIAN
3310 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3311 ((data_array[i] & 0x0000ff00) << 8) |
3312 ((data_array[i] & 0x00ff0000) >> 8) |
3313 ((data_array[i] & 0xff000000) >> 24);
3314 #endif
3315 }
3316 return rc;
3317 }
3318
3319 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3320 u8 devad, u16 reg, u16 or_val)
3321 {
3322 u16 val;
3323 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3324 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3325 }
3326
3327 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3328 u8 devad, u16 reg, u16 *ret_val)
3329 {
3330 u8 phy_index;
3331 /*
3332 * Probe for the phy according to the given phy_addr, and execute
3333 * the read request on it
3334 */
3335 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3336 if (params->phy[phy_index].addr == phy_addr) {
3337 return bnx2x_cl45_read(params->bp,
3338 &params->phy[phy_index], devad,
3339 reg, ret_val);
3340 }
3341 }
3342 return -EINVAL;
3343 }
3344
3345 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3346 u8 devad, u16 reg, u16 val)
3347 {
3348 u8 phy_index;
3349 /*
3350 * Probe for the phy according to the given phy_addr, and execute
3351 * the write request on it
3352 */
3353 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3354 if (params->phy[phy_index].addr == phy_addr) {
3355 return bnx2x_cl45_write(params->bp,
3356 &params->phy[phy_index], devad,
3357 reg, val);
3358 }
3359 }
3360 return -EINVAL;
3361 }
3362 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3363 struct link_params *params)
3364 {
3365 u8 lane = 0;
3366 struct bnx2x *bp = params->bp;
3367 u32 path_swap, path_swap_ovr;
3368 u8 path, port;
3369
3370 path = BP_PATH(bp);
3371 port = params->port;
3372
3373 if (bnx2x_is_4_port_mode(bp)) {
3374 u32 port_swap, port_swap_ovr;
3375
3376 /*figure out path swap value */
3377 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3378 if (path_swap_ovr & 0x1)
3379 path_swap = (path_swap_ovr & 0x2);
3380 else
3381 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3382
3383 if (path_swap)
3384 path = path ^ 1;
3385
3386 /*figure out port swap value */
3387 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3388 if (port_swap_ovr & 0x1)
3389 port_swap = (port_swap_ovr & 0x2);
3390 else
3391 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3392
3393 if (port_swap)
3394 port = port ^ 1;
3395
3396 lane = (port<<1) + path;
3397 } else { /* two port mode - no port swap */
3398
3399 /*figure out path swap value */
3400 path_swap_ovr =
3401 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3402 if (path_swap_ovr & 0x1) {
3403 path_swap = (path_swap_ovr & 0x2);
3404 } else {
3405 path_swap =
3406 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3407 }
3408 if (path_swap)
3409 path = path ^ 1;
3410
3411 lane = path << 1 ;
3412 }
3413 return lane;
3414 }
3415
3416 static void bnx2x_set_aer_mmd(struct link_params *params,
3417 struct bnx2x_phy *phy)
3418 {
3419 u32 ser_lane;
3420 u16 offset, aer_val;
3421 struct bnx2x *bp = params->bp;
3422 ser_lane = ((params->lane_config &
3423 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3424 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3425
3426 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3427 (phy->addr + ser_lane) : 0;
3428
3429 if (USES_WARPCORE(bp)) {
3430 aer_val = bnx2x_get_warpcore_lane(phy, params);
3431 /*
3432 * In Dual-lane mode, two lanes are joined together,
3433 * so in order to configure them, the AER broadcast method is
3434 * used here.
3435 * 0x200 is the broadcast address for lanes 0,1
3436 * 0x201 is the broadcast address for lanes 2,3
3437 */
3438 if (phy->flags & FLAGS_WC_DUAL_MODE)
3439 aer_val = (aer_val >> 1) | 0x200;
3440 } else if (CHIP_IS_E2(bp))
3441 aer_val = 0x3800 + offset - 1;
3442 else
3443 aer_val = 0x3800 + offset;
3444
3445 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3446 MDIO_AER_BLOCK_AER_REG, aer_val);
3447
3448 }
3449
3450 /******************************************************************/
3451 /* Internal phy section */
3452 /******************************************************************/
3453
3454 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3455 {
3456 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3457
3458 /* Set Clause 22 */
3459 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3460 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3461 udelay(500);
3462 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3463 udelay(500);
3464 /* Set Clause 45 */
3465 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3466 }
3467
3468 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3469 {
3470 u32 val;
3471
3472 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3473
3474 val = SERDES_RESET_BITS << (port*16);
3475
3476 /* reset and unreset the SerDes/XGXS */
3477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3478 udelay(500);
3479 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3480
3481 bnx2x_set_serdes_access(bp, port);
3482
3483 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3484 DEFAULT_PHY_DEV_ADDR);
3485 }
3486
3487 static void bnx2x_xgxs_deassert(struct link_params *params)
3488 {
3489 struct bnx2x *bp = params->bp;
3490 u8 port;
3491 u32 val;
3492 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3493 port = params->port;
3494
3495 val = XGXS_RESET_BITS << (port*16);
3496
3497 /* reset and unreset the SerDes/XGXS */
3498 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3499 udelay(500);
3500 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3501
3502 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3503 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3504 params->phy[INT_PHY].def_md_devad);
3505 }
3506
3507 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3508 struct link_params *params, u16 *ieee_fc)
3509 {
3510 struct bnx2x *bp = params->bp;
3511 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3512 /**
3513 * resolve pause mode and advertisement Please refer to Table
3514 * 28B-3 of the 802.3ab-1999 spec
3515 */
3516
3517 switch (phy->req_flow_ctrl) {
3518 case BNX2X_FLOW_CTRL_AUTO:
3519 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3520 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3521 else
3522 *ieee_fc |=
3523 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3524 break;
3525
3526 case BNX2X_FLOW_CTRL_TX:
3527 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3528 break;
3529
3530 case BNX2X_FLOW_CTRL_RX:
3531 case BNX2X_FLOW_CTRL_BOTH:
3532 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3533 break;
3534
3535 case BNX2X_FLOW_CTRL_NONE:
3536 default:
3537 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3538 break;
3539 }
3540 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3541 }
3542
3543 static void set_phy_vars(struct link_params *params,
3544 struct link_vars *vars)
3545 {
3546 struct bnx2x *bp = params->bp;
3547 u8 actual_phy_idx, phy_index, link_cfg_idx;
3548 u8 phy_config_swapped = params->multi_phy_config &
3549 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3550 for (phy_index = INT_PHY; phy_index < params->num_phys;
3551 phy_index++) {
3552 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3553 actual_phy_idx = phy_index;
3554 if (phy_config_swapped) {
3555 if (phy_index == EXT_PHY1)
3556 actual_phy_idx = EXT_PHY2;
3557 else if (phy_index == EXT_PHY2)
3558 actual_phy_idx = EXT_PHY1;
3559 }
3560 params->phy[actual_phy_idx].req_flow_ctrl =
3561 params->req_flow_ctrl[link_cfg_idx];
3562
3563 params->phy[actual_phy_idx].req_line_speed =
3564 params->req_line_speed[link_cfg_idx];
3565
3566 params->phy[actual_phy_idx].speed_cap_mask =
3567 params->speed_cap_mask[link_cfg_idx];
3568
3569 params->phy[actual_phy_idx].req_duplex =
3570 params->req_duplex[link_cfg_idx];
3571
3572 if (params->req_line_speed[link_cfg_idx] ==
3573 SPEED_AUTO_NEG)
3574 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3575
3576 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3577 " speed_cap_mask %x\n",
3578 params->phy[actual_phy_idx].req_flow_ctrl,
3579 params->phy[actual_phy_idx].req_line_speed,
3580 params->phy[actual_phy_idx].speed_cap_mask);
3581 }
3582 }
3583
3584 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3585 struct bnx2x_phy *phy,
3586 struct link_vars *vars)
3587 {
3588 u16 val;
3589 struct bnx2x *bp = params->bp;
3590 /* read modify write pause advertizing */
3591 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3592
3593 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3594
3595 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3596 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3597 if ((vars->ieee_fc &
3598 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3599 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3600 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3601 }
3602 if ((vars->ieee_fc &
3603 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3604 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3605 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3606 }
3607 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3608 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3609 }
3610
3611 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3612 { /* LD LP */
3613 switch (pause_result) { /* ASYM P ASYM P */
3614 case 0xb: /* 1 0 1 1 */
3615 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3616 break;
3617
3618 case 0xe: /* 1 1 1 0 */
3619 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3620 break;
3621
3622 case 0x5: /* 0 1 0 1 */
3623 case 0x7: /* 0 1 1 1 */
3624 case 0xd: /* 1 1 0 1 */
3625 case 0xf: /* 1 1 1 1 */
3626 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3627 break;
3628
3629 default:
3630 break;
3631 }
3632 if (pause_result & (1<<0))
3633 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3634 if (pause_result & (1<<1))
3635 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3636 }
3637
3638 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3639 struct link_params *params,
3640 struct link_vars *vars)
3641 {
3642 struct bnx2x *bp = params->bp;
3643 u16 ld_pause; /* local */
3644 u16 lp_pause; /* link partner */
3645 u16 pause_result;
3646 u8 ret = 0;
3647 /* read twice */
3648
3649 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3650
3651 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3652 vars->flow_ctrl = phy->req_flow_ctrl;
3653 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3654 vars->flow_ctrl = params->req_fc_auto_adv;
3655 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3656 ret = 1;
3657 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3658 bnx2x_cl22_read(bp, phy,
3659 0x4, &ld_pause);
3660 bnx2x_cl22_read(bp, phy,
3661 0x5, &lp_pause);
3662 } else {
3663 bnx2x_cl45_read(bp, phy,
3664 MDIO_AN_DEVAD,
3665 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3666 bnx2x_cl45_read(bp, phy,
3667 MDIO_AN_DEVAD,
3668 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3669 }
3670 pause_result = (ld_pause &
3671 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3672 pause_result |= (lp_pause &
3673 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3674 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3675 pause_result);
3676 bnx2x_pause_resolve(vars, pause_result);
3677 }
3678 return ret;
3679 }
3680 /******************************************************************/
3681 /* Warpcore section */
3682 /******************************************************************/
3683 /* The init_internal_warpcore should mirror the xgxs,
3684 * i.e. reset the lane (if needed), set aer for the
3685 * init configuration, and set/clear SGMII flag. Internal
3686 * phy init is done purely in phy_init stage.
3687 */
3688 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3689 struct link_params *params,
3690 struct link_vars *vars) {
3691 u16 val16 = 0, lane, bam37 = 0;
3692 struct bnx2x *bp = params->bp;
3693 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3694
3695 /* Disable Autoneg: re-enable it after adv is done. */
3696 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3697 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3698
3699 /* Check adding advertisement for 1G KX */
3700 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3701 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3702 (vars->line_speed == SPEED_1000)) {
3703 u16 sd_digital;
3704 val16 |= (1<<5);
3705
3706 /* Enable CL37 1G Parallel Detect */
3707 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3708 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3709 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3710 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3711 (sd_digital | 0x1));
3712
3713 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3714 }
3715 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3716 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3717 (vars->line_speed == SPEED_10000)) {
3718 /* Check adding advertisement for 10G KR */
3719 val16 |= (1<<7);
3720 /* Enable 10G Parallel Detect */
3721 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3722 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3723
3724 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3725 }
3726
3727 /* Set Transmit PMD settings */
3728 lane = bnx2x_get_warpcore_lane(phy, params);
3729 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3730 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3731 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3732 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3733 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3734 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3735 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3736 0x03f0);
3737 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3738 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3739 0x03f0);
3740
3741 /* Advertised speeds */
3742 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3743 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3744
3745 /* Advertised and set FEC (Forward Error Correction) */
3746 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3747 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3748 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3749 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3750
3751 /* Enable CL37 BAM */
3752 if (REG_RD(bp, params->shmem_base +
3753 offsetof(struct shmem_region, dev_info.
3754 port_hw_config[params->port].default_cfg)) &
3755 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3756 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3757 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3758 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3759 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3760 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3761 }
3762
3763 /* Advertise pause */
3764 bnx2x_ext_phy_set_pause(params, phy, vars);
3765
3766 /*
3767 * Set KR Autoneg Work-Around flag for Warpcore version older than D108
3768 */
3769 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3770 MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
3771 if (val16 < 0xd108) {
3772 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
3773 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3774 }
3775
3776 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3777 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3778
3779 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3780 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3781
3782 /* Over 1G - AN local device user page 1 */
3783 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3784 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3785
3786 /* Enable Autoneg */
3787 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3788 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3789
3790 }
3791
3792 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3793 struct link_params *params,
3794 struct link_vars *vars)
3795 {
3796 struct bnx2x *bp = params->bp;
3797 u16 val;
3798
3799 /* Disable Autoneg */
3800 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3801 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3802
3803 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3804 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3805
3806 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3807 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3808
3809 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3810 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3811
3812 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3813 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3814
3815 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3816 MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3817
3818 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3819 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3820
3821 /* Disable CL36 PCS Tx */
3822 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3823 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3824
3825 /* Double Wide Single Data Rate @ pll rate */
3826 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3827 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3828
3829 /* Leave cl72 training enable, needed for KR */
3830 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3831 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3832 0x2);
3833
3834 /* Leave CL72 enabled */
3835 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3836 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3837 &val);
3838 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3839 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3840 val | 0x3800);
3841
3842 /* Set speed via PMA/PMD register */
3843 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3844 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3845
3846 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3847 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3848
3849 /*Enable encoded forced speed */
3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3852
3853 /* Turn TX scramble payload only the 64/66 scrambler */
3854 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3855 MDIO_WC_REG_TX66_CONTROL, 0x9);
3856
3857 /* Turn RX scramble payload only the 64/66 scrambler */
3858 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3859 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3860
3861 /* set and clear loopback to cause a reset to 64/66 decoder */
3862 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3863 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3864 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3865 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3866
3867 }
3868
3869 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3870 struct link_params *params,
3871 u8 is_xfi)
3872 {
3873 struct bnx2x *bp = params->bp;
3874 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3875 /* Hold rxSeqStart */
3876 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3877 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3878 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3880
3881 /* Hold tx_fifo_reset */
3882 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3883 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3884 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3885 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3886
3887 /* Disable CL73 AN */
3888 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3889
3890 /* Disable 100FX Enable and Auto-Detect */
3891 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3892 MDIO_WC_REG_FX100_CTRL1, &val);
3893 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3895
3896 /* Disable 100FX Idle detect */
3897 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3898 MDIO_WC_REG_FX100_CTRL3, &val);
3899 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3901
3902 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3903 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3904 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3905 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3906 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3907
3908 /* Turn off auto-detect & fiber mode */
3909 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3910 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3911 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3912 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3913 (val & 0xFFEE));
3914
3915 /* Set filter_force_link, disable_false_link and parallel_detect */
3916 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3917 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3918 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3919 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3920 ((val | 0x0006) & 0xFFFE));
3921
3922 /* Set XFI / SFI */
3923 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3924 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3925
3926 misc1_val &= ~(0x1f);
3927
3928 if (is_xfi) {
3929 misc1_val |= 0x5;
3930 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3931 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3932 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3933 tx_driver_val =
3934 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3935 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3936 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3937
3938 } else {
3939 misc1_val |= 0x9;
3940 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3941 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3942 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3943 tx_driver_val =
3944 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3945 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3946 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3947 }
3948 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3949 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3950
3951 /* Set Transmit PMD settings */
3952 lane = bnx2x_get_warpcore_lane(phy, params);
3953 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3954 MDIO_WC_REG_TX_FIR_TAP,
3955 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3956 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3957 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3958 tx_driver_val);
3959
3960 /* Enable fiber mode, enable and invert sig_det */
3961 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3962 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3963 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3964 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3965
3966 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3967 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3968 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3969 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3970 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3971
3972 /* 10G XFI Full Duplex */
3973 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3974 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3975
3976 /* Release tx_fifo_reset */
3977 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3978 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3979 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3980 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3981
3982 /* Release rxSeqStart */
3983 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3984 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3985 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3986 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3987 }
3988
3989 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3990 struct bnx2x_phy *phy)
3991 {
3992 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3993 }
3994
3995 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3996 struct bnx2x_phy *phy,
3997 u16 lane)
3998 {
3999 /* Rx0 anaRxControl1G */
4000 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4001 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4002
4003 /* Rx2 anaRxControl1G */
4004 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4005 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4006
4007 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4008 MDIO_WC_REG_RX66_SCW0, 0xE070);
4009
4010 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4011 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4012
4013 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4014 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4015
4016 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4017 MDIO_WC_REG_RX66_SCW3, 0x8090);
4018
4019 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4020 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4021
4022 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4024
4025 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4026 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4027
4028 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4029 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4030
4031 /* Serdes Digital Misc1 */
4032 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4033 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4034
4035 /* Serdes Digital4 Misc3 */
4036 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4037 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4038
4039 /* Set Transmit PMD settings */
4040 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041 MDIO_WC_REG_TX_FIR_TAP,
4042 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4043 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4044 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4045 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4046 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4047 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4048 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4049 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4050 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4051 }
4052
4053 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4054 struct link_params *params,
4055 u8 fiber_mode,
4056 u8 always_autoneg)
4057 {
4058 struct bnx2x *bp = params->bp;
4059 u16 val16, digctrl_kx1, digctrl_kx2;
4060
4061 /* Clear XFI clock comp in non-10G single lane mode. */
4062 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4063 MDIO_WC_REG_RX66_CONTROL, &val16);
4064 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
4066
4067 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4068 /* SGMII Autoneg */
4069 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4070 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4071 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4072 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4073 val16 | 0x1000);
4074 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4075 } else {
4076 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4077 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4078 val16 &= 0xcebf;
4079 switch (phy->req_line_speed) {
4080 case SPEED_10:
4081 break;
4082 case SPEED_100:
4083 val16 |= 0x2000;
4084 break;
4085 case SPEED_1000:
4086 val16 |= 0x0040;
4087 break;
4088 default:
4089 DP(NETIF_MSG_LINK,
4090 "Speed not supported: 0x%x\n", phy->req_line_speed);
4091 return;
4092 }
4093
4094 if (phy->req_duplex == DUPLEX_FULL)
4095 val16 |= 0x0100;
4096
4097 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4099
4100 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4101 phy->req_line_speed);
4102 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4103 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4104 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4105 }
4106
4107 /* SGMII Slave mode and disable signal detect */
4108 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4109 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4110 if (fiber_mode)
4111 digctrl_kx1 = 1;
4112 else
4113 digctrl_kx1 &= 0xff4a;
4114
4115 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4116 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4117 digctrl_kx1);
4118
4119 /* Turn off parallel detect */
4120 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4121 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4122 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4123 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4124 (digctrl_kx2 & ~(1<<2)));
4125
4126 /* Re-enable parallel detect */
4127 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4128 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4129 (digctrl_kx2 | (1<<2)));
4130
4131 /* Enable autodet */
4132 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4133 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4134 (digctrl_kx1 | 0x10));
4135 }
4136
4137 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4138 struct bnx2x_phy *phy,
4139 u8 reset)
4140 {
4141 u16 val;
4142 /* Take lane out of reset after configuration is finished */
4143 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4144 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4145 if (reset)
4146 val |= 0xC000;
4147 else
4148 val &= 0x3FFF;
4149 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4150 MDIO_WC_REG_DIGITAL5_MISC6, val);
4151 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4152 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4153 }
4154 /* Clear SFI/XFI link settings registers */
4155 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4156 struct link_params *params,
4157 u16 lane)
4158 {
4159 struct bnx2x *bp = params->bp;
4160 u16 val16;
4161
4162 /* Set XFI clock comp as default. */
4163 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4164 MDIO_WC_REG_RX66_CONTROL, &val16);
4165 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4166 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4167
4168 bnx2x_warpcore_reset_lane(bp, phy, 1);
4169 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4170 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4171 MDIO_WC_REG_FX100_CTRL1, 0x014a);
4172 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173 MDIO_WC_REG_FX100_CTRL3, 0x0800);
4174 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4175 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4176 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4177 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4178 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4179 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4180 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4181 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4182 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4183 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4184 lane = bnx2x_get_warpcore_lane(phy, params);
4185 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4186 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4187 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4188 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4189 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4190 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4191 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4192 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4193 bnx2x_warpcore_reset_lane(bp, phy, 0);
4194 }
4195
4196 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4197 u32 chip_id,
4198 u32 shmem_base, u8 port,
4199 u8 *gpio_num, u8 *gpio_port)
4200 {
4201 u32 cfg_pin;
4202 *gpio_num = 0;
4203 *gpio_port = 0;
4204 if (CHIP_IS_E3(bp)) {
4205 cfg_pin = (REG_RD(bp, shmem_base +
4206 offsetof(struct shmem_region,
4207 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4208 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4209 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4210
4211 /*
4212 * Should not happen. This function called upon interrupt
4213 * triggered by GPIO ( since EPIO can only generate interrupts
4214 * to MCP).
4215 * So if this function was called and none of the GPIOs was set,
4216 * it means the shit hit the fan.
4217 */
4218 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4219 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4220 DP(NETIF_MSG_LINK,
4221 "ERROR: Invalid cfg pin %x for module detect indication\n",
4222 cfg_pin);
4223 return -EINVAL;
4224 }
4225
4226 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4227 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4228 } else {
4229 *gpio_num = MISC_REGISTERS_GPIO_3;
4230 *gpio_port = port;
4231 }
4232 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4233 return 0;
4234 }
4235
4236 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4237 struct link_params *params)
4238 {
4239 struct bnx2x *bp = params->bp;
4240 u8 gpio_num, gpio_port;
4241 u32 gpio_val;
4242 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4243 params->shmem_base, params->port,
4244 &gpio_num, &gpio_port) != 0)
4245 return 0;
4246 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4247
4248 /* Call the handling function in case module is detected */
4249 if (gpio_val == 0)
4250 return 1;
4251 else
4252 return 0;
4253 }
4254 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4255 struct link_params *params)
4256 {
4257 u16 gp2_status_reg0, lane;
4258 struct bnx2x *bp = params->bp;
4259
4260 lane = bnx2x_get_warpcore_lane(phy, params);
4261
4262 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4263 &gp2_status_reg0);
4264
4265 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4266 }
4267
4268 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4269 struct link_params *params,
4270 struct link_vars *vars)
4271 {
4272 struct bnx2x *bp = params->bp;
4273 u32 serdes_net_if;
4274 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4275 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4276
4277 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4278
4279 if (!vars->turn_to_run_wc_rt)
4280 return;
4281
4282 /* return if there is no link partner */
4283 if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4284 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4285 return;
4286 }
4287
4288 if (vars->rx_tx_asic_rst) {
4289 serdes_net_if = (REG_RD(bp, params->shmem_base +
4290 offsetof(struct shmem_region, dev_info.
4291 port_hw_config[params->port].default_cfg)) &
4292 PORT_HW_CFG_NET_SERDES_IF_MASK);
4293
4294 switch (serdes_net_if) {
4295 case PORT_HW_CFG_NET_SERDES_IF_KR:
4296 /* Do we get link yet? */
4297 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4298 &gp_status1);
4299 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4300 /*10G KR*/
4301 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4302
4303 DP(NETIF_MSG_LINK,
4304 "gp_status1 0x%x\n", gp_status1);
4305
4306 if (lnkup_kr || lnkup) {
4307 vars->rx_tx_asic_rst = 0;
4308 DP(NETIF_MSG_LINK,
4309 "link up, rx_tx_asic_rst 0x%x\n",
4310 vars->rx_tx_asic_rst);
4311 } else {
4312 /*reset the lane to see if link comes up.*/
4313 bnx2x_warpcore_reset_lane(bp, phy, 1);
4314 bnx2x_warpcore_reset_lane(bp, phy, 0);
4315
4316 /* restart Autoneg */
4317 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4318 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4319
4320 vars->rx_tx_asic_rst--;
4321 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4322 vars->rx_tx_asic_rst);
4323 }
4324 break;
4325
4326 default:
4327 break;
4328 }
4329
4330 } /*params->rx_tx_asic_rst*/
4331
4332 }
4333
4334 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4335 struct link_params *params,
4336 struct link_vars *vars)
4337 {
4338 struct bnx2x *bp = params->bp;
4339 u32 serdes_net_if;
4340 u8 fiber_mode;
4341 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4342 serdes_net_if = (REG_RD(bp, params->shmem_base +
4343 offsetof(struct shmem_region, dev_info.
4344 port_hw_config[params->port].default_cfg)) &
4345 PORT_HW_CFG_NET_SERDES_IF_MASK);
4346 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4347 "serdes_net_if = 0x%x\n",
4348 vars->line_speed, serdes_net_if);
4349 bnx2x_set_aer_mmd(params, phy);
4350
4351 vars->phy_flags |= PHY_XGXS_FLAG;
4352 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4353 (phy->req_line_speed &&
4354 ((phy->req_line_speed == SPEED_100) ||
4355 (phy->req_line_speed == SPEED_10)))) {
4356 vars->phy_flags |= PHY_SGMII_FLAG;
4357 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4358 bnx2x_warpcore_clear_regs(phy, params, lane);
4359 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4360 } else {
4361 switch (serdes_net_if) {
4362 case PORT_HW_CFG_NET_SERDES_IF_KR:
4363 /* Enable KR Auto Neg */
4364 if (params->loopback_mode == LOOPBACK_NONE)
4365 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4366 else {
4367 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4368 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4369 }
4370 break;
4371
4372 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4373 bnx2x_warpcore_clear_regs(phy, params, lane);
4374 if (vars->line_speed == SPEED_10000) {
4375 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4376 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4377 } else {
4378 if (SINGLE_MEDIA_DIRECT(params)) {
4379 DP(NETIF_MSG_LINK, "1G Fiber\n");
4380 fiber_mode = 1;
4381 } else {
4382 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4383 fiber_mode = 0;
4384 }
4385 bnx2x_warpcore_set_sgmii_speed(phy,
4386 params,
4387 fiber_mode,
4388 0);
4389 }
4390
4391 break;
4392
4393 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4394
4395 bnx2x_warpcore_clear_regs(phy, params, lane);
4396 if (vars->line_speed == SPEED_10000) {
4397 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4398 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4399 } else if (vars->line_speed == SPEED_1000) {
4400 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4401 bnx2x_warpcore_set_sgmii_speed(
4402 phy, params, 1, 0);
4403 }
4404 /* Issue Module detection */
4405 if (bnx2x_is_sfp_module_plugged(phy, params))
4406 bnx2x_sfp_module_detection(phy, params);
4407 break;
4408
4409 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4410 if (vars->line_speed != SPEED_20000) {
4411 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4412 return;
4413 }
4414 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4415 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4416 /* Issue Module detection */
4417
4418 bnx2x_sfp_module_detection(phy, params);
4419 break;
4420
4421 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4422 if (vars->line_speed != SPEED_20000) {
4423 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4424 return;
4425 }
4426 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4427 bnx2x_warpcore_set_20G_KR2(bp, phy);
4428 break;
4429
4430 default:
4431 DP(NETIF_MSG_LINK,
4432 "Unsupported Serdes Net Interface 0x%x\n",
4433 serdes_net_if);
4434 return;
4435 }
4436 }
4437
4438 /* Take lane out of reset after configuration is finished */
4439 bnx2x_warpcore_reset_lane(bp, phy, 0);
4440 DP(NETIF_MSG_LINK, "Exit config init\n");
4441 }
4442
4443 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4444 struct bnx2x_phy *phy,
4445 u8 tx_en)
4446 {
4447 struct bnx2x *bp = params->bp;
4448 u32 cfg_pin;
4449 u8 port = params->port;
4450
4451 cfg_pin = REG_RD(bp, params->shmem_base +
4452 offsetof(struct shmem_region,
4453 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4454 PORT_HW_CFG_TX_LASER_MASK;
4455 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4456 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4457 /* For 20G, the expected pin to be used is 3 pins after the current */
4458
4459 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4460 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4461 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4462 }
4463
4464 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4465 struct link_params *params)
4466 {
4467 struct bnx2x *bp = params->bp;
4468 u16 val16;
4469 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4470 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4471 bnx2x_set_aer_mmd(params, phy);
4472 /* Global register */
4473 bnx2x_warpcore_reset_lane(bp, phy, 1);
4474
4475 /* Clear loopback settings (if any) */
4476 /* 10G & 20G */
4477 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4478 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4479 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4480 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4481 0xBFFF);
4482
4483 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4484 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4485 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4486 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4487
4488 /* Update those 1-copy registers */
4489 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4490 MDIO_AER_BLOCK_AER_REG, 0);
4491 /* Enable 1G MDIO (1-copy) */
4492 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4493 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4494 &val16);
4495 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4496 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4497 val16 & ~0x10);
4498
4499 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4500 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4501 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4502 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4503 val16 & 0xff00);
4504
4505 }
4506
4507 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4508 struct link_params *params)
4509 {
4510 struct bnx2x *bp = params->bp;
4511 u16 val16;
4512 u32 lane;
4513 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4514 params->loopback_mode, phy->req_line_speed);
4515
4516 if (phy->req_line_speed < SPEED_10000) {
4517 /* 10/100/1000 */
4518
4519 /* Update those 1-copy registers */
4520 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4521 MDIO_AER_BLOCK_AER_REG, 0);
4522 /* Enable 1G MDIO (1-copy) */
4523 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4524 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4525 &val16);
4526 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4527 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4528 val16 | 0x10);
4529 /* Set 1G loopback based on lane (1-copy) */
4530 lane = bnx2x_get_warpcore_lane(phy, params);
4531 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4532 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4533 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4534 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4535 val16 | (1<<lane));
4536
4537 /* Switch back to 4-copy registers */
4538 bnx2x_set_aer_mmd(params, phy);
4539 } else {
4540 /* 10G & 20G */
4541 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4542 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4543 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4544 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4545 0x4000);
4546
4547 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4548 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4549 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4550 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4551 }
4552 }
4553
4554
4555 void bnx2x_sync_link(struct link_params *params,
4556 struct link_vars *vars)
4557 {
4558 struct bnx2x *bp = params->bp;
4559 u8 link_10g_plus;
4560 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4561 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4562 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4563 if (vars->link_up) {
4564 DP(NETIF_MSG_LINK, "phy link up\n");
4565
4566 vars->phy_link_up = 1;
4567 vars->duplex = DUPLEX_FULL;
4568 switch (vars->link_status &
4569 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4570 case LINK_10THD:
4571 vars->duplex = DUPLEX_HALF;
4572 /* fall thru */
4573 case LINK_10TFD:
4574 vars->line_speed = SPEED_10;
4575 break;
4576
4577 case LINK_100TXHD:
4578 vars->duplex = DUPLEX_HALF;
4579 /* fall thru */
4580 case LINK_100T4:
4581 case LINK_100TXFD:
4582 vars->line_speed = SPEED_100;
4583 break;
4584
4585 case LINK_1000THD:
4586 vars->duplex = DUPLEX_HALF;
4587 /* fall thru */
4588 case LINK_1000TFD:
4589 vars->line_speed = SPEED_1000;
4590 break;
4591
4592 case LINK_2500THD:
4593 vars->duplex = DUPLEX_HALF;
4594 /* fall thru */
4595 case LINK_2500TFD:
4596 vars->line_speed = SPEED_2500;
4597 break;
4598
4599 case LINK_10GTFD:
4600 vars->line_speed = SPEED_10000;
4601 break;
4602 case LINK_20GTFD:
4603 vars->line_speed = SPEED_20000;
4604 break;
4605 default:
4606 break;
4607 }
4608 vars->flow_ctrl = 0;
4609 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4610 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4611
4612 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4613 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4614
4615 if (!vars->flow_ctrl)
4616 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4617
4618 if (vars->line_speed &&
4619 ((vars->line_speed == SPEED_10) ||
4620 (vars->line_speed == SPEED_100))) {
4621 vars->phy_flags |= PHY_SGMII_FLAG;
4622 } else {
4623 vars->phy_flags &= ~PHY_SGMII_FLAG;
4624 }
4625 if (vars->line_speed &&
4626 USES_WARPCORE(bp) &&
4627 (vars->line_speed == SPEED_1000))
4628 vars->phy_flags |= PHY_SGMII_FLAG;
4629 /* anything 10 and over uses the bmac */
4630 link_10g_plus = (vars->line_speed >= SPEED_10000);
4631
4632 if (link_10g_plus) {
4633 if (USES_WARPCORE(bp))
4634 vars->mac_type = MAC_TYPE_XMAC;
4635 else
4636 vars->mac_type = MAC_TYPE_BMAC;
4637 } else {
4638 if (USES_WARPCORE(bp))
4639 vars->mac_type = MAC_TYPE_UMAC;
4640 else
4641 vars->mac_type = MAC_TYPE_EMAC;
4642 }
4643 } else { /* link down */
4644 DP(NETIF_MSG_LINK, "phy link down\n");
4645
4646 vars->phy_link_up = 0;
4647
4648 vars->line_speed = 0;
4649 vars->duplex = DUPLEX_FULL;
4650 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4651
4652 /* indicate no mac active */
4653 vars->mac_type = MAC_TYPE_NONE;
4654 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4655 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4656 }
4657 }
4658
4659 void bnx2x_link_status_update(struct link_params *params,
4660 struct link_vars *vars)
4661 {
4662 struct bnx2x *bp = params->bp;
4663 u8 port = params->port;
4664 u32 sync_offset, media_types;
4665 /* Update PHY configuration */
4666 set_phy_vars(params, vars);
4667
4668 vars->link_status = REG_RD(bp, params->shmem_base +
4669 offsetof(struct shmem_region,
4670 port_mb[port].link_status));
4671
4672 vars->phy_flags = PHY_XGXS_FLAG;
4673 bnx2x_sync_link(params, vars);
4674 /* Sync media type */
4675 sync_offset = params->shmem_base +
4676 offsetof(struct shmem_region,
4677 dev_info.port_hw_config[port].media_type);
4678 media_types = REG_RD(bp, sync_offset);
4679
4680 params->phy[INT_PHY].media_type =
4681 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4682 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4683 params->phy[EXT_PHY1].media_type =
4684 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4685 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4686 params->phy[EXT_PHY2].media_type =
4687 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4688 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4689 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4690
4691 /* Sync AEU offset */
4692 sync_offset = params->shmem_base +
4693 offsetof(struct shmem_region,
4694 dev_info.port_hw_config[port].aeu_int_mask);
4695
4696 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4697
4698 /* Sync PFC status */
4699 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4700 params->feature_config_flags |=
4701 FEATURE_CONFIG_PFC_ENABLED;
4702 else
4703 params->feature_config_flags &=
4704 ~FEATURE_CONFIG_PFC_ENABLED;
4705
4706 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4707 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4708 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4709 vars->line_speed, vars->duplex, vars->flow_ctrl);
4710 }
4711
4712 static void bnx2x_set_master_ln(struct link_params *params,
4713 struct bnx2x_phy *phy)
4714 {
4715 struct bnx2x *bp = params->bp;
4716 u16 new_master_ln, ser_lane;
4717 ser_lane = ((params->lane_config &
4718 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4719 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4720
4721 /* set the master_ln for AN */
4722 CL22_RD_OVER_CL45(bp, phy,
4723 MDIO_REG_BANK_XGXS_BLOCK2,
4724 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4725 &new_master_ln);
4726
4727 CL22_WR_OVER_CL45(bp, phy,
4728 MDIO_REG_BANK_XGXS_BLOCK2 ,
4729 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4730 (new_master_ln | ser_lane));
4731 }
4732
4733 static int bnx2x_reset_unicore(struct link_params *params,
4734 struct bnx2x_phy *phy,
4735 u8 set_serdes)
4736 {
4737 struct bnx2x *bp = params->bp;
4738 u16 mii_control;
4739 u16 i;
4740 CL22_RD_OVER_CL45(bp, phy,
4741 MDIO_REG_BANK_COMBO_IEEE0,
4742 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4743
4744 /* reset the unicore */
4745 CL22_WR_OVER_CL45(bp, phy,
4746 MDIO_REG_BANK_COMBO_IEEE0,
4747 MDIO_COMBO_IEEE0_MII_CONTROL,
4748 (mii_control |
4749 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4750 if (set_serdes)
4751 bnx2x_set_serdes_access(bp, params->port);
4752
4753 /* wait for the reset to self clear */
4754 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4755 udelay(5);
4756
4757 /* the reset erased the previous bank value */
4758 CL22_RD_OVER_CL45(bp, phy,
4759 MDIO_REG_BANK_COMBO_IEEE0,
4760 MDIO_COMBO_IEEE0_MII_CONTROL,
4761 &mii_control);
4762
4763 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4764 udelay(5);
4765 return 0;
4766 }
4767 }
4768
4769 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4770 " Port %d\n",
4771 params->port);
4772 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4773 return -EINVAL;
4774
4775 }
4776
4777 static void bnx2x_set_swap_lanes(struct link_params *params,
4778 struct bnx2x_phy *phy)
4779 {
4780 struct bnx2x *bp = params->bp;
4781 /*
4782 * Each two bits represents a lane number:
4783 * No swap is 0123 => 0x1b no need to enable the swap
4784 */
4785 u16 rx_lane_swap, tx_lane_swap;
4786
4787 rx_lane_swap = ((params->lane_config &
4788 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4789 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4790 tx_lane_swap = ((params->lane_config &
4791 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4792 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4793
4794 if (rx_lane_swap != 0x1b) {
4795 CL22_WR_OVER_CL45(bp, phy,
4796 MDIO_REG_BANK_XGXS_BLOCK2,
4797 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4798 (rx_lane_swap |
4799 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4800 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4801 } else {
4802 CL22_WR_OVER_CL45(bp, phy,
4803 MDIO_REG_BANK_XGXS_BLOCK2,
4804 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4805 }
4806
4807 if (tx_lane_swap != 0x1b) {
4808 CL22_WR_OVER_CL45(bp, phy,
4809 MDIO_REG_BANK_XGXS_BLOCK2,
4810 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4811 (tx_lane_swap |
4812 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4813 } else {
4814 CL22_WR_OVER_CL45(bp, phy,
4815 MDIO_REG_BANK_XGXS_BLOCK2,
4816 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4817 }
4818 }
4819
4820 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4821 struct link_params *params)
4822 {
4823 struct bnx2x *bp = params->bp;
4824 u16 control2;
4825 CL22_RD_OVER_CL45(bp, phy,
4826 MDIO_REG_BANK_SERDES_DIGITAL,
4827 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4828 &control2);
4829 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4830 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4831 else
4832 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4833 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4834 phy->speed_cap_mask, control2);
4835 CL22_WR_OVER_CL45(bp, phy,
4836 MDIO_REG_BANK_SERDES_DIGITAL,
4837 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4838 control2);
4839
4840 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4841 (phy->speed_cap_mask &
4842 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4843 DP(NETIF_MSG_LINK, "XGXS\n");
4844
4845 CL22_WR_OVER_CL45(bp, phy,
4846 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4847 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4848 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4849
4850 CL22_RD_OVER_CL45(bp, phy,
4851 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4852 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4853 &control2);
4854
4855
4856 control2 |=
4857 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4858
4859 CL22_WR_OVER_CL45(bp, phy,
4860 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4861 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4862 control2);
4863
4864 /* Disable parallel detection of HiG */
4865 CL22_WR_OVER_CL45(bp, phy,
4866 MDIO_REG_BANK_XGXS_BLOCK2,
4867 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4868 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4869 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4870 }
4871 }
4872
4873 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4874 struct link_params *params,
4875 struct link_vars *vars,
4876 u8 enable_cl73)
4877 {
4878 struct bnx2x *bp = params->bp;
4879 u16 reg_val;
4880
4881 /* CL37 Autoneg */
4882 CL22_RD_OVER_CL45(bp, phy,
4883 MDIO_REG_BANK_COMBO_IEEE0,
4884 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4885
4886 /* CL37 Autoneg Enabled */
4887 if (vars->line_speed == SPEED_AUTO_NEG)
4888 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4889 else /* CL37 Autoneg Disabled */
4890 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4891 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4892
4893 CL22_WR_OVER_CL45(bp, phy,
4894 MDIO_REG_BANK_COMBO_IEEE0,
4895 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4896
4897 /* Enable/Disable Autodetection */
4898
4899 CL22_RD_OVER_CL45(bp, phy,
4900 MDIO_REG_BANK_SERDES_DIGITAL,
4901 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4902 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4903 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4904 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4905 if (vars->line_speed == SPEED_AUTO_NEG)
4906 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4907 else
4908 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4909
4910 CL22_WR_OVER_CL45(bp, phy,
4911 MDIO_REG_BANK_SERDES_DIGITAL,
4912 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4913
4914 /* Enable TetonII and BAM autoneg */
4915 CL22_RD_OVER_CL45(bp, phy,
4916 MDIO_REG_BANK_BAM_NEXT_PAGE,
4917 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4918 &reg_val);
4919 if (vars->line_speed == SPEED_AUTO_NEG) {
4920 /* Enable BAM aneg Mode and TetonII aneg Mode */
4921 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4922 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4923 } else {
4924 /* TetonII and BAM Autoneg Disabled */
4925 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4926 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4927 }
4928 CL22_WR_OVER_CL45(bp, phy,
4929 MDIO_REG_BANK_BAM_NEXT_PAGE,
4930 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4931 reg_val);
4932
4933 if (enable_cl73) {
4934 /* Enable Cl73 FSM status bits */
4935 CL22_WR_OVER_CL45(bp, phy,
4936 MDIO_REG_BANK_CL73_USERB0,
4937 MDIO_CL73_USERB0_CL73_UCTRL,
4938 0xe);
4939
4940 /* Enable BAM Station Manager*/
4941 CL22_WR_OVER_CL45(bp, phy,
4942 MDIO_REG_BANK_CL73_USERB0,
4943 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4944 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4945 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4946 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4947
4948 /* Advertise CL73 link speeds */
4949 CL22_RD_OVER_CL45(bp, phy,
4950 MDIO_REG_BANK_CL73_IEEEB1,
4951 MDIO_CL73_IEEEB1_AN_ADV2,
4952 &reg_val);
4953 if (phy->speed_cap_mask &
4954 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4955 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4956 if (phy->speed_cap_mask &
4957 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4958 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4959
4960 CL22_WR_OVER_CL45(bp, phy,
4961 MDIO_REG_BANK_CL73_IEEEB1,
4962 MDIO_CL73_IEEEB1_AN_ADV2,
4963 reg_val);
4964
4965 /* CL73 Autoneg Enabled */
4966 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4967
4968 } else /* CL73 Autoneg Disabled */
4969 reg_val = 0;
4970
4971 CL22_WR_OVER_CL45(bp, phy,
4972 MDIO_REG_BANK_CL73_IEEEB0,
4973 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4974 }
4975
4976 /* program SerDes, forced speed */
4977 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4978 struct link_params *params,
4979 struct link_vars *vars)
4980 {
4981 struct bnx2x *bp = params->bp;
4982 u16 reg_val;
4983
4984 /* program duplex, disable autoneg and sgmii*/
4985 CL22_RD_OVER_CL45(bp, phy,
4986 MDIO_REG_BANK_COMBO_IEEE0,
4987 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4988 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4989 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4990 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4991 if (phy->req_duplex == DUPLEX_FULL)
4992 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4993 CL22_WR_OVER_CL45(bp, phy,
4994 MDIO_REG_BANK_COMBO_IEEE0,
4995 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4996
4997 /*
4998 * program speed
4999 * - needed only if the speed is greater than 1G (2.5G or 10G)
5000 */
5001 CL22_RD_OVER_CL45(bp, phy,
5002 MDIO_REG_BANK_SERDES_DIGITAL,
5003 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5004 /* clearing the speed value before setting the right speed */
5005 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5006
5007 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5008 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5009
5010 if (!((vars->line_speed == SPEED_1000) ||
5011 (vars->line_speed == SPEED_100) ||
5012 (vars->line_speed == SPEED_10))) {
5013
5014 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5015 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5016 if (vars->line_speed == SPEED_10000)
5017 reg_val |=
5018 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5019 }
5020
5021 CL22_WR_OVER_CL45(bp, phy,
5022 MDIO_REG_BANK_SERDES_DIGITAL,
5023 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5024
5025 }
5026
5027 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5028 struct link_params *params)
5029 {
5030 struct bnx2x *bp = params->bp;
5031 u16 val = 0;
5032
5033 /* configure the 48 bits for BAM AN */
5034
5035 /* set extended capabilities */
5036 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5037 val |= MDIO_OVER_1G_UP1_2_5G;
5038 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5039 val |= MDIO_OVER_1G_UP1_10G;
5040 CL22_WR_OVER_CL45(bp, phy,
5041 MDIO_REG_BANK_OVER_1G,
5042 MDIO_OVER_1G_UP1, val);
5043
5044 CL22_WR_OVER_CL45(bp, phy,
5045 MDIO_REG_BANK_OVER_1G,
5046 MDIO_OVER_1G_UP3, 0x400);
5047 }
5048
5049 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5050 struct link_params *params,
5051 u16 ieee_fc)
5052 {
5053 struct bnx2x *bp = params->bp;
5054 u16 val;
5055 /* for AN, we are always publishing full duplex */
5056
5057 CL22_WR_OVER_CL45(bp, phy,
5058 MDIO_REG_BANK_COMBO_IEEE0,
5059 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5060 CL22_RD_OVER_CL45(bp, phy,
5061 MDIO_REG_BANK_CL73_IEEEB1,
5062 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5063 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5064 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5065 CL22_WR_OVER_CL45(bp, phy,
5066 MDIO_REG_BANK_CL73_IEEEB1,
5067 MDIO_CL73_IEEEB1_AN_ADV1, val);
5068 }
5069
5070 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5071 struct link_params *params,
5072 u8 enable_cl73)
5073 {
5074 struct bnx2x *bp = params->bp;
5075 u16 mii_control;
5076
5077 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5078 /* Enable and restart BAM/CL37 aneg */
5079
5080 if (enable_cl73) {
5081 CL22_RD_OVER_CL45(bp, phy,
5082 MDIO_REG_BANK_CL73_IEEEB0,
5083 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5084 &mii_control);
5085
5086 CL22_WR_OVER_CL45(bp, phy,
5087 MDIO_REG_BANK_CL73_IEEEB0,
5088 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5089 (mii_control |
5090 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5091 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5092 } else {
5093
5094 CL22_RD_OVER_CL45(bp, phy,
5095 MDIO_REG_BANK_COMBO_IEEE0,
5096 MDIO_COMBO_IEEE0_MII_CONTROL,
5097 &mii_control);
5098 DP(NETIF_MSG_LINK,
5099 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5100 mii_control);
5101 CL22_WR_OVER_CL45(bp, phy,
5102 MDIO_REG_BANK_COMBO_IEEE0,
5103 MDIO_COMBO_IEEE0_MII_CONTROL,
5104 (mii_control |
5105 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5106 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5107 }
5108 }
5109
5110 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5111 struct link_params *params,
5112 struct link_vars *vars)
5113 {
5114 struct bnx2x *bp = params->bp;
5115 u16 control1;
5116
5117 /* in SGMII mode, the unicore is always slave */
5118
5119 CL22_RD_OVER_CL45(bp, phy,
5120 MDIO_REG_BANK_SERDES_DIGITAL,
5121 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5122 &control1);
5123 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5124 /* set sgmii mode (and not fiber) */
5125 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5126 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5127 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5128 CL22_WR_OVER_CL45(bp, phy,
5129 MDIO_REG_BANK_SERDES_DIGITAL,
5130 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5131 control1);
5132
5133 /* if forced speed */
5134 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5135 /* set speed, disable autoneg */
5136 u16 mii_control;
5137
5138 CL22_RD_OVER_CL45(bp, phy,
5139 MDIO_REG_BANK_COMBO_IEEE0,
5140 MDIO_COMBO_IEEE0_MII_CONTROL,
5141 &mii_control);
5142 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5143 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5144 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5145
5146 switch (vars->line_speed) {
5147 case SPEED_100:
5148 mii_control |=
5149 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5150 break;
5151 case SPEED_1000:
5152 mii_control |=
5153 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5154 break;
5155 case SPEED_10:
5156 /* there is nothing to set for 10M */
5157 break;
5158 default:
5159 /* invalid speed for SGMII */
5160 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5161 vars->line_speed);
5162 break;
5163 }
5164
5165 /* setting the full duplex */
5166 if (phy->req_duplex == DUPLEX_FULL)
5167 mii_control |=
5168 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5169 CL22_WR_OVER_CL45(bp, phy,
5170 MDIO_REG_BANK_COMBO_IEEE0,
5171 MDIO_COMBO_IEEE0_MII_CONTROL,
5172 mii_control);
5173
5174 } else { /* AN mode */
5175 /* enable and restart AN */
5176 bnx2x_restart_autoneg(phy, params, 0);
5177 }
5178 }
5179
5180
5181 /*
5182 * link management
5183 */
5184
5185 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5186 struct link_params *params)
5187 {
5188 struct bnx2x *bp = params->bp;
5189 u16 pd_10g, status2_1000x;
5190 if (phy->req_line_speed != SPEED_AUTO_NEG)
5191 return 0;
5192 CL22_RD_OVER_CL45(bp, phy,
5193 MDIO_REG_BANK_SERDES_DIGITAL,
5194 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5195 &status2_1000x);
5196 CL22_RD_OVER_CL45(bp, phy,
5197 MDIO_REG_BANK_SERDES_DIGITAL,
5198 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5199 &status2_1000x);
5200 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5201 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5202 params->port);
5203 return 1;
5204 }
5205
5206 CL22_RD_OVER_CL45(bp, phy,
5207 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5208 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5209 &pd_10g);
5210
5211 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5212 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5213 params->port);
5214 return 1;
5215 }
5216 return 0;
5217 }
5218
5219 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5220 struct link_params *params,
5221 struct link_vars *vars,
5222 u32 gp_status)
5223 {
5224 struct bnx2x *bp = params->bp;
5225 u16 ld_pause; /* local driver */
5226 u16 lp_pause; /* link partner */
5227 u16 pause_result;
5228
5229 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5230
5231 /* resolve from gp_status in case of AN complete and not sgmii */
5232 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5233 vars->flow_ctrl = phy->req_flow_ctrl;
5234 else if (phy->req_line_speed != SPEED_AUTO_NEG)
5235 vars->flow_ctrl = params->req_fc_auto_adv;
5236 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5237 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5238 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5239 vars->flow_ctrl = params->req_fc_auto_adv;
5240 return;
5241 }
5242 if ((gp_status &
5243 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5244 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5245 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5246 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5247
5248 CL22_RD_OVER_CL45(bp, phy,
5249 MDIO_REG_BANK_CL73_IEEEB1,
5250 MDIO_CL73_IEEEB1_AN_ADV1,
5251 &ld_pause);
5252 CL22_RD_OVER_CL45(bp, phy,
5253 MDIO_REG_BANK_CL73_IEEEB1,
5254 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5255 &lp_pause);
5256 pause_result = (ld_pause &
5257 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5258 >> 8;
5259 pause_result |= (lp_pause &
5260 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5261 >> 10;
5262 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5263 pause_result);
5264 } else {
5265 CL22_RD_OVER_CL45(bp, phy,
5266 MDIO_REG_BANK_COMBO_IEEE0,
5267 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5268 &ld_pause);
5269 CL22_RD_OVER_CL45(bp, phy,
5270 MDIO_REG_BANK_COMBO_IEEE0,
5271 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5272 &lp_pause);
5273 pause_result = (ld_pause &
5274 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5275 pause_result |= (lp_pause &
5276 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5277 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5278 pause_result);
5279 }
5280 bnx2x_pause_resolve(vars, pause_result);
5281 }
5282 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5283 }
5284
5285 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5286 struct link_params *params)
5287 {
5288 struct bnx2x *bp = params->bp;
5289 u16 rx_status, ustat_val, cl37_fsm_received;
5290 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5291 /* Step 1: Make sure signal is detected */
5292 CL22_RD_OVER_CL45(bp, phy,
5293 MDIO_REG_BANK_RX0,
5294 MDIO_RX0_RX_STATUS,
5295 &rx_status);
5296 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5297 (MDIO_RX0_RX_STATUS_SIGDET)) {
5298 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5299 "rx_status(0x80b0) = 0x%x\n", rx_status);
5300 CL22_WR_OVER_CL45(bp, phy,
5301 MDIO_REG_BANK_CL73_IEEEB0,
5302 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5303 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5304 return;
5305 }
5306 /* Step 2: Check CL73 state machine */
5307 CL22_RD_OVER_CL45(bp, phy,
5308 MDIO_REG_BANK_CL73_USERB0,
5309 MDIO_CL73_USERB0_CL73_USTAT1,
5310 &ustat_val);
5311 if ((ustat_val &
5312 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5313 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5314 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5315 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5316 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5317 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5318 return;
5319 }
5320 /*
5321 * Step 3: Check CL37 Message Pages received to indicate LP
5322 * supports only CL37
5323 */
5324 CL22_RD_OVER_CL45(bp, phy,
5325 MDIO_REG_BANK_REMOTE_PHY,
5326 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5327 &cl37_fsm_received);
5328 if ((cl37_fsm_received &
5329 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5330 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5331 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5332 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5333 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5334 "misc_rx_status(0x8330) = 0x%x\n",
5335 cl37_fsm_received);
5336 return;
5337 }
5338 /*
5339 * The combined cl37/cl73 fsm state information indicating that
5340 * we are connected to a device which does not support cl73, but
5341 * does support cl37 BAM. In this case we disable cl73 and
5342 * restart cl37 auto-neg
5343 */
5344
5345 /* Disable CL73 */
5346 CL22_WR_OVER_CL45(bp, phy,
5347 MDIO_REG_BANK_CL73_IEEEB0,
5348 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5349 0);
5350 /* Restart CL37 autoneg */
5351 bnx2x_restart_autoneg(phy, params, 0);
5352 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5353 }
5354
5355 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5356 struct link_params *params,
5357 struct link_vars *vars,
5358 u32 gp_status)
5359 {
5360 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5361 vars->link_status |=
5362 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5363
5364 if (bnx2x_direct_parallel_detect_used(phy, params))
5365 vars->link_status |=
5366 LINK_STATUS_PARALLEL_DETECTION_USED;
5367 }
5368 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5369 struct link_params *params,
5370 struct link_vars *vars,
5371 u16 is_link_up,
5372 u16 speed_mask,
5373 u16 is_duplex)
5374 {
5375 struct bnx2x *bp = params->bp;
5376 if (phy->req_line_speed == SPEED_AUTO_NEG)
5377 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5378 if (is_link_up) {
5379 DP(NETIF_MSG_LINK, "phy link up\n");
5380
5381 vars->phy_link_up = 1;
5382 vars->link_status |= LINK_STATUS_LINK_UP;
5383
5384 switch (speed_mask) {
5385 case GP_STATUS_10M:
5386 vars->line_speed = SPEED_10;
5387 if (vars->duplex == DUPLEX_FULL)
5388 vars->link_status |= LINK_10TFD;
5389 else
5390 vars->link_status |= LINK_10THD;
5391 break;
5392
5393 case GP_STATUS_100M:
5394 vars->line_speed = SPEED_100;
5395 if (vars->duplex == DUPLEX_FULL)
5396 vars->link_status |= LINK_100TXFD;
5397 else
5398 vars->link_status |= LINK_100TXHD;
5399 break;
5400
5401 case GP_STATUS_1G:
5402 case GP_STATUS_1G_KX:
5403 vars->line_speed = SPEED_1000;
5404 if (vars->duplex == DUPLEX_FULL)
5405 vars->link_status |= LINK_1000TFD;
5406 else
5407 vars->link_status |= LINK_1000THD;
5408 break;
5409
5410 case GP_STATUS_2_5G:
5411 vars->line_speed = SPEED_2500;
5412 if (vars->duplex == DUPLEX_FULL)
5413 vars->link_status |= LINK_2500TFD;
5414 else
5415 vars->link_status |= LINK_2500THD;
5416 break;
5417
5418 case GP_STATUS_5G:
5419 case GP_STATUS_6G:
5420 DP(NETIF_MSG_LINK,
5421 "link speed unsupported gp_status 0x%x\n",
5422 speed_mask);
5423 return -EINVAL;
5424
5425 case GP_STATUS_10G_KX4:
5426 case GP_STATUS_10G_HIG:
5427 case GP_STATUS_10G_CX4:
5428 case GP_STATUS_10G_KR:
5429 case GP_STATUS_10G_SFI:
5430 case GP_STATUS_10G_XFI:
5431 vars->line_speed = SPEED_10000;
5432 vars->link_status |= LINK_10GTFD;
5433 break;
5434 case GP_STATUS_20G_DXGXS:
5435 vars->line_speed = SPEED_20000;
5436 vars->link_status |= LINK_20GTFD;
5437 break;
5438 default:
5439 DP(NETIF_MSG_LINK,
5440 "link speed unsupported gp_status 0x%x\n",
5441 speed_mask);
5442 return -EINVAL;
5443 }
5444 } else { /* link_down */
5445 DP(NETIF_MSG_LINK, "phy link down\n");
5446
5447 vars->phy_link_up = 0;
5448
5449 vars->duplex = DUPLEX_FULL;
5450 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5451 vars->mac_type = MAC_TYPE_NONE;
5452 }
5453 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5454 vars->phy_link_up, vars->line_speed);
5455 return 0;
5456 }
5457
5458 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5459 struct link_params *params,
5460 struct link_vars *vars)
5461 {
5462 struct bnx2x *bp = params->bp;
5463
5464 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5465 int rc = 0;
5466
5467 /* Read gp_status */
5468 CL22_RD_OVER_CL45(bp, phy,
5469 MDIO_REG_BANK_GP_STATUS,
5470 MDIO_GP_STATUS_TOP_AN_STATUS1,
5471 &gp_status);
5472 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5473 duplex = DUPLEX_FULL;
5474 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5475 link_up = 1;
5476 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5477 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5478 gp_status, link_up, speed_mask);
5479 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5480 duplex);
5481 if (rc == -EINVAL)
5482 return rc;
5483
5484 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5485 if (SINGLE_MEDIA_DIRECT(params)) {
5486 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5487 if (phy->req_line_speed == SPEED_AUTO_NEG)
5488 bnx2x_xgxs_an_resolve(phy, params, vars,
5489 gp_status);
5490 }
5491 } else { /* link_down */
5492 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5493 SINGLE_MEDIA_DIRECT(params)) {
5494 /* Check signal is detected */
5495 bnx2x_check_fallback_to_cl37(phy, params);
5496 }
5497 }
5498
5499 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5500 vars->duplex, vars->flow_ctrl, vars->link_status);
5501 return rc;
5502 }
5503
5504 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5505 struct link_params *params,
5506 struct link_vars *vars)
5507 {
5508 struct bnx2x *bp = params->bp;
5509 u8 lane;
5510 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5511 int rc = 0;
5512 lane = bnx2x_get_warpcore_lane(phy, params);
5513 /* Read gp_status */
5514 if (phy->req_line_speed > SPEED_10000) {
5515 u16 temp_link_up;
5516 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5517 1, &temp_link_up);
5518 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5519 1, &link_up);
5520 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5521 temp_link_up, link_up);
5522 link_up &= (1<<2);
5523 if (link_up)
5524 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5525 } else {
5526 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5527 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5528 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5529 /* Check for either KR or generic link up. */
5530 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5531 ((gp_status1 >> 12) & 0xf);
5532 link_up = gp_status1 & (1 << lane);
5533 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5534 u16 pd, gp_status4;
5535 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5536 /* Check Autoneg complete */
5537 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5538 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5539 &gp_status4);
5540 if (gp_status4 & ((1<<12)<<lane))
5541 vars->link_status |=
5542 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5543
5544 /* Check parallel detect used */
5545 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5546 MDIO_WC_REG_PAR_DET_10G_STATUS,
5547 &pd);
5548 if (pd & (1<<15))
5549 vars->link_status |=
5550 LINK_STATUS_PARALLEL_DETECTION_USED;
5551 }
5552 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5553 }
5554 }
5555
5556 if (lane < 2) {
5557 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5558 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5559 } else {
5560 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5561 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5562 }
5563 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5564
5565 if ((lane & 1) == 0)
5566 gp_speed <<= 8;
5567 gp_speed &= 0x3f00;
5568
5569
5570 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5571 duplex);
5572
5573 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5574 vars->duplex, vars->flow_ctrl, vars->link_status);
5575 return rc;
5576 }
5577 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5578 {
5579 struct bnx2x *bp = params->bp;
5580 struct bnx2x_phy *phy = &params->phy[INT_PHY];
5581 u16 lp_up2;
5582 u16 tx_driver;
5583 u16 bank;
5584
5585 /* read precomp */
5586 CL22_RD_OVER_CL45(bp, phy,
5587 MDIO_REG_BANK_OVER_1G,
5588 MDIO_OVER_1G_LP_UP2, &lp_up2);
5589
5590 /* bits [10:7] at lp_up2, positioned at [15:12] */
5591 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5592 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5593 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5594
5595 if (lp_up2 == 0)
5596 return;
5597
5598 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5599 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5600 CL22_RD_OVER_CL45(bp, phy,
5601 bank,
5602 MDIO_TX0_TX_DRIVER, &tx_driver);
5603
5604 /* replace tx_driver bits [15:12] */
5605 if (lp_up2 !=
5606 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5607 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5608 tx_driver |= lp_up2;
5609 CL22_WR_OVER_CL45(bp, phy,
5610 bank,
5611 MDIO_TX0_TX_DRIVER, tx_driver);
5612 }
5613 }
5614 }
5615
5616 static int bnx2x_emac_program(struct link_params *params,
5617 struct link_vars *vars)
5618 {
5619 struct bnx2x *bp = params->bp;
5620 u8 port = params->port;
5621 u16 mode = 0;
5622
5623 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5624 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5625 EMAC_REG_EMAC_MODE,
5626 (EMAC_MODE_25G_MODE |
5627 EMAC_MODE_PORT_MII_10M |
5628 EMAC_MODE_HALF_DUPLEX));
5629 switch (vars->line_speed) {
5630 case SPEED_10:
5631 mode |= EMAC_MODE_PORT_MII_10M;
5632 break;
5633
5634 case SPEED_100:
5635 mode |= EMAC_MODE_PORT_MII;
5636 break;
5637
5638 case SPEED_1000:
5639 mode |= EMAC_MODE_PORT_GMII;
5640 break;
5641
5642 case SPEED_2500:
5643 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5644 break;
5645
5646 default:
5647 /* 10G not valid for EMAC */
5648 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5649 vars->line_speed);
5650 return -EINVAL;
5651 }
5652
5653 if (vars->duplex == DUPLEX_HALF)
5654 mode |= EMAC_MODE_HALF_DUPLEX;
5655 bnx2x_bits_en(bp,
5656 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5657 mode);
5658
5659 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5660 return 0;
5661 }
5662
5663 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5664 struct link_params *params)
5665 {
5666
5667 u16 bank, i = 0;
5668 struct bnx2x *bp = params->bp;
5669
5670 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5671 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5672 CL22_WR_OVER_CL45(bp, phy,
5673 bank,
5674 MDIO_RX0_RX_EQ_BOOST,
5675 phy->rx_preemphasis[i]);
5676 }
5677
5678 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5679 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5680 CL22_WR_OVER_CL45(bp, phy,
5681 bank,
5682 MDIO_TX0_TX_DRIVER,
5683 phy->tx_preemphasis[i]);
5684 }
5685 }
5686
5687 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5688 struct link_params *params,
5689 struct link_vars *vars)
5690 {
5691 struct bnx2x *bp = params->bp;
5692 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5693 (params->loopback_mode == LOOPBACK_XGXS));
5694 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5695 if (SINGLE_MEDIA_DIRECT(params) &&
5696 (params->feature_config_flags &
5697 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5698 bnx2x_set_preemphasis(phy, params);
5699
5700 /* forced speed requested? */
5701 if (vars->line_speed != SPEED_AUTO_NEG ||
5702 (SINGLE_MEDIA_DIRECT(params) &&
5703 params->loopback_mode == LOOPBACK_EXT)) {
5704 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5705
5706 /* disable autoneg */
5707 bnx2x_set_autoneg(phy, params, vars, 0);
5708
5709 /* program speed and duplex */
5710 bnx2x_program_serdes(phy, params, vars);
5711
5712 } else { /* AN_mode */
5713 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5714
5715 /* AN enabled */
5716 bnx2x_set_brcm_cl37_advertisement(phy, params);
5717
5718 /* program duplex & pause advertisement (for aneg) */
5719 bnx2x_set_ieee_aneg_advertisement(phy, params,
5720 vars->ieee_fc);
5721
5722 /* enable autoneg */
5723 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5724
5725 /* enable and restart AN */
5726 bnx2x_restart_autoneg(phy, params, enable_cl73);
5727 }
5728
5729 } else { /* SGMII mode */
5730 DP(NETIF_MSG_LINK, "SGMII\n");
5731
5732 bnx2x_initialize_sgmii_process(phy, params, vars);
5733 }
5734 }
5735
5736 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5737 struct link_params *params,
5738 struct link_vars *vars)
5739 {
5740 int rc;
5741 vars->phy_flags |= PHY_XGXS_FLAG;
5742 if ((phy->req_line_speed &&
5743 ((phy->req_line_speed == SPEED_100) ||
5744 (phy->req_line_speed == SPEED_10))) ||
5745 (!phy->req_line_speed &&
5746 (phy->speed_cap_mask >=
5747 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5748 (phy->speed_cap_mask <
5749 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5750 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5751 vars->phy_flags |= PHY_SGMII_FLAG;
5752 else
5753 vars->phy_flags &= ~PHY_SGMII_FLAG;
5754
5755 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5756 bnx2x_set_aer_mmd(params, phy);
5757 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5758 bnx2x_set_master_ln(params, phy);
5759
5760 rc = bnx2x_reset_unicore(params, phy, 0);
5761 /* reset the SerDes and wait for reset bit return low */
5762 if (rc != 0)
5763 return rc;
5764
5765 bnx2x_set_aer_mmd(params, phy);
5766 /* setting the masterLn_def again after the reset */
5767 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5768 bnx2x_set_master_ln(params, phy);
5769 bnx2x_set_swap_lanes(params, phy);
5770 }
5771
5772 return rc;
5773 }
5774
5775 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5776 struct bnx2x_phy *phy,
5777 struct link_params *params)
5778 {
5779 u16 cnt, ctrl;
5780 /* Wait for soft reset to get cleared up to 1 sec */
5781 for (cnt = 0; cnt < 1000; cnt++) {
5782 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5783 bnx2x_cl22_read(bp, phy,
5784 MDIO_PMA_REG_CTRL, &ctrl);
5785 else
5786 bnx2x_cl45_read(bp, phy,
5787 MDIO_PMA_DEVAD,
5788 MDIO_PMA_REG_CTRL, &ctrl);
5789 if (!(ctrl & (1<<15)))
5790 break;
5791 msleep(1);
5792 }
5793
5794 if (cnt == 1000)
5795 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5796 " Port %d\n",
5797 params->port);
5798 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5799 return cnt;
5800 }
5801
5802 static void bnx2x_link_int_enable(struct link_params *params)
5803 {
5804 u8 port = params->port;
5805 u32 mask;
5806 struct bnx2x *bp = params->bp;
5807
5808 /* Setting the status to report on link up for either XGXS or SerDes */
5809 if (CHIP_IS_E3(bp)) {
5810 mask = NIG_MASK_XGXS0_LINK_STATUS;
5811 if (!(SINGLE_MEDIA_DIRECT(params)))
5812 mask |= NIG_MASK_MI_INT;
5813 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5814 mask = (NIG_MASK_XGXS0_LINK10G |
5815 NIG_MASK_XGXS0_LINK_STATUS);
5816 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5817 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5818 params->phy[INT_PHY].type !=
5819 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5820 mask |= NIG_MASK_MI_INT;
5821 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5822 }
5823
5824 } else { /* SerDes */
5825 mask = NIG_MASK_SERDES0_LINK_STATUS;
5826 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5827 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5828 params->phy[INT_PHY].type !=
5829 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5830 mask |= NIG_MASK_MI_INT;
5831 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5832 }
5833 }
5834 bnx2x_bits_en(bp,
5835 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5836 mask);
5837
5838 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5839 (params->switch_cfg == SWITCH_CFG_10G),
5840 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5841 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5842 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5843 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5844 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5845 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5846 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5847 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5848 }
5849
5850 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5851 u8 exp_mi_int)
5852 {
5853 u32 latch_status = 0;
5854
5855 /*
5856 * Disable the MI INT ( external phy int ) by writing 1 to the
5857 * status register. Link down indication is high-active-signal,
5858 * so in this case we need to write the status to clear the XOR
5859 */
5860 /* Read Latched signals */
5861 latch_status = REG_RD(bp,
5862 NIG_REG_LATCH_STATUS_0 + port*8);
5863 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5864 /* Handle only those with latched-signal=up.*/
5865 if (exp_mi_int)
5866 bnx2x_bits_en(bp,
5867 NIG_REG_STATUS_INTERRUPT_PORT0
5868 + port*4,
5869 NIG_STATUS_EMAC0_MI_INT);
5870 else
5871 bnx2x_bits_dis(bp,
5872 NIG_REG_STATUS_INTERRUPT_PORT0
5873 + port*4,
5874 NIG_STATUS_EMAC0_MI_INT);
5875
5876 if (latch_status & 1) {
5877
5878 /* For all latched-signal=up : Re-Arm Latch signals */
5879 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5880 (latch_status & 0xfffe) | (latch_status & 1));
5881 }
5882 /* For all latched-signal=up,Write original_signal to status */
5883 }
5884
5885 static void bnx2x_link_int_ack(struct link_params *params,
5886 struct link_vars *vars, u8 is_10g_plus)
5887 {
5888 struct bnx2x *bp = params->bp;
5889 u8 port = params->port;
5890 u32 mask;
5891 /*
5892 * First reset all status we assume only one line will be
5893 * change at a time
5894 */
5895 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5896 (NIG_STATUS_XGXS0_LINK10G |
5897 NIG_STATUS_XGXS0_LINK_STATUS |
5898 NIG_STATUS_SERDES0_LINK_STATUS));
5899 if (vars->phy_link_up) {
5900 if (USES_WARPCORE(bp))
5901 mask = NIG_STATUS_XGXS0_LINK_STATUS;
5902 else {
5903 if (is_10g_plus)
5904 mask = NIG_STATUS_XGXS0_LINK10G;
5905 else if (params->switch_cfg == SWITCH_CFG_10G) {
5906 /*
5907 * Disable the link interrupt by writing 1 to
5908 * the relevant lane in the status register
5909 */
5910 u32 ser_lane =
5911 ((params->lane_config &
5912 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5913 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5914 mask = ((1 << ser_lane) <<
5915 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5916 } else
5917 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5918 }
5919 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5920 mask);
5921 bnx2x_bits_en(bp,
5922 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5923 mask);
5924 }
5925 }
5926
5927 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5928 {
5929 u8 *str_ptr = str;
5930 u32 mask = 0xf0000000;
5931 u8 shift = 8*4;
5932 u8 digit;
5933 u8 remove_leading_zeros = 1;
5934 if (*len < 10) {
5935 /* Need more than 10chars for this format */
5936 *str_ptr = '\0';
5937 (*len)--;
5938 return -EINVAL;
5939 }
5940 while (shift > 0) {
5941
5942 shift -= 4;
5943 digit = ((num & mask) >> shift);
5944 if (digit == 0 && remove_leading_zeros) {
5945 mask = mask >> 4;
5946 continue;
5947 } else if (digit < 0xa)
5948 *str_ptr = digit + '0';
5949 else
5950 *str_ptr = digit - 0xa + 'a';
5951 remove_leading_zeros = 0;
5952 str_ptr++;
5953 (*len)--;
5954 mask = mask >> 4;
5955 if (shift == 4*4) {
5956 *str_ptr = '.';
5957 str_ptr++;
5958 (*len)--;
5959 remove_leading_zeros = 1;
5960 }
5961 }
5962 return 0;
5963 }
5964
5965
5966 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5967 {
5968 str[0] = '\0';
5969 (*len)--;
5970 return 0;
5971 }
5972
5973 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5974 u8 *version, u16 len)
5975 {
5976 struct bnx2x *bp;
5977 u32 spirom_ver = 0;
5978 int status = 0;
5979 u8 *ver_p = version;
5980 u16 remain_len = len;
5981 if (version == NULL || params == NULL)
5982 return -EINVAL;
5983 bp = params->bp;
5984
5985 /* Extract first external phy*/
5986 version[0] = '\0';
5987 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5988
5989 if (params->phy[EXT_PHY1].format_fw_ver) {
5990 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5991 ver_p,
5992 &remain_len);
5993 ver_p += (len - remain_len);
5994 }
5995 if ((params->num_phys == MAX_PHYS) &&
5996 (params->phy[EXT_PHY2].ver_addr != 0)) {
5997 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5998 if (params->phy[EXT_PHY2].format_fw_ver) {
5999 *ver_p = '/';
6000 ver_p++;
6001 remain_len--;
6002 status |= params->phy[EXT_PHY2].format_fw_ver(
6003 spirom_ver,
6004 ver_p,
6005 &remain_len);
6006 ver_p = version + (len - remain_len);
6007 }
6008 }
6009 *ver_p = '\0';
6010 return status;
6011 }
6012
6013 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6014 struct link_params *params)
6015 {
6016 u8 port = params->port;
6017 struct bnx2x *bp = params->bp;
6018
6019 if (phy->req_line_speed != SPEED_1000) {
6020 u32 md_devad = 0;
6021
6022 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6023
6024 if (!CHIP_IS_E3(bp)) {
6025 /* change the uni_phy_addr in the nig */
6026 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6027 port*0x18));
6028
6029 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6030 0x5);
6031 }
6032
6033 bnx2x_cl45_write(bp, phy,
6034 5,
6035 (MDIO_REG_BANK_AER_BLOCK +
6036 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6037 0x2800);
6038
6039 bnx2x_cl45_write(bp, phy,
6040 5,
6041 (MDIO_REG_BANK_CL73_IEEEB0 +
6042 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6043 0x6041);
6044 msleep(200);
6045 /* set aer mmd back */
6046 bnx2x_set_aer_mmd(params, phy);
6047
6048 if (!CHIP_IS_E3(bp)) {
6049 /* and md_devad */
6050 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6051 md_devad);
6052 }
6053 } else {
6054 u16 mii_ctrl;
6055 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6056 bnx2x_cl45_read(bp, phy, 5,
6057 (MDIO_REG_BANK_COMBO_IEEE0 +
6058 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6059 &mii_ctrl);
6060 bnx2x_cl45_write(bp, phy, 5,
6061 (MDIO_REG_BANK_COMBO_IEEE0 +
6062 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6063 mii_ctrl |
6064 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6065 }
6066 }
6067
6068 int bnx2x_set_led(struct link_params *params,
6069 struct link_vars *vars, u8 mode, u32 speed)
6070 {
6071 u8 port = params->port;
6072 u16 hw_led_mode = params->hw_led_mode;
6073 int rc = 0;
6074 u8 phy_idx;
6075 u32 tmp;
6076 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6077 struct bnx2x *bp = params->bp;
6078 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6079 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6080 speed, hw_led_mode);
6081 /* In case */
6082 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6083 if (params->phy[phy_idx].set_link_led) {
6084 params->phy[phy_idx].set_link_led(
6085 &params->phy[phy_idx], params, mode);
6086 }
6087 }
6088
6089 switch (mode) {
6090 case LED_MODE_FRONT_PANEL_OFF:
6091 case LED_MODE_OFF:
6092 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6093 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6094 SHARED_HW_CFG_LED_MAC1);
6095
6096 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6097 if (params->phy[EXT_PHY1].type ==
6098 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6099 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp & 0xfff1);
6100 else {
6101 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6102 (tmp | EMAC_LED_OVERRIDE));
6103 }
6104 break;
6105
6106 case LED_MODE_OPER:
6107 /*
6108 * For all other phys, OPER mode is same as ON, so in case
6109 * link is down, do nothing
6110 */
6111 if (!vars->link_up)
6112 break;
6113 case LED_MODE_ON:
6114 if (((params->phy[EXT_PHY1].type ==
6115 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6116 (params->phy[EXT_PHY1].type ==
6117 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6118 CHIP_IS_E2(bp) && params->num_phys == 2) {
6119 /*
6120 * This is a work-around for E2+8727 Configurations
6121 */
6122 if (mode == LED_MODE_ON ||
6123 speed == SPEED_10000){
6124 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6125 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6126
6127 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6128 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6129 (tmp | EMAC_LED_OVERRIDE));
6130 /*
6131 * return here without enabling traffic
6132 * LED blink and setting rate in ON mode.
6133 * In oper mode, enabling LED blink
6134 * and setting rate is needed.
6135 */
6136 if (mode == LED_MODE_ON)
6137 return rc;
6138 }
6139 } else if (SINGLE_MEDIA_DIRECT(params)) {
6140 /*
6141 * This is a work-around for HW issue found when link
6142 * is up in CL73
6143 */
6144 if ((!CHIP_IS_E3(bp)) ||
6145 (CHIP_IS_E3(bp) &&
6146 mode == LED_MODE_ON))
6147 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6148
6149 if (CHIP_IS_E1x(bp) ||
6150 CHIP_IS_E2(bp) ||
6151 (mode == LED_MODE_ON))
6152 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6153 else
6154 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6155 hw_led_mode);
6156 } else if ((params->phy[EXT_PHY1].type ==
6157 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6158 (mode != LED_MODE_OPER)) {
6159 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6160 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6161 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 0x3);
6162 } else
6163 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6164 hw_led_mode);
6165
6166 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6167 /* Set blinking rate to ~15.9Hz */
6168 if (CHIP_IS_E3(bp))
6169 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6170 LED_BLINK_RATE_VAL_E3);
6171 else
6172 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6173 LED_BLINK_RATE_VAL_E1X_E2);
6174 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6175 port*4, 1);
6176 if ((params->phy[EXT_PHY1].type !=
6177 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6178 (mode != LED_MODE_OPER)) {
6179 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6180 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6181 (tmp & (~EMAC_LED_OVERRIDE)));
6182 }
6183
6184 if (CHIP_IS_E1(bp) &&
6185 ((speed == SPEED_2500) ||
6186 (speed == SPEED_1000) ||
6187 (speed == SPEED_100) ||
6188 (speed == SPEED_10))) {
6189 /*
6190 * On Everest 1 Ax chip versions for speeds less than
6191 * 10G LED scheme is different
6192 */
6193 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6194 + port*4, 1);
6195 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6196 port*4, 0);
6197 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6198 port*4, 1);
6199 }
6200 break;
6201
6202 default:
6203 rc = -EINVAL;
6204 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6205 mode);
6206 break;
6207 }
6208 return rc;
6209
6210 }
6211
6212 /*
6213 * This function comes to reflect the actual link state read DIRECTLY from the
6214 * HW
6215 */
6216 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6217 u8 is_serdes)
6218 {
6219 struct bnx2x *bp = params->bp;
6220 u16 gp_status = 0, phy_index = 0;
6221 u8 ext_phy_link_up = 0, serdes_phy_type;
6222 struct link_vars temp_vars;
6223 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6224
6225 if (CHIP_IS_E3(bp)) {
6226 u16 link_up;
6227 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6228 > SPEED_10000) {
6229 /* Check 20G link */
6230 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6231 1, &link_up);
6232 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6233 1, &link_up);
6234 link_up &= (1<<2);
6235 } else {
6236 /* Check 10G link and below*/
6237 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6238 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6239 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6240 &gp_status);
6241 gp_status = ((gp_status >> 8) & 0xf) |
6242 ((gp_status >> 12) & 0xf);
6243 link_up = gp_status & (1 << lane);
6244 }
6245 if (!link_up)
6246 return -ESRCH;
6247 } else {
6248 CL22_RD_OVER_CL45(bp, int_phy,
6249 MDIO_REG_BANK_GP_STATUS,
6250 MDIO_GP_STATUS_TOP_AN_STATUS1,
6251 &gp_status);
6252 /* link is up only if both local phy and external phy are up */
6253 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6254 return -ESRCH;
6255 }
6256 /* In XGXS loopback mode, do not check external PHY */
6257 if (params->loopback_mode == LOOPBACK_XGXS)
6258 return 0;
6259
6260 switch (params->num_phys) {
6261 case 1:
6262 /* No external PHY */
6263 return 0;
6264 case 2:
6265 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6266 &params->phy[EXT_PHY1],
6267 params, &temp_vars);
6268 break;
6269 case 3: /* Dual Media */
6270 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6271 phy_index++) {
6272 serdes_phy_type = ((params->phy[phy_index].media_type ==
6273 ETH_PHY_SFP_FIBER) ||
6274 (params->phy[phy_index].media_type ==
6275 ETH_PHY_XFP_FIBER) ||
6276 (params->phy[phy_index].media_type ==
6277 ETH_PHY_DA_TWINAX));
6278
6279 if (is_serdes != serdes_phy_type)
6280 continue;
6281 if (params->phy[phy_index].read_status) {
6282 ext_phy_link_up |=
6283 params->phy[phy_index].read_status(
6284 &params->phy[phy_index],
6285 params, &temp_vars);
6286 }
6287 }
6288 break;
6289 }
6290 if (ext_phy_link_up)
6291 return 0;
6292 return -ESRCH;
6293 }
6294
6295 static int bnx2x_link_initialize(struct link_params *params,
6296 struct link_vars *vars)
6297 {
6298 int rc = 0;
6299 u8 phy_index, non_ext_phy;
6300 struct bnx2x *bp = params->bp;
6301 /*
6302 * In case of external phy existence, the line speed would be the
6303 * line speed linked up by the external phy. In case it is direct
6304 * only, then the line_speed during initialization will be
6305 * equal to the req_line_speed
6306 */
6307 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6308
6309 /*
6310 * Initialize the internal phy in case this is a direct board
6311 * (no external phys), or this board has external phy which requires
6312 * to first.
6313 */
6314 if (!USES_WARPCORE(bp))
6315 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6316 /* init ext phy and enable link state int */
6317 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6318 (params->loopback_mode == LOOPBACK_XGXS));
6319
6320 if (non_ext_phy ||
6321 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6322 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6323 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6324 if (vars->line_speed == SPEED_AUTO_NEG &&
6325 (CHIP_IS_E1x(bp) ||
6326 CHIP_IS_E2(bp)))
6327 bnx2x_set_parallel_detection(phy, params);
6328 if (params->phy[INT_PHY].config_init)
6329 params->phy[INT_PHY].config_init(phy,
6330 params,
6331 vars);
6332 }
6333
6334 /* Init external phy*/
6335 if (non_ext_phy) {
6336 if (params->phy[INT_PHY].supported &
6337 SUPPORTED_FIBRE)
6338 vars->link_status |= LINK_STATUS_SERDES_LINK;
6339 } else {
6340 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6341 phy_index++) {
6342 /*
6343 * No need to initialize second phy in case of first
6344 * phy only selection. In case of second phy, we do
6345 * need to initialize the first phy, since they are
6346 * connected.
6347 */
6348 if (params->phy[phy_index].supported &
6349 SUPPORTED_FIBRE)
6350 vars->link_status |= LINK_STATUS_SERDES_LINK;
6351
6352 if (phy_index == EXT_PHY2 &&
6353 (bnx2x_phy_selection(params) ==
6354 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6355 DP(NETIF_MSG_LINK,
6356 "Not initializing second phy\n");
6357 continue;
6358 }
6359 params->phy[phy_index].config_init(
6360 &params->phy[phy_index],
6361 params, vars);
6362 }
6363 }
6364 /* Reset the interrupt indication after phy was initialized */
6365 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6366 params->port*4,
6367 (NIG_STATUS_XGXS0_LINK10G |
6368 NIG_STATUS_XGXS0_LINK_STATUS |
6369 NIG_STATUS_SERDES0_LINK_STATUS |
6370 NIG_MASK_MI_INT));
6371 bnx2x_update_mng(params, vars->link_status);
6372 return rc;
6373 }
6374
6375 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6376 struct link_params *params)
6377 {
6378 /* reset the SerDes/XGXS */
6379 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6380 (0x1ff << (params->port*16)));
6381 }
6382
6383 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6384 struct link_params *params)
6385 {
6386 struct bnx2x *bp = params->bp;
6387 u8 gpio_port;
6388 /* HW reset */
6389 if (CHIP_IS_E2(bp))
6390 gpio_port = BP_PATH(bp);
6391 else
6392 gpio_port = params->port;
6393 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6394 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6395 gpio_port);
6396 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6397 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6398 gpio_port);
6399 DP(NETIF_MSG_LINK, "reset external PHY\n");
6400 }
6401
6402 static int bnx2x_update_link_down(struct link_params *params,
6403 struct link_vars *vars)
6404 {
6405 struct bnx2x *bp = params->bp;
6406 u8 port = params->port;
6407
6408 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6409 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6410 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6411 /* indicate no mac active */
6412 vars->mac_type = MAC_TYPE_NONE;
6413
6414 /* update shared memory */
6415 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6416 LINK_STATUS_LINK_UP |
6417 LINK_STATUS_PHYSICAL_LINK_FLAG |
6418 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6419 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6420 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6421 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6422 vars->line_speed = 0;
6423 bnx2x_update_mng(params, vars->link_status);
6424
6425 /* activate nig drain */
6426 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6427
6428 /* disable emac */
6429 if (!CHIP_IS_E3(bp))
6430 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6431
6432 msleep(10);
6433 /* reset BigMac/Xmac */
6434 if (CHIP_IS_E1x(bp) ||
6435 CHIP_IS_E2(bp)) {
6436 bnx2x_bmac_rx_disable(bp, params->port);
6437 REG_WR(bp, GRCBASE_MISC +
6438 MISC_REGISTERS_RESET_REG_2_CLEAR,
6439 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6440 }
6441 if (CHIP_IS_E3(bp)) {
6442 bnx2x_xmac_disable(params);
6443 bnx2x_umac_disable(params);
6444 }
6445
6446 return 0;
6447 }
6448
6449 static int bnx2x_update_link_up(struct link_params *params,
6450 struct link_vars *vars,
6451 u8 link_10g)
6452 {
6453 struct bnx2x *bp = params->bp;
6454 u8 port = params->port;
6455 int rc = 0;
6456
6457 vars->link_status |= (LINK_STATUS_LINK_UP |
6458 LINK_STATUS_PHYSICAL_LINK_FLAG);
6459 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6460
6461 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6462 vars->link_status |=
6463 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6464
6465 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6466 vars->link_status |=
6467 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6468 if (USES_WARPCORE(bp)) {
6469 if (link_10g) {
6470 if (bnx2x_xmac_enable(params, vars, 0) ==
6471 -ESRCH) {
6472 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6473 vars->link_up = 0;
6474 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6475 vars->link_status &= ~LINK_STATUS_LINK_UP;
6476 }
6477 } else
6478 bnx2x_umac_enable(params, vars, 0);
6479 bnx2x_set_led(params, vars,
6480 LED_MODE_OPER, vars->line_speed);
6481 }
6482 if ((CHIP_IS_E1x(bp) ||
6483 CHIP_IS_E2(bp))) {
6484 if (link_10g) {
6485 if (bnx2x_bmac_enable(params, vars, 0) ==
6486 -ESRCH) {
6487 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6488 vars->link_up = 0;
6489 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6490 vars->link_status &= ~LINK_STATUS_LINK_UP;
6491 }
6492
6493 bnx2x_set_led(params, vars,
6494 LED_MODE_OPER, SPEED_10000);
6495 } else {
6496 rc = bnx2x_emac_program(params, vars);
6497 bnx2x_emac_enable(params, vars, 0);
6498
6499 /* AN complete? */
6500 if ((vars->link_status &
6501 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6502 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6503 SINGLE_MEDIA_DIRECT(params))
6504 bnx2x_set_gmii_tx_driver(params);
6505 }
6506 }
6507
6508 /* PBF - link up */
6509 if (CHIP_IS_E1x(bp))
6510 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6511 vars->line_speed);
6512
6513 /* disable drain */
6514 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6515
6516 /* update shared memory */
6517 bnx2x_update_mng(params, vars->link_status);
6518 msleep(20);
6519 return rc;
6520 }
6521 /*
6522 * The bnx2x_link_update function should be called upon link
6523 * interrupt.
6524 * Link is considered up as follows:
6525 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6526 * to be up
6527 * - SINGLE_MEDIA - The link between the 577xx and the external
6528 * phy (XGXS) need to up as well as the external link of the
6529 * phy (PHY_EXT1)
6530 * - DUAL_MEDIA - The link between the 577xx and the first
6531 * external phy needs to be up, and at least one of the 2
6532 * external phy link must be up.
6533 */
6534 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6535 {
6536 struct bnx2x *bp = params->bp;
6537 struct link_vars phy_vars[MAX_PHYS];
6538 u8 port = params->port;
6539 u8 link_10g_plus, phy_index;
6540 u8 ext_phy_link_up = 0, cur_link_up;
6541 int rc = 0;
6542 u8 is_mi_int = 0;
6543 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6544 u8 active_external_phy = INT_PHY;
6545 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6546 for (phy_index = INT_PHY; phy_index < params->num_phys;
6547 phy_index++) {
6548 phy_vars[phy_index].flow_ctrl = 0;
6549 phy_vars[phy_index].link_status = 0;
6550 phy_vars[phy_index].line_speed = 0;
6551 phy_vars[phy_index].duplex = DUPLEX_FULL;
6552 phy_vars[phy_index].phy_link_up = 0;
6553 phy_vars[phy_index].link_up = 0;
6554 phy_vars[phy_index].fault_detected = 0;
6555 }
6556
6557 if (USES_WARPCORE(bp))
6558 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6559
6560 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6561 port, (vars->phy_flags & PHY_XGXS_FLAG),
6562 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6563
6564 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6565 port*0x18) > 0);
6566 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6567 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6568 is_mi_int,
6569 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6570
6571 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6572 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6573 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6574
6575 /* disable emac */
6576 if (!CHIP_IS_E3(bp))
6577 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6578
6579 /*
6580 * Step 1:
6581 * Check external link change only for external phys, and apply
6582 * priority selection between them in case the link on both phys
6583 * is up. Note that instead of the common vars, a temporary
6584 * vars argument is used since each phy may have different link/
6585 * speed/duplex result
6586 */
6587 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6588 phy_index++) {
6589 struct bnx2x_phy *phy = &params->phy[phy_index];
6590 if (!phy->read_status)
6591 continue;
6592 /* Read link status and params of this ext phy */
6593 cur_link_up = phy->read_status(phy, params,
6594 &phy_vars[phy_index]);
6595 if (cur_link_up) {
6596 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6597 phy_index);
6598 } else {
6599 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6600 phy_index);
6601 continue;
6602 }
6603
6604 if (!ext_phy_link_up) {
6605 ext_phy_link_up = 1;
6606 active_external_phy = phy_index;
6607 } else {
6608 switch (bnx2x_phy_selection(params)) {
6609 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6610 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6611 /*
6612 * In this option, the first PHY makes sure to pass the
6613 * traffic through itself only.
6614 * Its not clear how to reset the link on the second phy
6615 */
6616 active_external_phy = EXT_PHY1;
6617 break;
6618 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6619 /*
6620 * In this option, the first PHY makes sure to pass the
6621 * traffic through the second PHY.
6622 */
6623 active_external_phy = EXT_PHY2;
6624 break;
6625 default:
6626 /*
6627 * Link indication on both PHYs with the following cases
6628 * is invalid:
6629 * - FIRST_PHY means that second phy wasn't initialized,
6630 * hence its link is expected to be down
6631 * - SECOND_PHY means that first phy should not be able
6632 * to link up by itself (using configuration)
6633 * - DEFAULT should be overriden during initialiazation
6634 */
6635 DP(NETIF_MSG_LINK, "Invalid link indication"
6636 "mpc=0x%x. DISABLING LINK !!!\n",
6637 params->multi_phy_config);
6638 ext_phy_link_up = 0;
6639 break;
6640 }
6641 }
6642 }
6643 prev_line_speed = vars->line_speed;
6644 /*
6645 * Step 2:
6646 * Read the status of the internal phy. In case of
6647 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6648 * otherwise this is the link between the 577xx and the first
6649 * external phy
6650 */
6651 if (params->phy[INT_PHY].read_status)
6652 params->phy[INT_PHY].read_status(
6653 &params->phy[INT_PHY],
6654 params, vars);
6655 /*
6656 * The INT_PHY flow control reside in the vars. This include the
6657 * case where the speed or flow control are not set to AUTO.
6658 * Otherwise, the active external phy flow control result is set
6659 * to the vars. The ext_phy_line_speed is needed to check if the
6660 * speed is different between the internal phy and external phy.
6661 * This case may be result of intermediate link speed change.
6662 */
6663 if (active_external_phy > INT_PHY) {
6664 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6665 /*
6666 * Link speed is taken from the XGXS. AN and FC result from
6667 * the external phy.
6668 */
6669 vars->link_status |= phy_vars[active_external_phy].link_status;
6670
6671 /*
6672 * if active_external_phy is first PHY and link is up - disable
6673 * disable TX on second external PHY
6674 */
6675 if (active_external_phy == EXT_PHY1) {
6676 if (params->phy[EXT_PHY2].phy_specific_func) {
6677 DP(NETIF_MSG_LINK,
6678 "Disabling TX on EXT_PHY2\n");
6679 params->phy[EXT_PHY2].phy_specific_func(
6680 &params->phy[EXT_PHY2],
6681 params, DISABLE_TX);
6682 }
6683 }
6684
6685 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6686 vars->duplex = phy_vars[active_external_phy].duplex;
6687 if (params->phy[active_external_phy].supported &
6688 SUPPORTED_FIBRE)
6689 vars->link_status |= LINK_STATUS_SERDES_LINK;
6690 else
6691 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6692 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6693 active_external_phy);
6694 }
6695
6696 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6697 phy_index++) {
6698 if (params->phy[phy_index].flags &
6699 FLAGS_REARM_LATCH_SIGNAL) {
6700 bnx2x_rearm_latch_signal(bp, port,
6701 phy_index ==
6702 active_external_phy);
6703 break;
6704 }
6705 }
6706 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6707 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6708 vars->link_status, ext_phy_line_speed);
6709 /*
6710 * Upon link speed change set the NIG into drain mode. Comes to
6711 * deals with possible FIFO glitch due to clk change when speed
6712 * is decreased without link down indicator
6713 */
6714
6715 if (vars->phy_link_up) {
6716 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6717 (ext_phy_line_speed != vars->line_speed)) {
6718 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6719 " different than the external"
6720 " link speed %d\n", vars->line_speed,
6721 ext_phy_line_speed);
6722 vars->phy_link_up = 0;
6723 } else if (prev_line_speed != vars->line_speed) {
6724 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6725 0);
6726 msleep(1);
6727 }
6728 }
6729
6730 /* anything 10 and over uses the bmac */
6731 link_10g_plus = (vars->line_speed >= SPEED_10000);
6732
6733 bnx2x_link_int_ack(params, vars, link_10g_plus);
6734
6735 /*
6736 * In case external phy link is up, and internal link is down
6737 * (not initialized yet probably after link initialization, it
6738 * needs to be initialized.
6739 * Note that after link down-up as result of cable plug, the xgxs
6740 * link would probably become up again without the need
6741 * initialize it
6742 */
6743 if (!(SINGLE_MEDIA_DIRECT(params))) {
6744 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6745 " init_preceding = %d\n", ext_phy_link_up,
6746 vars->phy_link_up,
6747 params->phy[EXT_PHY1].flags &
6748 FLAGS_INIT_XGXS_FIRST);
6749 if (!(params->phy[EXT_PHY1].flags &
6750 FLAGS_INIT_XGXS_FIRST)
6751 && ext_phy_link_up && !vars->phy_link_up) {
6752 vars->line_speed = ext_phy_line_speed;
6753 if (vars->line_speed < SPEED_1000)
6754 vars->phy_flags |= PHY_SGMII_FLAG;
6755 else
6756 vars->phy_flags &= ~PHY_SGMII_FLAG;
6757
6758 if (params->phy[INT_PHY].config_init)
6759 params->phy[INT_PHY].config_init(
6760 &params->phy[INT_PHY], params,
6761 vars);
6762 }
6763 }
6764 /*
6765 * Link is up only if both local phy and external phy (in case of
6766 * non-direct board) are up and no fault detected on active PHY.
6767 */
6768 vars->link_up = (vars->phy_link_up &&
6769 (ext_phy_link_up ||
6770 SINGLE_MEDIA_DIRECT(params)) &&
6771 (phy_vars[active_external_phy].fault_detected == 0));
6772
6773 if (vars->link_up)
6774 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6775 else
6776 rc = bnx2x_update_link_down(params, vars);
6777
6778 return rc;
6779 }
6780
6781 /*****************************************************************************/
6782 /* External Phy section */
6783 /*****************************************************************************/
6784 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6785 {
6786 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6787 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6788 msleep(1);
6789 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6790 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6791 }
6792
6793 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6794 u32 spirom_ver, u32 ver_addr)
6795 {
6796 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6797 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6798
6799 if (ver_addr)
6800 REG_WR(bp, ver_addr, spirom_ver);
6801 }
6802
6803 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6804 struct bnx2x_phy *phy,
6805 u8 port)
6806 {
6807 u16 fw_ver1, fw_ver2;
6808
6809 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6810 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6811 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6812 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6813 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6814 phy->ver_addr);
6815 }
6816
6817 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6818 struct bnx2x_phy *phy,
6819 struct link_vars *vars)
6820 {
6821 u16 val;
6822 bnx2x_cl45_read(bp, phy,
6823 MDIO_AN_DEVAD,
6824 MDIO_AN_REG_STATUS, &val);
6825 bnx2x_cl45_read(bp, phy,
6826 MDIO_AN_DEVAD,
6827 MDIO_AN_REG_STATUS, &val);
6828 if (val & (1<<5))
6829 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6830 if ((val & (1<<0)) == 0)
6831 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6832 }
6833
6834 /******************************************************************/
6835 /* common BCM8073/BCM8727 PHY SECTION */
6836 /******************************************************************/
6837 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6838 struct link_params *params,
6839 struct link_vars *vars)
6840 {
6841 struct bnx2x *bp = params->bp;
6842 if (phy->req_line_speed == SPEED_10 ||
6843 phy->req_line_speed == SPEED_100) {
6844 vars->flow_ctrl = phy->req_flow_ctrl;
6845 return;
6846 }
6847
6848 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6849 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6850 u16 pause_result;
6851 u16 ld_pause; /* local */
6852 u16 lp_pause; /* link partner */
6853 bnx2x_cl45_read(bp, phy,
6854 MDIO_AN_DEVAD,
6855 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6856
6857 bnx2x_cl45_read(bp, phy,
6858 MDIO_AN_DEVAD,
6859 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6860 pause_result = (ld_pause &
6861 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6862 pause_result |= (lp_pause &
6863 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6864
6865 bnx2x_pause_resolve(vars, pause_result);
6866 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6867 pause_result);
6868 }
6869 }
6870 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6871 struct bnx2x_phy *phy,
6872 u8 port)
6873 {
6874 u32 count = 0;
6875 u16 fw_ver1, fw_msgout;
6876 int rc = 0;
6877
6878 /* Boot port from external ROM */
6879 /* EDC grst */
6880 bnx2x_cl45_write(bp, phy,
6881 MDIO_PMA_DEVAD,
6882 MDIO_PMA_REG_GEN_CTRL,
6883 0x0001);
6884
6885 /* ucode reboot and rst */
6886 bnx2x_cl45_write(bp, phy,
6887 MDIO_PMA_DEVAD,
6888 MDIO_PMA_REG_GEN_CTRL,
6889 0x008c);
6890
6891 bnx2x_cl45_write(bp, phy,
6892 MDIO_PMA_DEVAD,
6893 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6894
6895 /* Reset internal microprocessor */
6896 bnx2x_cl45_write(bp, phy,
6897 MDIO_PMA_DEVAD,
6898 MDIO_PMA_REG_GEN_CTRL,
6899 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6900
6901 /* Release srst bit */
6902 bnx2x_cl45_write(bp, phy,
6903 MDIO_PMA_DEVAD,
6904 MDIO_PMA_REG_GEN_CTRL,
6905 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6906
6907 /* Delay 100ms per the PHY specifications */
6908 msleep(100);
6909
6910 /* 8073 sometimes taking longer to download */
6911 do {
6912 count++;
6913 if (count > 300) {
6914 DP(NETIF_MSG_LINK,
6915 "bnx2x_8073_8727_external_rom_boot port %x:"
6916 "Download failed. fw version = 0x%x\n",
6917 port, fw_ver1);
6918 rc = -EINVAL;
6919 break;
6920 }
6921
6922 bnx2x_cl45_read(bp, phy,
6923 MDIO_PMA_DEVAD,
6924 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6925 bnx2x_cl45_read(bp, phy,
6926 MDIO_PMA_DEVAD,
6927 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6928
6929 msleep(1);
6930 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6931 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6932 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6933
6934 /* Clear ser_boot_ctl bit */
6935 bnx2x_cl45_write(bp, phy,
6936 MDIO_PMA_DEVAD,
6937 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6938 bnx2x_save_bcm_spirom_ver(bp, phy, port);
6939
6940 DP(NETIF_MSG_LINK,
6941 "bnx2x_8073_8727_external_rom_boot port %x:"
6942 "Download complete. fw version = 0x%x\n",
6943 port, fw_ver1);
6944
6945 return rc;
6946 }
6947
6948 /******************************************************************/
6949 /* BCM8073 PHY SECTION */
6950 /******************************************************************/
6951 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6952 {
6953 /* This is only required for 8073A1, version 102 only */
6954 u16 val;
6955
6956 /* Read 8073 HW revision*/
6957 bnx2x_cl45_read(bp, phy,
6958 MDIO_PMA_DEVAD,
6959 MDIO_PMA_REG_8073_CHIP_REV, &val);
6960
6961 if (val != 1) {
6962 /* No need to workaround in 8073 A1 */
6963 return 0;
6964 }
6965
6966 bnx2x_cl45_read(bp, phy,
6967 MDIO_PMA_DEVAD,
6968 MDIO_PMA_REG_ROM_VER2, &val);
6969
6970 /* SNR should be applied only for version 0x102 */
6971 if (val != 0x102)
6972 return 0;
6973
6974 return 1;
6975 }
6976
6977 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6978 {
6979 u16 val, cnt, cnt1 ;
6980
6981 bnx2x_cl45_read(bp, phy,
6982 MDIO_PMA_DEVAD,
6983 MDIO_PMA_REG_8073_CHIP_REV, &val);
6984
6985 if (val > 0) {
6986 /* No need to workaround in 8073 A1 */
6987 return 0;
6988 }
6989 /* XAUI workaround in 8073 A0: */
6990
6991 /*
6992 * After loading the boot ROM and restarting Autoneg, poll
6993 * Dev1, Reg $C820:
6994 */
6995
6996 for (cnt = 0; cnt < 1000; cnt++) {
6997 bnx2x_cl45_read(bp, phy,
6998 MDIO_PMA_DEVAD,
6999 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7000 &val);
7001 /*
7002 * If bit [14] = 0 or bit [13] = 0, continue on with
7003 * system initialization (XAUI work-around not required, as
7004 * these bits indicate 2.5G or 1G link up).
7005 */
7006 if (!(val & (1<<14)) || !(val & (1<<13))) {
7007 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7008 return 0;
7009 } else if (!(val & (1<<15))) {
7010 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7011 /*
7012 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7013 * MSB (bit15) goes to 1 (indicating that the XAUI
7014 * workaround has completed), then continue on with
7015 * system initialization.
7016 */
7017 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7018 bnx2x_cl45_read(bp, phy,
7019 MDIO_PMA_DEVAD,
7020 MDIO_PMA_REG_8073_XAUI_WA, &val);
7021 if (val & (1<<15)) {
7022 DP(NETIF_MSG_LINK,
7023 "XAUI workaround has completed\n");
7024 return 0;
7025 }
7026 msleep(3);
7027 }
7028 break;
7029 }
7030 msleep(3);
7031 }
7032 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7033 return -EINVAL;
7034 }
7035
7036 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7037 {
7038 /* Force KR or KX */
7039 bnx2x_cl45_write(bp, phy,
7040 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7041 bnx2x_cl45_write(bp, phy,
7042 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7043 bnx2x_cl45_write(bp, phy,
7044 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7045 bnx2x_cl45_write(bp, phy,
7046 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7047 }
7048
7049 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7050 struct bnx2x_phy *phy,
7051 struct link_vars *vars)
7052 {
7053 u16 cl37_val;
7054 struct bnx2x *bp = params->bp;
7055 bnx2x_cl45_read(bp, phy,
7056 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7057
7058 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7059 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7060 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7061 if ((vars->ieee_fc &
7062 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7063 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7064 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7065 }
7066 if ((vars->ieee_fc &
7067 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7068 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7069 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7070 }
7071 if ((vars->ieee_fc &
7072 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7073 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7074 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7075 }
7076 DP(NETIF_MSG_LINK,
7077 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7078
7079 bnx2x_cl45_write(bp, phy,
7080 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7081 msleep(500);
7082 }
7083
7084 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7085 struct link_params *params,
7086 struct link_vars *vars)
7087 {
7088 struct bnx2x *bp = params->bp;
7089 u16 val = 0, tmp1;
7090 u8 gpio_port;
7091 DP(NETIF_MSG_LINK, "Init 8073\n");
7092
7093 if (CHIP_IS_E2(bp))
7094 gpio_port = BP_PATH(bp);
7095 else
7096 gpio_port = params->port;
7097 /* Restore normal power mode*/
7098 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7099 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7100
7101 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7102 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7103
7104 /* enable LASI */
7105 bnx2x_cl45_write(bp, phy,
7106 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7107 bnx2x_cl45_write(bp, phy,
7108 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7109
7110 bnx2x_8073_set_pause_cl37(params, phy, vars);
7111
7112 bnx2x_cl45_read(bp, phy,
7113 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7114
7115 bnx2x_cl45_read(bp, phy,
7116 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7117
7118 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7119
7120 /* Swap polarity if required - Must be done only in non-1G mode */
7121 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7122 /* Configure the 8073 to swap _P and _N of the KR lines */
7123 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7124 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7125 bnx2x_cl45_read(bp, phy,
7126 MDIO_PMA_DEVAD,
7127 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7128 bnx2x_cl45_write(bp, phy,
7129 MDIO_PMA_DEVAD,
7130 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7131 (val | (3<<9)));
7132 }
7133
7134
7135 /* Enable CL37 BAM */
7136 if (REG_RD(bp, params->shmem_base +
7137 offsetof(struct shmem_region, dev_info.
7138 port_hw_config[params->port].default_cfg)) &
7139 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7140
7141 bnx2x_cl45_read(bp, phy,
7142 MDIO_AN_DEVAD,
7143 MDIO_AN_REG_8073_BAM, &val);
7144 bnx2x_cl45_write(bp, phy,
7145 MDIO_AN_DEVAD,
7146 MDIO_AN_REG_8073_BAM, val | 1);
7147 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7148 }
7149 if (params->loopback_mode == LOOPBACK_EXT) {
7150 bnx2x_807x_force_10G(bp, phy);
7151 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7152 return 0;
7153 } else {
7154 bnx2x_cl45_write(bp, phy,
7155 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7156 }
7157 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7158 if (phy->req_line_speed == SPEED_10000) {
7159 val = (1<<7);
7160 } else if (phy->req_line_speed == SPEED_2500) {
7161 val = (1<<5);
7162 /*
7163 * Note that 2.5G works only when used with 1G
7164 * advertisement
7165 */
7166 } else
7167 val = (1<<5);
7168 } else {
7169 val = 0;
7170 if (phy->speed_cap_mask &
7171 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7172 val |= (1<<7);
7173
7174 /* Note that 2.5G works only when used with 1G advertisement */
7175 if (phy->speed_cap_mask &
7176 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7177 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7178 val |= (1<<5);
7179 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7180 }
7181
7182 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7183 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7184
7185 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7186 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7187 (phy->req_line_speed == SPEED_2500)) {
7188 u16 phy_ver;
7189 /* Allow 2.5G for A1 and above */
7190 bnx2x_cl45_read(bp, phy,
7191 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7192 &phy_ver);
7193 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7194 if (phy_ver > 0)
7195 tmp1 |= 1;
7196 else
7197 tmp1 &= 0xfffe;
7198 } else {
7199 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7200 tmp1 &= 0xfffe;
7201 }
7202
7203 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7204 /* Add support for CL37 (passive mode) II */
7205
7206 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7207 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7208 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7209 0x20 : 0x40)));
7210
7211 /* Add support for CL37 (passive mode) III */
7212 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7213
7214 /*
7215 * The SNR will improve about 2db by changing BW and FEE main
7216 * tap. Rest commands are executed after link is up
7217 * Change FFE main cursor to 5 in EDC register
7218 */
7219 if (bnx2x_8073_is_snr_needed(bp, phy))
7220 bnx2x_cl45_write(bp, phy,
7221 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7222 0xFB0C);
7223
7224 /* Enable FEC (Forware Error Correction) Request in the AN */
7225 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7226 tmp1 |= (1<<15);
7227 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7228
7229 bnx2x_ext_phy_set_pause(params, phy, vars);
7230
7231 /* Restart autoneg */
7232 msleep(500);
7233 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7234 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7235 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7236 return 0;
7237 }
7238
7239 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7240 struct link_params *params,
7241 struct link_vars *vars)
7242 {
7243 struct bnx2x *bp = params->bp;
7244 u8 link_up = 0;
7245 u16 val1, val2;
7246 u16 link_status = 0;
7247 u16 an1000_status = 0;
7248
7249 bnx2x_cl45_read(bp, phy,
7250 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7251
7252 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7253
7254 /* clear the interrupt LASI status register */
7255 bnx2x_cl45_read(bp, phy,
7256 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7257 bnx2x_cl45_read(bp, phy,
7258 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7259 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7260 /* Clear MSG-OUT */
7261 bnx2x_cl45_read(bp, phy,
7262 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7263
7264 /* Check the LASI */
7265 bnx2x_cl45_read(bp, phy,
7266 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7267
7268 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7269
7270 /* Check the link status */
7271 bnx2x_cl45_read(bp, phy,
7272 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7273 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7274
7275 bnx2x_cl45_read(bp, phy,
7276 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7277 bnx2x_cl45_read(bp, phy,
7278 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7279 link_up = ((val1 & 4) == 4);
7280 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7281
7282 if (link_up &&
7283 ((phy->req_line_speed != SPEED_10000))) {
7284 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7285 return 0;
7286 }
7287 bnx2x_cl45_read(bp, phy,
7288 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7289 bnx2x_cl45_read(bp, phy,
7290 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7291
7292 /* Check the link status on 1.1.2 */
7293 bnx2x_cl45_read(bp, phy,
7294 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7295 bnx2x_cl45_read(bp, phy,
7296 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7297 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7298 "an_link_status=0x%x\n", val2, val1, an1000_status);
7299
7300 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7301 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7302 /*
7303 * The SNR will improve about 2dbby changing the BW and FEE main
7304 * tap. The 1st write to change FFE main tap is set before
7305 * restart AN. Change PLL Bandwidth in EDC register
7306 */
7307 bnx2x_cl45_write(bp, phy,
7308 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7309 0x26BC);
7310
7311 /* Change CDR Bandwidth in EDC register */
7312 bnx2x_cl45_write(bp, phy,
7313 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7314 0x0333);
7315 }
7316 bnx2x_cl45_read(bp, phy,
7317 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7318 &link_status);
7319
7320 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7321 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7322 link_up = 1;
7323 vars->line_speed = SPEED_10000;
7324 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7325 params->port);
7326 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7327 link_up = 1;
7328 vars->line_speed = SPEED_2500;
7329 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7330 params->port);
7331 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7332 link_up = 1;
7333 vars->line_speed = SPEED_1000;
7334 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7335 params->port);
7336 } else {
7337 link_up = 0;
7338 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7339 params->port);
7340 }
7341
7342 if (link_up) {
7343 /* Swap polarity if required */
7344 if (params->lane_config &
7345 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7346 /* Configure the 8073 to swap P and N of the KR lines */
7347 bnx2x_cl45_read(bp, phy,
7348 MDIO_XS_DEVAD,
7349 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7350 /*
7351 * Set bit 3 to invert Rx in 1G mode and clear this bit
7352 * when it`s in 10G mode.
7353 */
7354 if (vars->line_speed == SPEED_1000) {
7355 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7356 "the 8073\n");
7357 val1 |= (1<<3);
7358 } else
7359 val1 &= ~(1<<3);
7360
7361 bnx2x_cl45_write(bp, phy,
7362 MDIO_XS_DEVAD,
7363 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7364 val1);
7365 }
7366 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7367 bnx2x_8073_resolve_fc(phy, params, vars);
7368 vars->duplex = DUPLEX_FULL;
7369 }
7370 return link_up;
7371 }
7372
7373 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7374 struct link_params *params)
7375 {
7376 struct bnx2x *bp = params->bp;
7377 u8 gpio_port;
7378 if (CHIP_IS_E2(bp))
7379 gpio_port = BP_PATH(bp);
7380 else
7381 gpio_port = params->port;
7382 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7383 gpio_port);
7384 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7385 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7386 gpio_port);
7387 }
7388
7389 /******************************************************************/
7390 /* BCM8705 PHY SECTION */
7391 /******************************************************************/
7392 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7393 struct link_params *params,
7394 struct link_vars *vars)
7395 {
7396 struct bnx2x *bp = params->bp;
7397 DP(NETIF_MSG_LINK, "init 8705\n");
7398 /* Restore normal power mode*/
7399 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7400 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7401 /* HW reset */
7402 bnx2x_ext_phy_hw_reset(bp, params->port);
7403 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7404 bnx2x_wait_reset_complete(bp, phy, params);
7405
7406 bnx2x_cl45_write(bp, phy,
7407 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7408 bnx2x_cl45_write(bp, phy,
7409 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7410 bnx2x_cl45_write(bp, phy,
7411 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7412 bnx2x_cl45_write(bp, phy,
7413 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7414 /* BCM8705 doesn't have microcode, hence the 0 */
7415 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7416 return 0;
7417 }
7418
7419 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7420 struct link_params *params,
7421 struct link_vars *vars)
7422 {
7423 u8 link_up = 0;
7424 u16 val1, rx_sd;
7425 struct bnx2x *bp = params->bp;
7426 DP(NETIF_MSG_LINK, "read status 8705\n");
7427 bnx2x_cl45_read(bp, phy,
7428 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7429 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7430
7431 bnx2x_cl45_read(bp, phy,
7432 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7433 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7434
7435 bnx2x_cl45_read(bp, phy,
7436 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7437
7438 bnx2x_cl45_read(bp, phy,
7439 MDIO_PMA_DEVAD, 0xc809, &val1);
7440 bnx2x_cl45_read(bp, phy,
7441 MDIO_PMA_DEVAD, 0xc809, &val1);
7442
7443 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7444 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7445 if (link_up) {
7446 vars->line_speed = SPEED_10000;
7447 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7448 }
7449 return link_up;
7450 }
7451
7452 /******************************************************************/
7453 /* SFP+ module Section */
7454 /******************************************************************/
7455 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7456 struct bnx2x_phy *phy,
7457 u8 pmd_dis)
7458 {
7459 struct bnx2x *bp = params->bp;
7460 /*
7461 * Disable transmitter only for bootcodes which can enable it afterwards
7462 * (for D3 link)
7463 */
7464 if (pmd_dis) {
7465 if (params->feature_config_flags &
7466 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7467 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7468 else {
7469 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7470 return;
7471 }
7472 } else
7473 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7474 bnx2x_cl45_write(bp, phy,
7475 MDIO_PMA_DEVAD,
7476 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7477 }
7478
7479 static u8 bnx2x_get_gpio_port(struct link_params *params)
7480 {
7481 u8 gpio_port;
7482 u32 swap_val, swap_override;
7483 struct bnx2x *bp = params->bp;
7484 if (CHIP_IS_E2(bp))
7485 gpio_port = BP_PATH(bp);
7486 else
7487 gpio_port = params->port;
7488 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7489 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7490 return gpio_port ^ (swap_val && swap_override);
7491 }
7492
7493 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7494 struct bnx2x_phy *phy,
7495 u8 tx_en)
7496 {
7497 u16 val;
7498 u8 port = params->port;
7499 struct bnx2x *bp = params->bp;
7500 u32 tx_en_mode;
7501
7502 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7503 tx_en_mode = REG_RD(bp, params->shmem_base +
7504 offsetof(struct shmem_region,
7505 dev_info.port_hw_config[port].sfp_ctrl)) &
7506 PORT_HW_CFG_TX_LASER_MASK;
7507 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7508 "mode = %x\n", tx_en, port, tx_en_mode);
7509 switch (tx_en_mode) {
7510 case PORT_HW_CFG_TX_LASER_MDIO:
7511
7512 bnx2x_cl45_read(bp, phy,
7513 MDIO_PMA_DEVAD,
7514 MDIO_PMA_REG_PHY_IDENTIFIER,
7515 &val);
7516
7517 if (tx_en)
7518 val &= ~(1<<15);
7519 else
7520 val |= (1<<15);
7521
7522 bnx2x_cl45_write(bp, phy,
7523 MDIO_PMA_DEVAD,
7524 MDIO_PMA_REG_PHY_IDENTIFIER,
7525 val);
7526 break;
7527 case PORT_HW_CFG_TX_LASER_GPIO0:
7528 case PORT_HW_CFG_TX_LASER_GPIO1:
7529 case PORT_HW_CFG_TX_LASER_GPIO2:
7530 case PORT_HW_CFG_TX_LASER_GPIO3:
7531 {
7532 u16 gpio_pin;
7533 u8 gpio_port, gpio_mode;
7534 if (tx_en)
7535 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7536 else
7537 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7538
7539 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7540 gpio_port = bnx2x_get_gpio_port(params);
7541 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7542 break;
7543 }
7544 default:
7545 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7546 break;
7547 }
7548 }
7549
7550 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7551 struct bnx2x_phy *phy,
7552 u8 tx_en)
7553 {
7554 struct bnx2x *bp = params->bp;
7555 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7556 if (CHIP_IS_E3(bp))
7557 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7558 else
7559 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7560 }
7561
7562 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7563 struct link_params *params,
7564 u16 addr, u8 byte_cnt, u8 *o_buf)
7565 {
7566 struct bnx2x *bp = params->bp;
7567 u16 val = 0;
7568 u16 i;
7569 if (byte_cnt > 16) {
7570 DP(NETIF_MSG_LINK,
7571 "Reading from eeprom is limited to 0xf\n");
7572 return -EINVAL;
7573 }
7574 /* Set the read command byte count */
7575 bnx2x_cl45_write(bp, phy,
7576 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7577 (byte_cnt | 0xa000));
7578
7579 /* Set the read command address */
7580 bnx2x_cl45_write(bp, phy,
7581 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7582 addr);
7583
7584 /* Activate read command */
7585 bnx2x_cl45_write(bp, phy,
7586 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7587 0x2c0f);
7588
7589 /* Wait up to 500us for command complete status */
7590 for (i = 0; i < 100; i++) {
7591 bnx2x_cl45_read(bp, phy,
7592 MDIO_PMA_DEVAD,
7593 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7594 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7595 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7596 break;
7597 udelay(5);
7598 }
7599
7600 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7601 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7602 DP(NETIF_MSG_LINK,
7603 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7604 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7605 return -EINVAL;
7606 }
7607
7608 /* Read the buffer */
7609 for (i = 0; i < byte_cnt; i++) {
7610 bnx2x_cl45_read(bp, phy,
7611 MDIO_PMA_DEVAD,
7612 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7613 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7614 }
7615
7616 for (i = 0; i < 100; i++) {
7617 bnx2x_cl45_read(bp, phy,
7618 MDIO_PMA_DEVAD,
7619 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7620 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7621 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7622 return 0;
7623 msleep(1);
7624 }
7625 return -EINVAL;
7626 }
7627
7628 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7629 struct link_params *params,
7630 u16 addr, u8 byte_cnt,
7631 u8 *o_buf)
7632 {
7633 int rc = 0;
7634 u8 i, j = 0, cnt = 0;
7635 u32 data_array[4];
7636 u16 addr32;
7637 struct bnx2x *bp = params->bp;
7638 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7639 " addr %d, cnt %d\n",
7640 addr, byte_cnt);*/
7641 if (byte_cnt > 16) {
7642 DP(NETIF_MSG_LINK,
7643 "Reading from eeprom is limited to 16 bytes\n");
7644 return -EINVAL;
7645 }
7646
7647 /* 4 byte aligned address */
7648 addr32 = addr & (~0x3);
7649 do {
7650 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7651 data_array);
7652 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7653
7654 if (rc == 0) {
7655 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7656 o_buf[j] = *((u8 *)data_array + i);
7657 j++;
7658 }
7659 }
7660
7661 return rc;
7662 }
7663
7664 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7665 struct link_params *params,
7666 u16 addr, u8 byte_cnt, u8 *o_buf)
7667 {
7668 struct bnx2x *bp = params->bp;
7669 u16 val, i;
7670
7671 if (byte_cnt > 16) {
7672 DP(NETIF_MSG_LINK,
7673 "Reading from eeprom is limited to 0xf\n");
7674 return -EINVAL;
7675 }
7676
7677 /* Need to read from 1.8000 to clear it */
7678 bnx2x_cl45_read(bp, phy,
7679 MDIO_PMA_DEVAD,
7680 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7681 &val);
7682
7683 /* Set the read command byte count */
7684 bnx2x_cl45_write(bp, phy,
7685 MDIO_PMA_DEVAD,
7686 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7687 ((byte_cnt < 2) ? 2 : byte_cnt));
7688
7689 /* Set the read command address */
7690 bnx2x_cl45_write(bp, phy,
7691 MDIO_PMA_DEVAD,
7692 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7693 addr);
7694 /* Set the destination address */
7695 bnx2x_cl45_write(bp, phy,
7696 MDIO_PMA_DEVAD,
7697 0x8004,
7698 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7699
7700 /* Activate read command */
7701 bnx2x_cl45_write(bp, phy,
7702 MDIO_PMA_DEVAD,
7703 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7704 0x8002);
7705 /*
7706 * Wait appropriate time for two-wire command to finish before
7707 * polling the status register
7708 */
7709 msleep(1);
7710
7711 /* Wait up to 500us for command complete status */
7712 for (i = 0; i < 100; i++) {
7713 bnx2x_cl45_read(bp, phy,
7714 MDIO_PMA_DEVAD,
7715 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7716 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7717 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7718 break;
7719 udelay(5);
7720 }
7721
7722 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7723 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7724 DP(NETIF_MSG_LINK,
7725 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7726 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7727 return -EFAULT;
7728 }
7729
7730 /* Read the buffer */
7731 for (i = 0; i < byte_cnt; i++) {
7732 bnx2x_cl45_read(bp, phy,
7733 MDIO_PMA_DEVAD,
7734 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7735 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7736 }
7737
7738 for (i = 0; i < 100; i++) {
7739 bnx2x_cl45_read(bp, phy,
7740 MDIO_PMA_DEVAD,
7741 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7742 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7743 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7744 return 0;
7745 msleep(1);
7746 }
7747
7748 return -EINVAL;
7749 }
7750
7751 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7752 struct link_params *params, u16 addr,
7753 u8 byte_cnt, u8 *o_buf)
7754 {
7755 int rc = -EINVAL;
7756 switch (phy->type) {
7757 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7758 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7759 byte_cnt, o_buf);
7760 break;
7761 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7762 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7763 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7764 byte_cnt, o_buf);
7765 break;
7766 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7767 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7768 byte_cnt, o_buf);
7769 break;
7770 }
7771 return rc;
7772 }
7773
7774 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7775 struct link_params *params,
7776 u16 *edc_mode)
7777 {
7778 struct bnx2x *bp = params->bp;
7779 u32 sync_offset = 0, phy_idx, media_types;
7780 u8 val, check_limiting_mode = 0;
7781 *edc_mode = EDC_MODE_LIMITING;
7782
7783 phy->media_type = ETH_PHY_UNSPECIFIED;
7784 /* First check for copper cable */
7785 if (bnx2x_read_sfp_module_eeprom(phy,
7786 params,
7787 SFP_EEPROM_CON_TYPE_ADDR,
7788 1,
7789 &val) != 0) {
7790 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7791 return -EINVAL;
7792 }
7793
7794 switch (val) {
7795 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7796 {
7797 u8 copper_module_type;
7798 phy->media_type = ETH_PHY_DA_TWINAX;
7799 /*
7800 * Check if its active cable (includes SFP+ module)
7801 * of passive cable
7802 */
7803 if (bnx2x_read_sfp_module_eeprom(phy,
7804 params,
7805 SFP_EEPROM_FC_TX_TECH_ADDR,
7806 1,
7807 &copper_module_type) != 0) {
7808 DP(NETIF_MSG_LINK,
7809 "Failed to read copper-cable-type"
7810 " from SFP+ EEPROM\n");
7811 return -EINVAL;
7812 }
7813
7814 if (copper_module_type &
7815 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7816 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7817 check_limiting_mode = 1;
7818 } else if (copper_module_type &
7819 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7820 DP(NETIF_MSG_LINK,
7821 "Passive Copper cable detected\n");
7822 *edc_mode =
7823 EDC_MODE_PASSIVE_DAC;
7824 } else {
7825 DP(NETIF_MSG_LINK,
7826 "Unknown copper-cable-type 0x%x !!!\n",
7827 copper_module_type);
7828 return -EINVAL;
7829 }
7830 break;
7831 }
7832 case SFP_EEPROM_CON_TYPE_VAL_LC:
7833 phy->media_type = ETH_PHY_SFP_FIBER;
7834 DP(NETIF_MSG_LINK, "Optic module detected\n");
7835 check_limiting_mode = 1;
7836 break;
7837 default:
7838 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7839 val);
7840 return -EINVAL;
7841 }
7842 sync_offset = params->shmem_base +
7843 offsetof(struct shmem_region,
7844 dev_info.port_hw_config[params->port].media_type);
7845 media_types = REG_RD(bp, sync_offset);
7846 /* Update media type for non-PMF sync */
7847 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7848 if (&(params->phy[phy_idx]) == phy) {
7849 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7850 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7851 media_types |= ((phy->media_type &
7852 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7853 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7854 break;
7855 }
7856 }
7857 REG_WR(bp, sync_offset, media_types);
7858 if (check_limiting_mode) {
7859 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7860 if (bnx2x_read_sfp_module_eeprom(phy,
7861 params,
7862 SFP_EEPROM_OPTIONS_ADDR,
7863 SFP_EEPROM_OPTIONS_SIZE,
7864 options) != 0) {
7865 DP(NETIF_MSG_LINK,
7866 "Failed to read Option field from module EEPROM\n");
7867 return -EINVAL;
7868 }
7869 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7870 *edc_mode = EDC_MODE_LINEAR;
7871 else
7872 *edc_mode = EDC_MODE_LIMITING;
7873 }
7874 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7875 return 0;
7876 }
7877 /*
7878 * This function read the relevant field from the module (SFP+), and verify it
7879 * is compliant with this board
7880 */
7881 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7882 struct link_params *params)
7883 {
7884 struct bnx2x *bp = params->bp;
7885 u32 val, cmd;
7886 u32 fw_resp, fw_cmd_param;
7887 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7888 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7889 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7890 val = REG_RD(bp, params->shmem_base +
7891 offsetof(struct shmem_region, dev_info.
7892 port_feature_config[params->port].config));
7893 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7894 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7895 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7896 return 0;
7897 }
7898
7899 if (params->feature_config_flags &
7900 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7901 /* Use specific phy request */
7902 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7903 } else if (params->feature_config_flags &
7904 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7905 /* Use first phy request only in case of non-dual media*/
7906 if (DUAL_MEDIA(params)) {
7907 DP(NETIF_MSG_LINK,
7908 "FW does not support OPT MDL verification\n");
7909 return -EINVAL;
7910 }
7911 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7912 } else {
7913 /* No support in OPT MDL detection */
7914 DP(NETIF_MSG_LINK,
7915 "FW does not support OPT MDL verification\n");
7916 return -EINVAL;
7917 }
7918
7919 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7920 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7921 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7922 DP(NETIF_MSG_LINK, "Approved module\n");
7923 return 0;
7924 }
7925
7926 /* format the warning message */
7927 if (bnx2x_read_sfp_module_eeprom(phy,
7928 params,
7929 SFP_EEPROM_VENDOR_NAME_ADDR,
7930 SFP_EEPROM_VENDOR_NAME_SIZE,
7931 (u8 *)vendor_name))
7932 vendor_name[0] = '\0';
7933 else
7934 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7935 if (bnx2x_read_sfp_module_eeprom(phy,
7936 params,
7937 SFP_EEPROM_PART_NO_ADDR,
7938 SFP_EEPROM_PART_NO_SIZE,
7939 (u8 *)vendor_pn))
7940 vendor_pn[0] = '\0';
7941 else
7942 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7943
7944 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
7945 " Port %d from %s part number %s\n",
7946 params->port, vendor_name, vendor_pn);
7947 phy->flags |= FLAGS_SFP_NOT_APPROVED;
7948 return -EINVAL;
7949 }
7950
7951 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7952 struct link_params *params)
7953
7954 {
7955 u8 val;
7956 struct bnx2x *bp = params->bp;
7957 u16 timeout;
7958 /*
7959 * Initialization time after hot-plug may take up to 300ms for
7960 * some phys type ( e.g. JDSU )
7961 */
7962
7963 for (timeout = 0; timeout < 60; timeout++) {
7964 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7965 == 0) {
7966 DP(NETIF_MSG_LINK,
7967 "SFP+ module initialization took %d ms\n",
7968 timeout * 5);
7969 return 0;
7970 }
7971 msleep(5);
7972 }
7973 return -EINVAL;
7974 }
7975
7976 static void bnx2x_8727_power_module(struct bnx2x *bp,
7977 struct bnx2x_phy *phy,
7978 u8 is_power_up) {
7979 /* Make sure GPIOs are not using for LED mode */
7980 u16 val;
7981 /*
7982 * In the GPIO register, bit 4 is use to determine if the GPIOs are
7983 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7984 * output
7985 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7986 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7987 * where the 1st bit is the over-current(only input), and 2nd bit is
7988 * for power( only output )
7989 *
7990 * In case of NOC feature is disabled and power is up, set GPIO control
7991 * as input to enable listening of over-current indication
7992 */
7993 if (phy->flags & FLAGS_NOC)
7994 return;
7995 if (is_power_up)
7996 val = (1<<4);
7997 else
7998 /*
7999 * Set GPIO control to OUTPUT, and set the power bit
8000 * to according to the is_power_up
8001 */
8002 val = (1<<1);
8003
8004 bnx2x_cl45_write(bp, phy,
8005 MDIO_PMA_DEVAD,
8006 MDIO_PMA_REG_8727_GPIO_CTRL,
8007 val);
8008 }
8009
8010 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8011 struct bnx2x_phy *phy,
8012 u16 edc_mode)
8013 {
8014 u16 cur_limiting_mode;
8015
8016 bnx2x_cl45_read(bp, phy,
8017 MDIO_PMA_DEVAD,
8018 MDIO_PMA_REG_ROM_VER2,
8019 &cur_limiting_mode);
8020 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8021 cur_limiting_mode);
8022
8023 if (edc_mode == EDC_MODE_LIMITING) {
8024 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8025 bnx2x_cl45_write(bp, phy,
8026 MDIO_PMA_DEVAD,
8027 MDIO_PMA_REG_ROM_VER2,
8028 EDC_MODE_LIMITING);
8029 } else { /* LRM mode ( default )*/
8030
8031 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8032
8033 /*
8034 * Changing to LRM mode takes quite few seconds. So do it only
8035 * if current mode is limiting (default is LRM)
8036 */
8037 if (cur_limiting_mode != EDC_MODE_LIMITING)
8038 return 0;
8039
8040 bnx2x_cl45_write(bp, phy,
8041 MDIO_PMA_DEVAD,
8042 MDIO_PMA_REG_LRM_MODE,
8043 0);
8044 bnx2x_cl45_write(bp, phy,
8045 MDIO_PMA_DEVAD,
8046 MDIO_PMA_REG_ROM_VER2,
8047 0x128);
8048 bnx2x_cl45_write(bp, phy,
8049 MDIO_PMA_DEVAD,
8050 MDIO_PMA_REG_MISC_CTRL0,
8051 0x4008);
8052 bnx2x_cl45_write(bp, phy,
8053 MDIO_PMA_DEVAD,
8054 MDIO_PMA_REG_LRM_MODE,
8055 0xaaaa);
8056 }
8057 return 0;
8058 }
8059
8060 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8061 struct bnx2x_phy *phy,
8062 u16 edc_mode)
8063 {
8064 u16 phy_identifier;
8065 u16 rom_ver2_val;
8066 bnx2x_cl45_read(bp, phy,
8067 MDIO_PMA_DEVAD,
8068 MDIO_PMA_REG_PHY_IDENTIFIER,
8069 &phy_identifier);
8070
8071 bnx2x_cl45_write(bp, phy,
8072 MDIO_PMA_DEVAD,
8073 MDIO_PMA_REG_PHY_IDENTIFIER,
8074 (phy_identifier & ~(1<<9)));
8075
8076 bnx2x_cl45_read(bp, phy,
8077 MDIO_PMA_DEVAD,
8078 MDIO_PMA_REG_ROM_VER2,
8079 &rom_ver2_val);
8080 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8081 bnx2x_cl45_write(bp, phy,
8082 MDIO_PMA_DEVAD,
8083 MDIO_PMA_REG_ROM_VER2,
8084 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8085
8086 bnx2x_cl45_write(bp, phy,
8087 MDIO_PMA_DEVAD,
8088 MDIO_PMA_REG_PHY_IDENTIFIER,
8089 (phy_identifier | (1<<9)));
8090
8091 return 0;
8092 }
8093
8094 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8095 struct link_params *params,
8096 u32 action)
8097 {
8098 struct bnx2x *bp = params->bp;
8099
8100 switch (action) {
8101 case DISABLE_TX:
8102 bnx2x_sfp_set_transmitter(params, phy, 0);
8103 break;
8104 case ENABLE_TX:
8105 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8106 bnx2x_sfp_set_transmitter(params, phy, 1);
8107 break;
8108 default:
8109 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8110 action);
8111 return;
8112 }
8113 }
8114
8115 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8116 u8 gpio_mode)
8117 {
8118 struct bnx2x *bp = params->bp;
8119
8120 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8121 offsetof(struct shmem_region,
8122 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8123 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8124 switch (fault_led_gpio) {
8125 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8126 return;
8127 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8128 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8129 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8130 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8131 {
8132 u8 gpio_port = bnx2x_get_gpio_port(params);
8133 u16 gpio_pin = fault_led_gpio -
8134 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8135 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8136 "pin %x port %x mode %x\n",
8137 gpio_pin, gpio_port, gpio_mode);
8138 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8139 }
8140 break;
8141 default:
8142 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8143 fault_led_gpio);
8144 }
8145 }
8146
8147 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8148 u8 gpio_mode)
8149 {
8150 u32 pin_cfg;
8151 u8 port = params->port;
8152 struct bnx2x *bp = params->bp;
8153 pin_cfg = (REG_RD(bp, params->shmem_base +
8154 offsetof(struct shmem_region,
8155 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8156 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8157 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8158 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8159 gpio_mode, pin_cfg);
8160 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8161 }
8162
8163 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8164 u8 gpio_mode)
8165 {
8166 struct bnx2x *bp = params->bp;
8167 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8168 if (CHIP_IS_E3(bp)) {
8169 /*
8170 * Low ==> if SFP+ module is supported otherwise
8171 * High ==> if SFP+ module is not on the approved vendor list
8172 */
8173 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8174 } else
8175 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8176 }
8177
8178 static void bnx2x_warpcore_power_module(struct link_params *params,
8179 struct bnx2x_phy *phy,
8180 u8 power)
8181 {
8182 u32 pin_cfg;
8183 struct bnx2x *bp = params->bp;
8184
8185 pin_cfg = (REG_RD(bp, params->shmem_base +
8186 offsetof(struct shmem_region,
8187 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8188 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8189 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8190
8191 if (pin_cfg == PIN_CFG_NA)
8192 return;
8193 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8194 power, pin_cfg);
8195 /*
8196 * Low ==> corresponding SFP+ module is powered
8197 * high ==> the SFP+ module is powered down
8198 */
8199 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8200 }
8201
8202 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8203 struct link_params *params)
8204 {
8205 struct bnx2x *bp = params->bp;
8206 bnx2x_warpcore_power_module(params, phy, 0);
8207 /* Put Warpcore in low power mode */
8208 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8209
8210 /* Put LCPLL in low power mode */
8211 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8212 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8213 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8214 }
8215
8216 static void bnx2x_power_sfp_module(struct link_params *params,
8217 struct bnx2x_phy *phy,
8218 u8 power)
8219 {
8220 struct bnx2x *bp = params->bp;
8221 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8222
8223 switch (phy->type) {
8224 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8225 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8226 bnx2x_8727_power_module(params->bp, phy, power);
8227 break;
8228 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8229 bnx2x_warpcore_power_module(params, phy, power);
8230 break;
8231 default:
8232 break;
8233 }
8234 }
8235 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8236 struct bnx2x_phy *phy,
8237 u16 edc_mode)
8238 {
8239 u16 val = 0;
8240 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8241 struct bnx2x *bp = params->bp;
8242
8243 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8244 /* This is a global register which controls all lanes */
8245 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8246 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8247 val &= ~(0xf << (lane << 2));
8248
8249 switch (edc_mode) {
8250 case EDC_MODE_LINEAR:
8251 case EDC_MODE_LIMITING:
8252 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8253 break;
8254 case EDC_MODE_PASSIVE_DAC:
8255 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8256 break;
8257 default:
8258 break;
8259 }
8260
8261 val |= (mode << (lane << 2));
8262 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8263 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8264 /* A must read */
8265 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8266 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8267
8268 /* Restart microcode to re-read the new mode */
8269 bnx2x_warpcore_reset_lane(bp, phy, 1);
8270 bnx2x_warpcore_reset_lane(bp, phy, 0);
8271
8272 }
8273
8274 static void bnx2x_set_limiting_mode(struct link_params *params,
8275 struct bnx2x_phy *phy,
8276 u16 edc_mode)
8277 {
8278 switch (phy->type) {
8279 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8280 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8281 break;
8282 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8283 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8284 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8285 break;
8286 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8287 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8288 break;
8289 }
8290 }
8291
8292 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8293 struct link_params *params)
8294 {
8295 struct bnx2x *bp = params->bp;
8296 u16 edc_mode;
8297 int rc = 0;
8298
8299 u32 val = REG_RD(bp, params->shmem_base +
8300 offsetof(struct shmem_region, dev_info.
8301 port_feature_config[params->port].config));
8302
8303 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8304 params->port);
8305 /* Power up module */
8306 bnx2x_power_sfp_module(params, phy, 1);
8307 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8308 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8309 return -EINVAL;
8310 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8311 /* check SFP+ module compatibility */
8312 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8313 rc = -EINVAL;
8314 /* Turn on fault module-detected led */
8315 bnx2x_set_sfp_module_fault_led(params,
8316 MISC_REGISTERS_GPIO_HIGH);
8317
8318 /* Check if need to power down the SFP+ module */
8319 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8320 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8321 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8322 bnx2x_power_sfp_module(params, phy, 0);
8323 return rc;
8324 }
8325 } else {
8326 /* Turn off fault module-detected led */
8327 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8328 }
8329
8330 /*
8331 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8332 * is done automatically
8333 */
8334 bnx2x_set_limiting_mode(params, phy, edc_mode);
8335
8336 /*
8337 * Enable transmit for this module if the module is approved, or
8338 * if unapproved modules should also enable the Tx laser
8339 */
8340 if (rc == 0 ||
8341 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8342 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8343 bnx2x_sfp_set_transmitter(params, phy, 1);
8344 else
8345 bnx2x_sfp_set_transmitter(params, phy, 0);
8346
8347 return rc;
8348 }
8349
8350 void bnx2x_handle_module_detect_int(struct link_params *params)
8351 {
8352 struct bnx2x *bp = params->bp;
8353 struct bnx2x_phy *phy;
8354 u32 gpio_val;
8355 u8 gpio_num, gpio_port;
8356 if (CHIP_IS_E3(bp))
8357 phy = &params->phy[INT_PHY];
8358 else
8359 phy = &params->phy[EXT_PHY1];
8360
8361 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8362 params->port, &gpio_num, &gpio_port) ==
8363 -EINVAL) {
8364 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8365 return;
8366 }
8367
8368 /* Set valid module led off */
8369 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8370
8371 /* Get current gpio val reflecting module plugged in / out*/
8372 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8373
8374 /* Call the handling function in case module is detected */
8375 if (gpio_val == 0) {
8376 bnx2x_power_sfp_module(params, phy, 1);
8377 bnx2x_set_gpio_int(bp, gpio_num,
8378 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8379 gpio_port);
8380 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8381 bnx2x_sfp_module_detection(phy, params);
8382 else
8383 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8384 } else {
8385 u32 val = REG_RD(bp, params->shmem_base +
8386 offsetof(struct shmem_region, dev_info.
8387 port_feature_config[params->port].
8388 config));
8389 bnx2x_set_gpio_int(bp, gpio_num,
8390 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8391 gpio_port);
8392 /*
8393 * Module was plugged out.
8394 * Disable transmit for this module
8395 */
8396 phy->media_type = ETH_PHY_NOT_PRESENT;
8397 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8398 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8399 CHIP_IS_E3(bp))
8400 bnx2x_sfp_set_transmitter(params, phy, 0);
8401 }
8402 }
8403
8404 /******************************************************************/
8405 /* Used by 8706 and 8727 */
8406 /******************************************************************/
8407 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8408 struct bnx2x_phy *phy,
8409 u16 alarm_status_offset,
8410 u16 alarm_ctrl_offset)
8411 {
8412 u16 alarm_status, val;
8413 bnx2x_cl45_read(bp, phy,
8414 MDIO_PMA_DEVAD, alarm_status_offset,
8415 &alarm_status);
8416 bnx2x_cl45_read(bp, phy,
8417 MDIO_PMA_DEVAD, alarm_status_offset,
8418 &alarm_status);
8419 /* Mask or enable the fault event. */
8420 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8421 if (alarm_status & (1<<0))
8422 val &= ~(1<<0);
8423 else
8424 val |= (1<<0);
8425 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8426 }
8427 /******************************************************************/
8428 /* common BCM8706/BCM8726 PHY SECTION */
8429 /******************************************************************/
8430 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8431 struct link_params *params,
8432 struct link_vars *vars)
8433 {
8434 u8 link_up = 0;
8435 u16 val1, val2, rx_sd, pcs_status;
8436 struct bnx2x *bp = params->bp;
8437 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8438 /* Clear RX Alarm*/
8439 bnx2x_cl45_read(bp, phy,
8440 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8441
8442 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8443 MDIO_PMA_LASI_TXCTRL);
8444
8445 /* clear LASI indication*/
8446 bnx2x_cl45_read(bp, phy,
8447 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8448 bnx2x_cl45_read(bp, phy,
8449 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8450 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8451
8452 bnx2x_cl45_read(bp, phy,
8453 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8454 bnx2x_cl45_read(bp, phy,
8455 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8456 bnx2x_cl45_read(bp, phy,
8457 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8458 bnx2x_cl45_read(bp, phy,
8459 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8460
8461 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8462 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8463 /*
8464 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8465 * are set, or if the autoneg bit 1 is set
8466 */
8467 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8468 if (link_up) {
8469 if (val2 & (1<<1))
8470 vars->line_speed = SPEED_1000;
8471 else
8472 vars->line_speed = SPEED_10000;
8473 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8474 vars->duplex = DUPLEX_FULL;
8475 }
8476
8477 /* Capture 10G link fault. Read twice to clear stale value. */
8478 if (vars->line_speed == SPEED_10000) {
8479 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8480 MDIO_PMA_LASI_TXSTAT, &val1);
8481 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8482 MDIO_PMA_LASI_TXSTAT, &val1);
8483 if (val1 & (1<<0))
8484 vars->fault_detected = 1;
8485 }
8486
8487 return link_up;
8488 }
8489
8490 /******************************************************************/
8491 /* BCM8706 PHY SECTION */
8492 /******************************************************************/
8493 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8494 struct link_params *params,
8495 struct link_vars *vars)
8496 {
8497 u32 tx_en_mode;
8498 u16 cnt, val, tmp1;
8499 struct bnx2x *bp = params->bp;
8500
8501 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8502 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8503 /* HW reset */
8504 bnx2x_ext_phy_hw_reset(bp, params->port);
8505 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8506 bnx2x_wait_reset_complete(bp, phy, params);
8507
8508 /* Wait until fw is loaded */
8509 for (cnt = 0; cnt < 100; cnt++) {
8510 bnx2x_cl45_read(bp, phy,
8511 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8512 if (val)
8513 break;
8514 msleep(10);
8515 }
8516 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8517 if ((params->feature_config_flags &
8518 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8519 u8 i;
8520 u16 reg;
8521 for (i = 0; i < 4; i++) {
8522 reg = MDIO_XS_8706_REG_BANK_RX0 +
8523 i*(MDIO_XS_8706_REG_BANK_RX1 -
8524 MDIO_XS_8706_REG_BANK_RX0);
8525 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8526 /* Clear first 3 bits of the control */
8527 val &= ~0x7;
8528 /* Set control bits according to configuration */
8529 val |= (phy->rx_preemphasis[i] & 0x7);
8530 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8531 " reg 0x%x <-- val 0x%x\n", reg, val);
8532 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8533 }
8534 }
8535 /* Force speed */
8536 if (phy->req_line_speed == SPEED_10000) {
8537 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8538
8539 bnx2x_cl45_write(bp, phy,
8540 MDIO_PMA_DEVAD,
8541 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8542 bnx2x_cl45_write(bp, phy,
8543 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8544 0);
8545 /* Arm LASI for link and Tx fault. */
8546 bnx2x_cl45_write(bp, phy,
8547 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8548 } else {
8549 /* Force 1Gbps using autoneg with 1G advertisement */
8550
8551 /* Allow CL37 through CL73 */
8552 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8553 bnx2x_cl45_write(bp, phy,
8554 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8555
8556 /* Enable Full-Duplex advertisement on CL37 */
8557 bnx2x_cl45_write(bp, phy,
8558 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8559 /* Enable CL37 AN */
8560 bnx2x_cl45_write(bp, phy,
8561 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8562 /* 1G support */
8563 bnx2x_cl45_write(bp, phy,
8564 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8565
8566 /* Enable clause 73 AN */
8567 bnx2x_cl45_write(bp, phy,
8568 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8569 bnx2x_cl45_write(bp, phy,
8570 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8571 0x0400);
8572 bnx2x_cl45_write(bp, phy,
8573 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8574 0x0004);
8575 }
8576 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8577
8578 /*
8579 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8580 * power mode, if TX Laser is disabled
8581 */
8582
8583 tx_en_mode = REG_RD(bp, params->shmem_base +
8584 offsetof(struct shmem_region,
8585 dev_info.port_hw_config[params->port].sfp_ctrl))
8586 & PORT_HW_CFG_TX_LASER_MASK;
8587
8588 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8589 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8590 bnx2x_cl45_read(bp, phy,
8591 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8592 tmp1 |= 0x1;
8593 bnx2x_cl45_write(bp, phy,
8594 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8595 }
8596
8597 return 0;
8598 }
8599
8600 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8601 struct link_params *params,
8602 struct link_vars *vars)
8603 {
8604 return bnx2x_8706_8726_read_status(phy, params, vars);
8605 }
8606
8607 /******************************************************************/
8608 /* BCM8726 PHY SECTION */
8609 /******************************************************************/
8610 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8611 struct link_params *params)
8612 {
8613 struct bnx2x *bp = params->bp;
8614 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8615 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8616 }
8617
8618 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8619 struct link_params *params)
8620 {
8621 struct bnx2x *bp = params->bp;
8622 /* Need to wait 100ms after reset */
8623 msleep(100);
8624
8625 /* Micro controller re-boot */
8626 bnx2x_cl45_write(bp, phy,
8627 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8628
8629 /* Set soft reset */
8630 bnx2x_cl45_write(bp, phy,
8631 MDIO_PMA_DEVAD,
8632 MDIO_PMA_REG_GEN_CTRL,
8633 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8634
8635 bnx2x_cl45_write(bp, phy,
8636 MDIO_PMA_DEVAD,
8637 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8638
8639 bnx2x_cl45_write(bp, phy,
8640 MDIO_PMA_DEVAD,
8641 MDIO_PMA_REG_GEN_CTRL,
8642 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8643
8644 /* wait for 150ms for microcode load */
8645 msleep(150);
8646
8647 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8648 bnx2x_cl45_write(bp, phy,
8649 MDIO_PMA_DEVAD,
8650 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8651
8652 msleep(200);
8653 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8654 }
8655
8656 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8657 struct link_params *params,
8658 struct link_vars *vars)
8659 {
8660 struct bnx2x *bp = params->bp;
8661 u16 val1;
8662 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8663 if (link_up) {
8664 bnx2x_cl45_read(bp, phy,
8665 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8666 &val1);
8667 if (val1 & (1<<15)) {
8668 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8669 link_up = 0;
8670 vars->line_speed = 0;
8671 }
8672 }
8673 return link_up;
8674 }
8675
8676
8677 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8678 struct link_params *params,
8679 struct link_vars *vars)
8680 {
8681 struct bnx2x *bp = params->bp;
8682 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8683
8684 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8685 bnx2x_wait_reset_complete(bp, phy, params);
8686
8687 bnx2x_8726_external_rom_boot(phy, params);
8688
8689 /*
8690 * Need to call module detected on initialization since the module
8691 * detection triggered by actual module insertion might occur before
8692 * driver is loaded, and when driver is loaded, it reset all
8693 * registers, including the transmitter
8694 */
8695 bnx2x_sfp_module_detection(phy, params);
8696
8697 if (phy->req_line_speed == SPEED_1000) {
8698 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8699 bnx2x_cl45_write(bp, phy,
8700 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8701 bnx2x_cl45_write(bp, phy,
8702 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8703 bnx2x_cl45_write(bp, phy,
8704 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8705 bnx2x_cl45_write(bp, phy,
8706 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8707 0x400);
8708 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8709 (phy->speed_cap_mask &
8710 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8711 ((phy->speed_cap_mask &
8712 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8713 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8714 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8715 /* Set Flow control */
8716 bnx2x_ext_phy_set_pause(params, phy, vars);
8717 bnx2x_cl45_write(bp, phy,
8718 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8719 bnx2x_cl45_write(bp, phy,
8720 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8721 bnx2x_cl45_write(bp, phy,
8722 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8723 bnx2x_cl45_write(bp, phy,
8724 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8725 bnx2x_cl45_write(bp, phy,
8726 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8727 /*
8728 * Enable RX-ALARM control to receive interrupt for 1G speed
8729 * change
8730 */
8731 bnx2x_cl45_write(bp, phy,
8732 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8733 bnx2x_cl45_write(bp, phy,
8734 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8735 0x400);
8736
8737 } else { /* Default 10G. Set only LASI control */
8738 bnx2x_cl45_write(bp, phy,
8739 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8740 }
8741
8742 /* Set TX PreEmphasis if needed */
8743 if ((params->feature_config_flags &
8744 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8745 DP(NETIF_MSG_LINK,
8746 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8747 phy->tx_preemphasis[0],
8748 phy->tx_preemphasis[1]);
8749 bnx2x_cl45_write(bp, phy,
8750 MDIO_PMA_DEVAD,
8751 MDIO_PMA_REG_8726_TX_CTRL1,
8752 phy->tx_preemphasis[0]);
8753
8754 bnx2x_cl45_write(bp, phy,
8755 MDIO_PMA_DEVAD,
8756 MDIO_PMA_REG_8726_TX_CTRL2,
8757 phy->tx_preemphasis[1]);
8758 }
8759
8760 return 0;
8761
8762 }
8763
8764 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8765 struct link_params *params)
8766 {
8767 struct bnx2x *bp = params->bp;
8768 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8769 /* Set serial boot control for external load */
8770 bnx2x_cl45_write(bp, phy,
8771 MDIO_PMA_DEVAD,
8772 MDIO_PMA_REG_GEN_CTRL, 0x0001);
8773 }
8774
8775 /******************************************************************/
8776 /* BCM8727 PHY SECTION */
8777 /******************************************************************/
8778
8779 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8780 struct link_params *params, u8 mode)
8781 {
8782 struct bnx2x *bp = params->bp;
8783 u16 led_mode_bitmask = 0;
8784 u16 gpio_pins_bitmask = 0;
8785 u16 val;
8786 /* Only NOC flavor requires to set the LED specifically */
8787 if (!(phy->flags & FLAGS_NOC))
8788 return;
8789 switch (mode) {
8790 case LED_MODE_FRONT_PANEL_OFF:
8791 case LED_MODE_OFF:
8792 led_mode_bitmask = 0;
8793 gpio_pins_bitmask = 0x03;
8794 break;
8795 case LED_MODE_ON:
8796 led_mode_bitmask = 0;
8797 gpio_pins_bitmask = 0x02;
8798 break;
8799 case LED_MODE_OPER:
8800 led_mode_bitmask = 0x60;
8801 gpio_pins_bitmask = 0x11;
8802 break;
8803 }
8804 bnx2x_cl45_read(bp, phy,
8805 MDIO_PMA_DEVAD,
8806 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8807 &val);
8808 val &= 0xff8f;
8809 val |= led_mode_bitmask;
8810 bnx2x_cl45_write(bp, phy,
8811 MDIO_PMA_DEVAD,
8812 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8813 val);
8814 bnx2x_cl45_read(bp, phy,
8815 MDIO_PMA_DEVAD,
8816 MDIO_PMA_REG_8727_GPIO_CTRL,
8817 &val);
8818 val &= 0xffe0;
8819 val |= gpio_pins_bitmask;
8820 bnx2x_cl45_write(bp, phy,
8821 MDIO_PMA_DEVAD,
8822 MDIO_PMA_REG_8727_GPIO_CTRL,
8823 val);
8824 }
8825 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8826 struct link_params *params) {
8827 u32 swap_val, swap_override;
8828 u8 port;
8829 /*
8830 * The PHY reset is controlled by GPIO 1. Fake the port number
8831 * to cancel the swap done in set_gpio()
8832 */
8833 struct bnx2x *bp = params->bp;
8834 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8835 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8836 port = (swap_val && swap_override) ^ 1;
8837 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8838 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8839 }
8840
8841 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8842 struct link_params *params,
8843 struct link_vars *vars)
8844 {
8845 u32 tx_en_mode;
8846 u16 tmp1, val, mod_abs, tmp2;
8847 u16 rx_alarm_ctrl_val;
8848 u16 lasi_ctrl_val;
8849 struct bnx2x *bp = params->bp;
8850 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8851
8852 bnx2x_wait_reset_complete(bp, phy, params);
8853 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8854 /* Should be 0x6 to enable XS on Tx side. */
8855 lasi_ctrl_val = 0x0006;
8856
8857 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8858 /* enable LASI */
8859 bnx2x_cl45_write(bp, phy,
8860 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8861 rx_alarm_ctrl_val);
8862 bnx2x_cl45_write(bp, phy,
8863 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8864 0);
8865 bnx2x_cl45_write(bp, phy,
8866 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8867
8868 /*
8869 * Initially configure MOD_ABS to interrupt when module is
8870 * presence( bit 8)
8871 */
8872 bnx2x_cl45_read(bp, phy,
8873 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8874 /*
8875 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8876 * When the EDC is off it locks onto a reference clock and avoids
8877 * becoming 'lost'
8878 */
8879 mod_abs &= ~(1<<8);
8880 if (!(phy->flags & FLAGS_NOC))
8881 mod_abs &= ~(1<<9);
8882 bnx2x_cl45_write(bp, phy,
8883 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8884
8885
8886 /* Enable/Disable PHY transmitter output */
8887 bnx2x_set_disable_pmd_transmit(params, phy, 0);
8888
8889 /* Make MOD_ABS give interrupt on change */
8890 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8891 &val);
8892 val |= (1<<12);
8893 if (phy->flags & FLAGS_NOC)
8894 val |= (3<<5);
8895
8896 /*
8897 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8898 * status which reflect SFP+ module over-current
8899 */
8900 if (!(phy->flags & FLAGS_NOC))
8901 val &= 0xff8f; /* Reset bits 4-6 */
8902 bnx2x_cl45_write(bp, phy,
8903 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8904
8905 bnx2x_8727_power_module(bp, phy, 1);
8906
8907 bnx2x_cl45_read(bp, phy,
8908 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8909
8910 bnx2x_cl45_read(bp, phy,
8911 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8912
8913 /* Set option 1G speed */
8914 if (phy->req_line_speed == SPEED_1000) {
8915 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8916 bnx2x_cl45_write(bp, phy,
8917 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8918 bnx2x_cl45_write(bp, phy,
8919 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8920 bnx2x_cl45_read(bp, phy,
8921 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8922 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8923 /*
8924 * Power down the XAUI until link is up in case of dual-media
8925 * and 1G
8926 */
8927 if (DUAL_MEDIA(params)) {
8928 bnx2x_cl45_read(bp, phy,
8929 MDIO_PMA_DEVAD,
8930 MDIO_PMA_REG_8727_PCS_GP, &val);
8931 val |= (3<<10);
8932 bnx2x_cl45_write(bp, phy,
8933 MDIO_PMA_DEVAD,
8934 MDIO_PMA_REG_8727_PCS_GP, val);
8935 }
8936 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8937 ((phy->speed_cap_mask &
8938 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8939 ((phy->speed_cap_mask &
8940 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8941 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8942
8943 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8944 bnx2x_cl45_write(bp, phy,
8945 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8946 bnx2x_cl45_write(bp, phy,
8947 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8948 } else {
8949 /*
8950 * Since the 8727 has only single reset pin, need to set the 10G
8951 * registers although it is default
8952 */
8953 bnx2x_cl45_write(bp, phy,
8954 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8955 0x0020);
8956 bnx2x_cl45_write(bp, phy,
8957 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8958 bnx2x_cl45_write(bp, phy,
8959 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8960 bnx2x_cl45_write(bp, phy,
8961 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8962 0x0008);
8963 }
8964
8965 /*
8966 * Set 2-wire transfer rate of SFP+ module EEPROM
8967 * to 100Khz since some DACs(direct attached cables) do
8968 * not work at 400Khz.
8969 */
8970 bnx2x_cl45_write(bp, phy,
8971 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8972 0xa001);
8973
8974 /* Set TX PreEmphasis if needed */
8975 if ((params->feature_config_flags &
8976 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8977 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8978 phy->tx_preemphasis[0],
8979 phy->tx_preemphasis[1]);
8980 bnx2x_cl45_write(bp, phy,
8981 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8982 phy->tx_preemphasis[0]);
8983
8984 bnx2x_cl45_write(bp, phy,
8985 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8986 phy->tx_preemphasis[1]);
8987 }
8988
8989 /*
8990 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8991 * power mode, if TX Laser is disabled
8992 */
8993 tx_en_mode = REG_RD(bp, params->shmem_base +
8994 offsetof(struct shmem_region,
8995 dev_info.port_hw_config[params->port].sfp_ctrl))
8996 & PORT_HW_CFG_TX_LASER_MASK;
8997
8998 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8999
9000 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9001 bnx2x_cl45_read(bp, phy,
9002 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9003 tmp2 |= 0x1000;
9004 tmp2 &= 0xFFEF;
9005 bnx2x_cl45_write(bp, phy,
9006 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9007 }
9008
9009 return 0;
9010 }
9011
9012 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9013 struct link_params *params)
9014 {
9015 struct bnx2x *bp = params->bp;
9016 u16 mod_abs, rx_alarm_status;
9017 u32 val = REG_RD(bp, params->shmem_base +
9018 offsetof(struct shmem_region, dev_info.
9019 port_feature_config[params->port].
9020 config));
9021 bnx2x_cl45_read(bp, phy,
9022 MDIO_PMA_DEVAD,
9023 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9024 if (mod_abs & (1<<8)) {
9025
9026 /* Module is absent */
9027 DP(NETIF_MSG_LINK,
9028 "MOD_ABS indication show module is absent\n");
9029 phy->media_type = ETH_PHY_NOT_PRESENT;
9030 /*
9031 * 1. Set mod_abs to detect next module
9032 * presence event
9033 * 2. Set EDC off by setting OPTXLOS signal input to low
9034 * (bit 9).
9035 * When the EDC is off it locks onto a reference clock and
9036 * avoids becoming 'lost'.
9037 */
9038 mod_abs &= ~(1<<8);
9039 if (!(phy->flags & FLAGS_NOC))
9040 mod_abs &= ~(1<<9);
9041 bnx2x_cl45_write(bp, phy,
9042 MDIO_PMA_DEVAD,
9043 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9044
9045 /*
9046 * Clear RX alarm since it stays up as long as
9047 * the mod_abs wasn't changed
9048 */
9049 bnx2x_cl45_read(bp, phy,
9050 MDIO_PMA_DEVAD,
9051 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9052
9053 } else {
9054 /* Module is present */
9055 DP(NETIF_MSG_LINK,
9056 "MOD_ABS indication show module is present\n");
9057 /*
9058 * First disable transmitter, and if the module is ok, the
9059 * module_detection will enable it
9060 * 1. Set mod_abs to detect next module absent event ( bit 8)
9061 * 2. Restore the default polarity of the OPRXLOS signal and
9062 * this signal will then correctly indicate the presence or
9063 * absence of the Rx signal. (bit 9)
9064 */
9065 mod_abs |= (1<<8);
9066 if (!(phy->flags & FLAGS_NOC))
9067 mod_abs |= (1<<9);
9068 bnx2x_cl45_write(bp, phy,
9069 MDIO_PMA_DEVAD,
9070 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9071
9072 /*
9073 * Clear RX alarm since it stays up as long as the mod_abs
9074 * wasn't changed. This is need to be done before calling the
9075 * module detection, otherwise it will clear* the link update
9076 * alarm
9077 */
9078 bnx2x_cl45_read(bp, phy,
9079 MDIO_PMA_DEVAD,
9080 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9081
9082
9083 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9084 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9085 bnx2x_sfp_set_transmitter(params, phy, 0);
9086
9087 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9088 bnx2x_sfp_module_detection(phy, params);
9089 else
9090 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9091 }
9092
9093 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9094 rx_alarm_status);
9095 /* No need to check link status in case of module plugged in/out */
9096 }
9097
9098 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9099 struct link_params *params,
9100 struct link_vars *vars)
9101
9102 {
9103 struct bnx2x *bp = params->bp;
9104 u8 link_up = 0, oc_port = params->port;
9105 u16 link_status = 0;
9106 u16 rx_alarm_status, lasi_ctrl, val1;
9107
9108 /* If PHY is not initialized, do not check link status */
9109 bnx2x_cl45_read(bp, phy,
9110 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9111 &lasi_ctrl);
9112 if (!lasi_ctrl)
9113 return 0;
9114
9115 /* Check the LASI on Rx */
9116 bnx2x_cl45_read(bp, phy,
9117 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9118 &rx_alarm_status);
9119 vars->line_speed = 0;
9120 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9121
9122 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9123 MDIO_PMA_LASI_TXCTRL);
9124
9125 bnx2x_cl45_read(bp, phy,
9126 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9127
9128 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9129
9130 /* Clear MSG-OUT */
9131 bnx2x_cl45_read(bp, phy,
9132 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9133
9134 /*
9135 * If a module is present and there is need to check
9136 * for over current
9137 */
9138 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9139 /* Check over-current using 8727 GPIO0 input*/
9140 bnx2x_cl45_read(bp, phy,
9141 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9142 &val1);
9143
9144 if ((val1 & (1<<8)) == 0) {
9145 if (!CHIP_IS_E1x(bp))
9146 oc_port = BP_PATH(bp) + (params->port << 1);
9147 DP(NETIF_MSG_LINK,
9148 "8727 Power fault has been detected on port %d\n",
9149 oc_port);
9150 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9151 "been detected and the power to "
9152 "that SFP+ module has been removed "
9153 "to prevent failure of the card. "
9154 "Please remove the SFP+ module and "
9155 "restart the system to clear this "
9156 "error.\n",
9157 oc_port);
9158 /* Disable all RX_ALARMs except for mod_abs */
9159 bnx2x_cl45_write(bp, phy,
9160 MDIO_PMA_DEVAD,
9161 MDIO_PMA_LASI_RXCTRL, (1<<5));
9162
9163 bnx2x_cl45_read(bp, phy,
9164 MDIO_PMA_DEVAD,
9165 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9166 /* Wait for module_absent_event */
9167 val1 |= (1<<8);
9168 bnx2x_cl45_write(bp, phy,
9169 MDIO_PMA_DEVAD,
9170 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9171 /* Clear RX alarm */
9172 bnx2x_cl45_read(bp, phy,
9173 MDIO_PMA_DEVAD,
9174 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9175 return 0;
9176 }
9177 } /* Over current check */
9178
9179 /* When module absent bit is set, check module */
9180 if (rx_alarm_status & (1<<5)) {
9181 bnx2x_8727_handle_mod_abs(phy, params);
9182 /* Enable all mod_abs and link detection bits */
9183 bnx2x_cl45_write(bp, phy,
9184 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9185 ((1<<5) | (1<<2)));
9186 }
9187 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
9188 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
9189 /* If transmitter is disabled, ignore false link up indication */
9190 bnx2x_cl45_read(bp, phy,
9191 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9192 if (val1 & (1<<15)) {
9193 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9194 return 0;
9195 }
9196
9197 bnx2x_cl45_read(bp, phy,
9198 MDIO_PMA_DEVAD,
9199 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9200
9201 /*
9202 * Bits 0..2 --> speed detected,
9203 * Bits 13..15--> link is down
9204 */
9205 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9206 link_up = 1;
9207 vars->line_speed = SPEED_10000;
9208 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9209 params->port);
9210 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9211 link_up = 1;
9212 vars->line_speed = SPEED_1000;
9213 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9214 params->port);
9215 } else {
9216 link_up = 0;
9217 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9218 params->port);
9219 }
9220
9221 /* Capture 10G link fault. */
9222 if (vars->line_speed == SPEED_10000) {
9223 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9224 MDIO_PMA_LASI_TXSTAT, &val1);
9225
9226 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9227 MDIO_PMA_LASI_TXSTAT, &val1);
9228
9229 if (val1 & (1<<0)) {
9230 vars->fault_detected = 1;
9231 }
9232 }
9233
9234 if (link_up) {
9235 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9236 vars->duplex = DUPLEX_FULL;
9237 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9238 }
9239
9240 if ((DUAL_MEDIA(params)) &&
9241 (phy->req_line_speed == SPEED_1000)) {
9242 bnx2x_cl45_read(bp, phy,
9243 MDIO_PMA_DEVAD,
9244 MDIO_PMA_REG_8727_PCS_GP, &val1);
9245 /*
9246 * In case of dual-media board and 1G, power up the XAUI side,
9247 * otherwise power it down. For 10G it is done automatically
9248 */
9249 if (link_up)
9250 val1 &= ~(3<<10);
9251 else
9252 val1 |= (3<<10);
9253 bnx2x_cl45_write(bp, phy,
9254 MDIO_PMA_DEVAD,
9255 MDIO_PMA_REG_8727_PCS_GP, val1);
9256 }
9257 return link_up;
9258 }
9259
9260 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9261 struct link_params *params)
9262 {
9263 struct bnx2x *bp = params->bp;
9264
9265 /* Enable/Disable PHY transmitter output */
9266 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9267
9268 /* Disable Transmitter */
9269 bnx2x_sfp_set_transmitter(params, phy, 0);
9270 /* Clear LASI */
9271 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9272
9273 }
9274
9275 /******************************************************************/
9276 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9277 /******************************************************************/
9278 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9279 struct bnx2x *bp,
9280 u8 port)
9281 {
9282 u16 val, fw_ver1, fw_ver2, cnt;
9283
9284 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9285 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9286 bnx2x_save_spirom_version(bp, port,
9287 ((fw_ver1 & 0xf000)>>5) | (fw_ver1 & 0x7f),
9288 phy->ver_addr);
9289 } else {
9290 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9291 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9292 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9293 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9294 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9295 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9296 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9297
9298 for (cnt = 0; cnt < 100; cnt++) {
9299 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9300 if (val & 1)
9301 break;
9302 udelay(5);
9303 }
9304 if (cnt == 100) {
9305 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9306 "phy fw version(1)\n");
9307 bnx2x_save_spirom_version(bp, port, 0,
9308 phy->ver_addr);
9309 return;
9310 }
9311
9312
9313 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9314 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9315 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9316 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9317 for (cnt = 0; cnt < 100; cnt++) {
9318 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9319 if (val & 1)
9320 break;
9321 udelay(5);
9322 }
9323 if (cnt == 100) {
9324 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9325 "version(2)\n");
9326 bnx2x_save_spirom_version(bp, port, 0,
9327 phy->ver_addr);
9328 return;
9329 }
9330
9331 /* lower 16 bits of the register SPI_FW_STATUS */
9332 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9333 /* upper 16 bits of register SPI_FW_STATUS */
9334 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9335
9336 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9337 phy->ver_addr);
9338 }
9339
9340 }
9341 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9342 struct bnx2x_phy *phy)
9343 {
9344 u16 val, offset;
9345
9346 /* PHYC_CTL_LED_CTL */
9347 bnx2x_cl45_read(bp, phy,
9348 MDIO_PMA_DEVAD,
9349 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9350 val &= 0xFE00;
9351 val |= 0x0092;
9352
9353 bnx2x_cl45_write(bp, phy,
9354 MDIO_PMA_DEVAD,
9355 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9356
9357 bnx2x_cl45_write(bp, phy,
9358 MDIO_PMA_DEVAD,
9359 MDIO_PMA_REG_8481_LED1_MASK,
9360 0x80);
9361
9362 bnx2x_cl45_write(bp, phy,
9363 MDIO_PMA_DEVAD,
9364 MDIO_PMA_REG_8481_LED2_MASK,
9365 0x18);
9366
9367 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9368 bnx2x_cl45_write(bp, phy,
9369 MDIO_PMA_DEVAD,
9370 MDIO_PMA_REG_8481_LED3_MASK,
9371 0x0006);
9372
9373 /* Select the closest activity blink rate to that in 10/100/1000 */
9374 bnx2x_cl45_write(bp, phy,
9375 MDIO_PMA_DEVAD,
9376 MDIO_PMA_REG_8481_LED3_BLINK,
9377 0);
9378
9379 /* Configure the blink rate to ~15.9 Hz */
9380 bnx2x_cl45_write(bp, phy,
9381 MDIO_PMA_DEVAD,
9382 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9383 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9384
9385 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9386 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9387 else
9388 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9389
9390 bnx2x_cl45_read(bp, phy,
9391 MDIO_PMA_DEVAD, offset, &val);
9392 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9393 bnx2x_cl45_write(bp, phy,
9394 MDIO_PMA_DEVAD, offset, val);
9395
9396 /* 'Interrupt Mask' */
9397 bnx2x_cl45_write(bp, phy,
9398 MDIO_AN_DEVAD,
9399 0xFFFB, 0xFFFD);
9400 }
9401
9402 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9403 struct link_params *params,
9404 struct link_vars *vars)
9405 {
9406 struct bnx2x *bp = params->bp;
9407 u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val;
9408 u16 tmp_req_line_speed;
9409
9410 tmp_req_line_speed = phy->req_line_speed;
9411 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9412 if (phy->req_line_speed == SPEED_10000)
9413 phy->req_line_speed = SPEED_AUTO_NEG;
9414 } else {
9415 /* Save spirom version */
9416 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9417 }
9418 /*
9419 * This phy uses the NIG latch mechanism since link indication
9420 * arrives through its LED4 and not via its LASI signal, so we
9421 * get steady signal instead of clear on read
9422 */
9423 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9424 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9425
9426 bnx2x_cl45_write(bp, phy,
9427 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9428
9429 bnx2x_848xx_set_led(bp, phy);
9430
9431 /* set 1000 speed advertisement */
9432 bnx2x_cl45_read(bp, phy,
9433 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9434 &an_1000_val);
9435
9436 bnx2x_ext_phy_set_pause(params, phy, vars);
9437 bnx2x_cl45_read(bp, phy,
9438 MDIO_AN_DEVAD,
9439 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9440 &an_10_100_val);
9441 bnx2x_cl45_read(bp, phy,
9442 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9443 &autoneg_val);
9444 /* Disable forced speed */
9445 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9446 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9447
9448 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9449 (phy->speed_cap_mask &
9450 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9451 (phy->req_line_speed == SPEED_1000)) {
9452 an_1000_val |= (1<<8);
9453 autoneg_val |= (1<<9 | 1<<12);
9454 if (phy->req_duplex == DUPLEX_FULL)
9455 an_1000_val |= (1<<9);
9456 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9457 } else
9458 an_1000_val &= ~((1<<8) | (1<<9));
9459
9460 bnx2x_cl45_write(bp, phy,
9461 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9462 an_1000_val);
9463
9464 /* set 100 speed advertisement */
9465 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9466 (phy->speed_cap_mask &
9467 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9468 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9469 an_10_100_val |= (1<<7);
9470 /* Enable autoneg and restart autoneg for legacy speeds */
9471 autoneg_val |= (1<<9 | 1<<12);
9472
9473 if (phy->req_duplex == DUPLEX_FULL)
9474 an_10_100_val |= (1<<8);
9475 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9476 }
9477 /* set 10 speed advertisement */
9478 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9479 (phy->speed_cap_mask &
9480 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9481 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9482 (phy->supported &
9483 (SUPPORTED_10baseT_Half |
9484 SUPPORTED_10baseT_Full)))) {
9485 an_10_100_val |= (1<<5);
9486 autoneg_val |= (1<<9 | 1<<12);
9487 if (phy->req_duplex == DUPLEX_FULL)
9488 an_10_100_val |= (1<<6);
9489 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9490 }
9491
9492 /* Only 10/100 are allowed to work in FORCE mode */
9493 if ((phy->req_line_speed == SPEED_100) &&
9494 (phy->supported &
9495 (SUPPORTED_100baseT_Half |
9496 SUPPORTED_100baseT_Full))) {
9497 autoneg_val |= (1<<13);
9498 /* Enabled AUTO-MDIX when autoneg is disabled */
9499 bnx2x_cl45_write(bp, phy,
9500 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9501 (1<<15 | 1<<9 | 7<<0));
9502 /* The PHY needs this set even for forced link. */
9503 an_10_100_val |= (1<<8) | (1<<7);
9504 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9505 }
9506 if ((phy->req_line_speed == SPEED_10) &&
9507 (phy->supported &
9508 (SUPPORTED_10baseT_Half |
9509 SUPPORTED_10baseT_Full))) {
9510 /* Enabled AUTO-MDIX when autoneg is disabled */
9511 bnx2x_cl45_write(bp, phy,
9512 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9513 (1<<15 | 1<<9 | 7<<0));
9514 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9515 }
9516
9517 bnx2x_cl45_write(bp, phy,
9518 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9519 an_10_100_val);
9520
9521 if (phy->req_duplex == DUPLEX_FULL)
9522 autoneg_val |= (1<<8);
9523
9524 /*
9525 * Always write this if this is not 84833.
9526 * For 84833, write it only when it's a forced speed.
9527 */
9528 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9529 ((autoneg_val & (1<<12)) == 0))
9530 bnx2x_cl45_write(bp, phy,
9531 MDIO_AN_DEVAD,
9532 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9533
9534 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9535 (phy->speed_cap_mask &
9536 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9537 (phy->req_line_speed == SPEED_10000)) {
9538 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9539 /* Restart autoneg for 10G*/
9540
9541 bnx2x_cl45_read(bp, phy,
9542 MDIO_AN_DEVAD,
9543 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9544 &an_10g_val);
9545 bnx2x_cl45_write(bp, phy,
9546 MDIO_AN_DEVAD,
9547 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9548 an_10g_val | 0x1000);
9549 bnx2x_cl45_write(bp, phy,
9550 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9551 0x3200);
9552 } else
9553 bnx2x_cl45_write(bp, phy,
9554 MDIO_AN_DEVAD,
9555 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9556 1);
9557
9558 phy->req_line_speed = tmp_req_line_speed;
9559
9560 return 0;
9561 }
9562
9563 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9564 struct link_params *params,
9565 struct link_vars *vars)
9566 {
9567 struct bnx2x *bp = params->bp;
9568 /* Restore normal power mode*/
9569 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9570 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9571
9572 /* HW reset */
9573 bnx2x_ext_phy_hw_reset(bp, params->port);
9574 bnx2x_wait_reset_complete(bp, phy, params);
9575
9576 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9577 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9578 }
9579
9580 #define PHY84833_CMDHDLR_WAIT 300
9581 #define PHY84833_CMDHDLR_MAX_ARGS 5
9582 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9583 struct link_params *params,
9584 u16 fw_cmd,
9585 u16 cmd_args[])
9586 {
9587 u32 idx;
9588 u16 val;
9589 struct bnx2x *bp = params->bp;
9590 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9591 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9592 MDIO_84833_CMD_HDLR_STATUS,
9593 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9594 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9595 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9596 MDIO_84833_CMD_HDLR_STATUS, &val);
9597 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9598 break;
9599 msleep(1);
9600 }
9601 if (idx >= PHY84833_CMDHDLR_WAIT) {
9602 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9603 return -EINVAL;
9604 }
9605
9606 /* Prepare argument(s) and issue command */
9607 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9608 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9609 MDIO_84833_CMD_HDLR_DATA1 + idx,
9610 cmd_args[idx]);
9611 }
9612 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9613 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9614 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9615 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9616 MDIO_84833_CMD_HDLR_STATUS, &val);
9617 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9618 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9619 break;
9620 msleep(1);
9621 }
9622 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9623 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9624 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9625 return -EINVAL;
9626 }
9627 /* Gather returning data */
9628 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9629 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9630 MDIO_84833_CMD_HDLR_DATA1 + idx,
9631 &cmd_args[idx]);
9632 }
9633 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9634 MDIO_84833_CMD_HDLR_STATUS,
9635 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9636 return 0;
9637 }
9638
9639
9640 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9641 struct link_params *params,
9642 struct link_vars *vars)
9643 {
9644 u32 pair_swap;
9645 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9646 int status;
9647 struct bnx2x *bp = params->bp;
9648
9649 /* Check for configuration. */
9650 pair_swap = REG_RD(bp, params->shmem_base +
9651 offsetof(struct shmem_region,
9652 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9653 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9654
9655 if (pair_swap == 0)
9656 return 0;
9657
9658 /* Only the second argument is used for this command */
9659 data[1] = (u16)pair_swap;
9660
9661 status = bnx2x_84833_cmd_hdlr(phy, params,
9662 PHY84833_CMD_SET_PAIR_SWAP, data);
9663 if (status == 0)
9664 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9665
9666 return status;
9667 }
9668
9669 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9670 u32 shmem_base_path[],
9671 u32 chip_id)
9672 {
9673 u32 reset_pin[2];
9674 u32 idx;
9675 u8 reset_gpios;
9676 if (CHIP_IS_E3(bp)) {
9677 /* Assume that these will be GPIOs, not EPIOs. */
9678 for (idx = 0; idx < 2; idx++) {
9679 /* Map config param to register bit. */
9680 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9681 offsetof(struct shmem_region,
9682 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9683 reset_pin[idx] = (reset_pin[idx] &
9684 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9685 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9686 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9687 reset_pin[idx] = (1 << reset_pin[idx]);
9688 }
9689 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9690 } else {
9691 /* E2, look from diff place of shmem. */
9692 for (idx = 0; idx < 2; idx++) {
9693 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9694 offsetof(struct shmem_region,
9695 dev_info.port_hw_config[0].default_cfg));
9696 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9697 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9698 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9699 reset_pin[idx] = (1 << reset_pin[idx]);
9700 }
9701 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9702 }
9703
9704 return reset_gpios;
9705 }
9706
9707 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9708 struct link_params *params)
9709 {
9710 struct bnx2x *bp = params->bp;
9711 u8 reset_gpios;
9712 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9713 offsetof(struct shmem2_region,
9714 other_shmem_base_addr));
9715
9716 u32 shmem_base_path[2];
9717 shmem_base_path[0] = params->shmem_base;
9718 shmem_base_path[1] = other_shmem_base_addr;
9719
9720 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9721 params->chip_id);
9722
9723 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9724 udelay(10);
9725 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9726 reset_gpios);
9727
9728 return 0;
9729 }
9730
9731 #define PHY84833_CONSTANT_LATENCY 1193
9732 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9733 struct link_params *params,
9734 struct link_vars *vars)
9735 {
9736 struct bnx2x *bp = params->bp;
9737 u8 port, initialize = 1;
9738 u16 val;
9739 u32 actual_phy_selection, cms_enable;
9740 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9741 int rc = 0;
9742
9743 msleep(1);
9744
9745 if (!(CHIP_IS_E1(bp)))
9746 port = BP_PATH(bp);
9747 else
9748 port = params->port;
9749
9750 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9751 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9752 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9753 port);
9754 } else {
9755 /* MDIO reset */
9756 bnx2x_cl45_write(bp, phy,
9757 MDIO_PMA_DEVAD,
9758 MDIO_PMA_REG_CTRL, 0x8000);
9759 }
9760
9761 bnx2x_wait_reset_complete(bp, phy, params);
9762
9763 /* Wait for GPHY to come out of reset */
9764 msleep(50);
9765 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9766 /*
9767 * BCM84823 requires that XGXS links up first @ 10G for normal
9768 * behavior.
9769 */
9770 u16 temp;
9771 temp = vars->line_speed;
9772 vars->line_speed = SPEED_10000;
9773 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9774 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9775 vars->line_speed = temp;
9776 }
9777
9778 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9779 MDIO_CTL_REG_84823_MEDIA, &val);
9780 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9781 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9782 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9783 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9784 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9785
9786 if (CHIP_IS_E3(bp)) {
9787 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9788 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9789 } else {
9790 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9791 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9792 }
9793
9794 actual_phy_selection = bnx2x_phy_selection(params);
9795
9796 switch (actual_phy_selection) {
9797 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9798 /* Do nothing. Essentially this is like the priority copper */
9799 break;
9800 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9801 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9802 break;
9803 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9804 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9805 break;
9806 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9807 /* Do nothing here. The first PHY won't be initialized at all */
9808 break;
9809 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9810 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9811 initialize = 0;
9812 break;
9813 }
9814 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9815 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9816
9817 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9818 MDIO_CTL_REG_84823_MEDIA, val);
9819 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9820 params->multi_phy_config, val);
9821
9822 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9823 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9824
9825 /* Keep AutogrEEEn disabled. */
9826 cmd_args[0] = 0x0;
9827 cmd_args[1] = 0x0;
9828 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9829 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9830 rc = bnx2x_84833_cmd_hdlr(phy, params,
9831 PHY84833_CMD_SET_EEE_MODE, cmd_args);
9832 if (rc != 0)
9833 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
9834 }
9835 if (initialize)
9836 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9837 else
9838 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9839 /* 84833 PHY has a better feature and doesn't need to support this. */
9840 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9841 cms_enable = REG_RD(bp, params->shmem_base +
9842 offsetof(struct shmem_region,
9843 dev_info.port_hw_config[params->port].default_cfg)) &
9844 PORT_HW_CFG_ENABLE_CMS_MASK;
9845
9846 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9847 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9848 if (cms_enable)
9849 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9850 else
9851 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9852 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9853 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9854 }
9855
9856 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9857 /* Bring PHY out of super isolate mode as the final step. */
9858 bnx2x_cl45_read(bp, phy,
9859 MDIO_CTL_DEVAD,
9860 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9861 val &= ~MDIO_84833_SUPER_ISOLATE;
9862 bnx2x_cl45_write(bp, phy,
9863 MDIO_CTL_DEVAD,
9864 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9865 }
9866 return rc;
9867 }
9868
9869 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9870 struct link_params *params,
9871 struct link_vars *vars)
9872 {
9873 struct bnx2x *bp = params->bp;
9874 u16 val, val1, val2;
9875 u8 link_up = 0;
9876
9877
9878 /* Check 10G-BaseT link status */
9879 /* Check PMD signal ok */
9880 bnx2x_cl45_read(bp, phy,
9881 MDIO_AN_DEVAD, 0xFFFA, &val1);
9882 bnx2x_cl45_read(bp, phy,
9883 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9884 &val2);
9885 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9886
9887 /* Check link 10G */
9888 if (val2 & (1<<11)) {
9889 vars->line_speed = SPEED_10000;
9890 vars->duplex = DUPLEX_FULL;
9891 link_up = 1;
9892 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9893 } else { /* Check Legacy speed link */
9894 u16 legacy_status, legacy_speed;
9895
9896 /* Enable expansion register 0x42 (Operation mode status) */
9897 bnx2x_cl45_write(bp, phy,
9898 MDIO_AN_DEVAD,
9899 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9900
9901 /* Get legacy speed operation status */
9902 bnx2x_cl45_read(bp, phy,
9903 MDIO_AN_DEVAD,
9904 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9905 &legacy_status);
9906
9907 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
9908 legacy_status);
9909 link_up = ((legacy_status & (1<<11)) == (1<<11));
9910 if (link_up) {
9911 legacy_speed = (legacy_status & (3<<9));
9912 if (legacy_speed == (0<<9))
9913 vars->line_speed = SPEED_10;
9914 else if (legacy_speed == (1<<9))
9915 vars->line_speed = SPEED_100;
9916 else if (legacy_speed == (2<<9))
9917 vars->line_speed = SPEED_1000;
9918 else /* Should not happen */
9919 vars->line_speed = 0;
9920
9921 if (legacy_status & (1<<8))
9922 vars->duplex = DUPLEX_FULL;
9923 else
9924 vars->duplex = DUPLEX_HALF;
9925
9926 DP(NETIF_MSG_LINK,
9927 "Link is up in %dMbps, is_duplex_full= %d\n",
9928 vars->line_speed,
9929 (vars->duplex == DUPLEX_FULL));
9930 /* Check legacy speed AN resolution */
9931 bnx2x_cl45_read(bp, phy,
9932 MDIO_AN_DEVAD,
9933 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9934 &val);
9935 if (val & (1<<5))
9936 vars->link_status |=
9937 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9938 bnx2x_cl45_read(bp, phy,
9939 MDIO_AN_DEVAD,
9940 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9941 &val);
9942 if ((val & (1<<0)) == 0)
9943 vars->link_status |=
9944 LINK_STATUS_PARALLEL_DETECTION_USED;
9945 }
9946 }
9947 if (link_up) {
9948 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9949 vars->line_speed);
9950 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9951 }
9952
9953 return link_up;
9954 }
9955
9956
9957 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9958 {
9959 int status = 0;
9960 u32 spirom_ver;
9961 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9962 status = bnx2x_format_ver(spirom_ver, str, len);
9963 return status;
9964 }
9965
9966 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9967 struct link_params *params)
9968 {
9969 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9970 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9971 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9972 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9973 }
9974
9975 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9976 struct link_params *params)
9977 {
9978 bnx2x_cl45_write(params->bp, phy,
9979 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9980 bnx2x_cl45_write(params->bp, phy,
9981 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9982 }
9983
9984 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9985 struct link_params *params)
9986 {
9987 struct bnx2x *bp = params->bp;
9988 u8 port;
9989 u16 val16;
9990
9991 if (!(CHIP_IS_E1(bp)))
9992 port = BP_PATH(bp);
9993 else
9994 port = params->port;
9995
9996 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9997 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9998 MISC_REGISTERS_GPIO_OUTPUT_LOW,
9999 port);
10000 } else {
10001 bnx2x_cl45_read(bp, phy,
10002 MDIO_CTL_DEVAD,
10003 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10004 val16 |= MDIO_84833_SUPER_ISOLATE;
10005 bnx2x_cl45_write(bp, phy,
10006 MDIO_CTL_DEVAD,
10007 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10008 }
10009 }
10010
10011 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10012 struct link_params *params, u8 mode)
10013 {
10014 struct bnx2x *bp = params->bp;
10015 u16 val;
10016 u8 port;
10017
10018 if (!(CHIP_IS_E1(bp)))
10019 port = BP_PATH(bp);
10020 else
10021 port = params->port;
10022
10023 switch (mode) {
10024 case LED_MODE_OFF:
10025
10026 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10027
10028 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10029 SHARED_HW_CFG_LED_EXTPHY1) {
10030
10031 /* Set LED masks */
10032 bnx2x_cl45_write(bp, phy,
10033 MDIO_PMA_DEVAD,
10034 MDIO_PMA_REG_8481_LED1_MASK,
10035 0x0);
10036
10037 bnx2x_cl45_write(bp, phy,
10038 MDIO_PMA_DEVAD,
10039 MDIO_PMA_REG_8481_LED2_MASK,
10040 0x0);
10041
10042 bnx2x_cl45_write(bp, phy,
10043 MDIO_PMA_DEVAD,
10044 MDIO_PMA_REG_8481_LED3_MASK,
10045 0x0);
10046
10047 bnx2x_cl45_write(bp, phy,
10048 MDIO_PMA_DEVAD,
10049 MDIO_PMA_REG_8481_LED5_MASK,
10050 0x0);
10051
10052 } else {
10053 bnx2x_cl45_write(bp, phy,
10054 MDIO_PMA_DEVAD,
10055 MDIO_PMA_REG_8481_LED1_MASK,
10056 0x0);
10057 }
10058 break;
10059 case LED_MODE_FRONT_PANEL_OFF:
10060
10061 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10062 port);
10063
10064 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10065 SHARED_HW_CFG_LED_EXTPHY1) {
10066
10067 /* Set LED masks */
10068 bnx2x_cl45_write(bp, phy,
10069 MDIO_PMA_DEVAD,
10070 MDIO_PMA_REG_8481_LED1_MASK,
10071 0x0);
10072
10073 bnx2x_cl45_write(bp, phy,
10074 MDIO_PMA_DEVAD,
10075 MDIO_PMA_REG_8481_LED2_MASK,
10076 0x0);
10077
10078 bnx2x_cl45_write(bp, phy,
10079 MDIO_PMA_DEVAD,
10080 MDIO_PMA_REG_8481_LED3_MASK,
10081 0x0);
10082
10083 bnx2x_cl45_write(bp, phy,
10084 MDIO_PMA_DEVAD,
10085 MDIO_PMA_REG_8481_LED5_MASK,
10086 0x20);
10087
10088 } else {
10089 bnx2x_cl45_write(bp, phy,
10090 MDIO_PMA_DEVAD,
10091 MDIO_PMA_REG_8481_LED1_MASK,
10092 0x0);
10093 }
10094 break;
10095 case LED_MODE_ON:
10096
10097 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10098
10099 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10100 SHARED_HW_CFG_LED_EXTPHY1) {
10101 /* Set control reg */
10102 bnx2x_cl45_read(bp, phy,
10103 MDIO_PMA_DEVAD,
10104 MDIO_PMA_REG_8481_LINK_SIGNAL,
10105 &val);
10106 val &= 0x8000;
10107 val |= 0x2492;
10108
10109 bnx2x_cl45_write(bp, phy,
10110 MDIO_PMA_DEVAD,
10111 MDIO_PMA_REG_8481_LINK_SIGNAL,
10112 val);
10113
10114 /* Set LED masks */
10115 bnx2x_cl45_write(bp, phy,
10116 MDIO_PMA_DEVAD,
10117 MDIO_PMA_REG_8481_LED1_MASK,
10118 0x0);
10119
10120 bnx2x_cl45_write(bp, phy,
10121 MDIO_PMA_DEVAD,
10122 MDIO_PMA_REG_8481_LED2_MASK,
10123 0x20);
10124
10125 bnx2x_cl45_write(bp, phy,
10126 MDIO_PMA_DEVAD,
10127 MDIO_PMA_REG_8481_LED3_MASK,
10128 0x20);
10129
10130 bnx2x_cl45_write(bp, phy,
10131 MDIO_PMA_DEVAD,
10132 MDIO_PMA_REG_8481_LED5_MASK,
10133 0x0);
10134 } else {
10135 bnx2x_cl45_write(bp, phy,
10136 MDIO_PMA_DEVAD,
10137 MDIO_PMA_REG_8481_LED1_MASK,
10138 0x20);
10139 }
10140 break;
10141
10142 case LED_MODE_OPER:
10143
10144 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10145
10146 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10147 SHARED_HW_CFG_LED_EXTPHY1) {
10148
10149 /* Set control reg */
10150 bnx2x_cl45_read(bp, phy,
10151 MDIO_PMA_DEVAD,
10152 MDIO_PMA_REG_8481_LINK_SIGNAL,
10153 &val);
10154
10155 if (!((val &
10156 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10157 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10158 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10159 bnx2x_cl45_write(bp, phy,
10160 MDIO_PMA_DEVAD,
10161 MDIO_PMA_REG_8481_LINK_SIGNAL,
10162 0xa492);
10163 }
10164
10165 /* Set LED masks */
10166 bnx2x_cl45_write(bp, phy,
10167 MDIO_PMA_DEVAD,
10168 MDIO_PMA_REG_8481_LED1_MASK,
10169 0x10);
10170
10171 bnx2x_cl45_write(bp, phy,
10172 MDIO_PMA_DEVAD,
10173 MDIO_PMA_REG_8481_LED2_MASK,
10174 0x80);
10175
10176 bnx2x_cl45_write(bp, phy,
10177 MDIO_PMA_DEVAD,
10178 MDIO_PMA_REG_8481_LED3_MASK,
10179 0x98);
10180
10181 bnx2x_cl45_write(bp, phy,
10182 MDIO_PMA_DEVAD,
10183 MDIO_PMA_REG_8481_LED5_MASK,
10184 0x40);
10185
10186 } else {
10187 bnx2x_cl45_write(bp, phy,
10188 MDIO_PMA_DEVAD,
10189 MDIO_PMA_REG_8481_LED1_MASK,
10190 0x80);
10191
10192 /* Tell LED3 to blink on source */
10193 bnx2x_cl45_read(bp, phy,
10194 MDIO_PMA_DEVAD,
10195 MDIO_PMA_REG_8481_LINK_SIGNAL,
10196 &val);
10197 val &= ~(7<<6);
10198 val |= (1<<6); /* A83B[8:6]= 1 */
10199 bnx2x_cl45_write(bp, phy,
10200 MDIO_PMA_DEVAD,
10201 MDIO_PMA_REG_8481_LINK_SIGNAL,
10202 val);
10203 }
10204 break;
10205 }
10206
10207 /*
10208 * This is a workaround for E3+84833 until autoneg
10209 * restart is fixed in f/w
10210 */
10211 if (CHIP_IS_E3(bp)) {
10212 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10213 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10214 }
10215 }
10216
10217 /******************************************************************/
10218 /* 54618SE PHY SECTION */
10219 /******************************************************************/
10220 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10221 struct link_params *params,
10222 struct link_vars *vars)
10223 {
10224 struct bnx2x *bp = params->bp;
10225 u8 port;
10226 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10227 u32 cfg_pin;
10228
10229 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10230 usleep_range(1000, 1000);
10231
10232 /*
10233 * This works with E3 only, no need to check the chip
10234 * before determining the port.
10235 */
10236 port = params->port;
10237
10238 cfg_pin = (REG_RD(bp, params->shmem_base +
10239 offsetof(struct shmem_region,
10240 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10241 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10242 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10243
10244 /* Drive pin high to bring the GPHY out of reset. */
10245 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10246
10247 /* wait for GPHY to reset */
10248 msleep(50);
10249
10250 /* reset phy */
10251 bnx2x_cl22_write(bp, phy,
10252 MDIO_PMA_REG_CTRL, 0x8000);
10253 bnx2x_wait_reset_complete(bp, phy, params);
10254
10255 /*wait for GPHY to reset */
10256 msleep(50);
10257
10258 /* Configure LED4: set to INTR (0x6). */
10259 /* Accessing shadow register 0xe. */
10260 bnx2x_cl22_write(bp, phy,
10261 MDIO_REG_GPHY_SHADOW,
10262 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10263 bnx2x_cl22_read(bp, phy,
10264 MDIO_REG_GPHY_SHADOW,
10265 &temp);
10266 temp &= ~(0xf << 4);
10267 temp |= (0x6 << 4);
10268 bnx2x_cl22_write(bp, phy,
10269 MDIO_REG_GPHY_SHADOW,
10270 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10271 /* Configure INTR based on link status change. */
10272 bnx2x_cl22_write(bp, phy,
10273 MDIO_REG_INTR_MASK,
10274 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10275
10276 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10277 bnx2x_cl22_write(bp, phy,
10278 MDIO_REG_GPHY_SHADOW,
10279 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10280 bnx2x_cl22_read(bp, phy,
10281 MDIO_REG_GPHY_SHADOW,
10282 &temp);
10283 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10284 bnx2x_cl22_write(bp, phy,
10285 MDIO_REG_GPHY_SHADOW,
10286 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10287
10288 /* Set up fc */
10289 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10290 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10291 fc_val = 0;
10292 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10293 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10294 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10295
10296 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10297 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10298 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10299
10300 /* read all advertisement */
10301 bnx2x_cl22_read(bp, phy,
10302 0x09,
10303 &an_1000_val);
10304
10305 bnx2x_cl22_read(bp, phy,
10306 0x04,
10307 &an_10_100_val);
10308
10309 bnx2x_cl22_read(bp, phy,
10310 MDIO_PMA_REG_CTRL,
10311 &autoneg_val);
10312
10313 /* Disable forced speed */
10314 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10315 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10316 (1<<11));
10317
10318 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10319 (phy->speed_cap_mask &
10320 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10321 (phy->req_line_speed == SPEED_1000)) {
10322 an_1000_val |= (1<<8);
10323 autoneg_val |= (1<<9 | 1<<12);
10324 if (phy->req_duplex == DUPLEX_FULL)
10325 an_1000_val |= (1<<9);
10326 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10327 } else
10328 an_1000_val &= ~((1<<8) | (1<<9));
10329
10330 bnx2x_cl22_write(bp, phy,
10331 0x09,
10332 an_1000_val);
10333 bnx2x_cl22_read(bp, phy,
10334 0x09,
10335 &an_1000_val);
10336
10337 /* set 100 speed advertisement */
10338 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10339 (phy->speed_cap_mask &
10340 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10341 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10342 an_10_100_val |= (1<<7);
10343 /* Enable autoneg and restart autoneg for legacy speeds */
10344 autoneg_val |= (1<<9 | 1<<12);
10345
10346 if (phy->req_duplex == DUPLEX_FULL)
10347 an_10_100_val |= (1<<8);
10348 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10349 }
10350
10351 /* set 10 speed advertisement */
10352 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10353 (phy->speed_cap_mask &
10354 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10355 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10356 an_10_100_val |= (1<<5);
10357 autoneg_val |= (1<<9 | 1<<12);
10358 if (phy->req_duplex == DUPLEX_FULL)
10359 an_10_100_val |= (1<<6);
10360 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10361 }
10362
10363 /* Only 10/100 are allowed to work in FORCE mode */
10364 if (phy->req_line_speed == SPEED_100) {
10365 autoneg_val |= (1<<13);
10366 /* Enabled AUTO-MDIX when autoneg is disabled */
10367 bnx2x_cl22_write(bp, phy,
10368 0x18,
10369 (1<<15 | 1<<9 | 7<<0));
10370 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10371 }
10372 if (phy->req_line_speed == SPEED_10) {
10373 /* Enabled AUTO-MDIX when autoneg is disabled */
10374 bnx2x_cl22_write(bp, phy,
10375 0x18,
10376 (1<<15 | 1<<9 | 7<<0));
10377 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10378 }
10379
10380 /* Check if we should turn on Auto-GrEEEn */
10381 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10382 if (temp == MDIO_REG_GPHY_ID_54618SE) {
10383 if (params->feature_config_flags &
10384 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10385 temp = 6;
10386 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10387 } else {
10388 temp = 0;
10389 DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10390 }
10391 bnx2x_cl22_write(bp, phy,
10392 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10393 bnx2x_cl22_write(bp, phy,
10394 MDIO_REG_GPHY_CL45_DATA_REG,
10395 MDIO_REG_GPHY_EEE_ADV);
10396 bnx2x_cl22_write(bp, phy,
10397 MDIO_REG_GPHY_CL45_ADDR_REG,
10398 (0x1 << 14) | MDIO_AN_DEVAD);
10399 bnx2x_cl22_write(bp, phy,
10400 MDIO_REG_GPHY_CL45_DATA_REG,
10401 temp);
10402 }
10403
10404 bnx2x_cl22_write(bp, phy,
10405 0x04,
10406 an_10_100_val | fc_val);
10407
10408 if (phy->req_duplex == DUPLEX_FULL)
10409 autoneg_val |= (1<<8);
10410
10411 bnx2x_cl22_write(bp, phy,
10412 MDIO_PMA_REG_CTRL, autoneg_val);
10413
10414 return 0;
10415 }
10416
10417
10418 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10419 struct link_params *params, u8 mode)
10420 {
10421 struct bnx2x *bp = params->bp;
10422 u16 temp;
10423
10424 bnx2x_cl22_write(bp, phy,
10425 MDIO_REG_GPHY_SHADOW,
10426 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10427 bnx2x_cl22_read(bp, phy,
10428 MDIO_REG_GPHY_SHADOW,
10429 &temp);
10430 temp &= 0xff00;
10431
10432 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10433 switch (mode) {
10434 case LED_MODE_FRONT_PANEL_OFF:
10435 case LED_MODE_OFF:
10436 temp |= 0x00ee;
10437 break;
10438 case LED_MODE_OPER:
10439 temp |= 0x0001;
10440 break;
10441 case LED_MODE_ON:
10442 temp |= 0x00ff;
10443 break;
10444 default:
10445 break;
10446 }
10447 bnx2x_cl22_write(bp, phy,
10448 MDIO_REG_GPHY_SHADOW,
10449 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10450 return;
10451 }
10452
10453
10454 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10455 struct link_params *params)
10456 {
10457 struct bnx2x *bp = params->bp;
10458 u32 cfg_pin;
10459 u8 port;
10460
10461 /*
10462 * In case of no EPIO routed to reset the GPHY, put it
10463 * in low power mode.
10464 */
10465 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10466 /*
10467 * This works with E3 only, no need to check the chip
10468 * before determining the port.
10469 */
10470 port = params->port;
10471 cfg_pin = (REG_RD(bp, params->shmem_base +
10472 offsetof(struct shmem_region,
10473 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10474 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10475 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10476
10477 /* Drive pin low to put GPHY in reset. */
10478 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10479 }
10480
10481 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10482 struct link_params *params,
10483 struct link_vars *vars)
10484 {
10485 struct bnx2x *bp = params->bp;
10486 u16 val;
10487 u8 link_up = 0;
10488 u16 legacy_status, legacy_speed;
10489
10490 /* Get speed operation status */
10491 bnx2x_cl22_read(bp, phy,
10492 0x19,
10493 &legacy_status);
10494 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10495
10496 /* Read status to clear the PHY interrupt. */
10497 bnx2x_cl22_read(bp, phy,
10498 MDIO_REG_INTR_STATUS,
10499 &val);
10500
10501 link_up = ((legacy_status & (1<<2)) == (1<<2));
10502
10503 if (link_up) {
10504 legacy_speed = (legacy_status & (7<<8));
10505 if (legacy_speed == (7<<8)) {
10506 vars->line_speed = SPEED_1000;
10507 vars->duplex = DUPLEX_FULL;
10508 } else if (legacy_speed == (6<<8)) {
10509 vars->line_speed = SPEED_1000;
10510 vars->duplex = DUPLEX_HALF;
10511 } else if (legacy_speed == (5<<8)) {
10512 vars->line_speed = SPEED_100;
10513 vars->duplex = DUPLEX_FULL;
10514 }
10515 /* Omitting 100Base-T4 for now */
10516 else if (legacy_speed == (3<<8)) {
10517 vars->line_speed = SPEED_100;
10518 vars->duplex = DUPLEX_HALF;
10519 } else if (legacy_speed == (2<<8)) {
10520 vars->line_speed = SPEED_10;
10521 vars->duplex = DUPLEX_FULL;
10522 } else if (legacy_speed == (1<<8)) {
10523 vars->line_speed = SPEED_10;
10524 vars->duplex = DUPLEX_HALF;
10525 } else /* Should not happen */
10526 vars->line_speed = 0;
10527
10528 DP(NETIF_MSG_LINK,
10529 "Link is up in %dMbps, is_duplex_full= %d\n",
10530 vars->line_speed,
10531 (vars->duplex == DUPLEX_FULL));
10532
10533 /* Check legacy speed AN resolution */
10534 bnx2x_cl22_read(bp, phy,
10535 0x01,
10536 &val);
10537 if (val & (1<<5))
10538 vars->link_status |=
10539 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10540 bnx2x_cl22_read(bp, phy,
10541 0x06,
10542 &val);
10543 if ((val & (1<<0)) == 0)
10544 vars->link_status |=
10545 LINK_STATUS_PARALLEL_DETECTION_USED;
10546
10547 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10548 vars->line_speed);
10549
10550 /* Report whether EEE is resolved. */
10551 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10552 if (val == MDIO_REG_GPHY_ID_54618SE) {
10553 if (vars->link_status &
10554 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10555 val = 0;
10556 else {
10557 bnx2x_cl22_write(bp, phy,
10558 MDIO_REG_GPHY_CL45_ADDR_REG,
10559 MDIO_AN_DEVAD);
10560 bnx2x_cl22_write(bp, phy,
10561 MDIO_REG_GPHY_CL45_DATA_REG,
10562 MDIO_REG_GPHY_EEE_RESOLVED);
10563 bnx2x_cl22_write(bp, phy,
10564 MDIO_REG_GPHY_CL45_ADDR_REG,
10565 (0x1 << 14) | MDIO_AN_DEVAD);
10566 bnx2x_cl22_read(bp, phy,
10567 MDIO_REG_GPHY_CL45_DATA_REG,
10568 &val);
10569 }
10570 DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10571 }
10572
10573 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10574 }
10575 return link_up;
10576 }
10577
10578 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10579 struct link_params *params)
10580 {
10581 struct bnx2x *bp = params->bp;
10582 u16 val;
10583 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10584
10585 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10586
10587 /* Enable master/slave manual mmode and set to master */
10588 /* mii write 9 [bits set 11 12] */
10589 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10590
10591 /* forced 1G and disable autoneg */
10592 /* set val [mii read 0] */
10593 /* set val [expr $val & [bits clear 6 12 13]] */
10594 /* set val [expr $val | [bits set 6 8]] */
10595 /* mii write 0 $val */
10596 bnx2x_cl22_read(bp, phy, 0x00, &val);
10597 val &= ~((1<<6) | (1<<12) | (1<<13));
10598 val |= (1<<6) | (1<<8);
10599 bnx2x_cl22_write(bp, phy, 0x00, val);
10600
10601 /* Set external loopback and Tx using 6dB coding */
10602 /* mii write 0x18 7 */
10603 /* set val [mii read 0x18] */
10604 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10605 bnx2x_cl22_write(bp, phy, 0x18, 7);
10606 bnx2x_cl22_read(bp, phy, 0x18, &val);
10607 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10608
10609 /* This register opens the gate for the UMAC despite its name */
10610 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10611
10612 /*
10613 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10614 * length used by the MAC receive logic to check frames.
10615 */
10616 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10617 }
10618
10619 /******************************************************************/
10620 /* SFX7101 PHY SECTION */
10621 /******************************************************************/
10622 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10623 struct link_params *params)
10624 {
10625 struct bnx2x *bp = params->bp;
10626 /* SFX7101_XGXS_TEST1 */
10627 bnx2x_cl45_write(bp, phy,
10628 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10629 }
10630
10631 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10632 struct link_params *params,
10633 struct link_vars *vars)
10634 {
10635 u16 fw_ver1, fw_ver2, val;
10636 struct bnx2x *bp = params->bp;
10637 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10638
10639 /* Restore normal power mode*/
10640 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10641 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10642 /* HW reset */
10643 bnx2x_ext_phy_hw_reset(bp, params->port);
10644 bnx2x_wait_reset_complete(bp, phy, params);
10645
10646 bnx2x_cl45_write(bp, phy,
10647 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10648 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10649 bnx2x_cl45_write(bp, phy,
10650 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10651
10652 bnx2x_ext_phy_set_pause(params, phy, vars);
10653 /* Restart autoneg */
10654 bnx2x_cl45_read(bp, phy,
10655 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10656 val |= 0x200;
10657 bnx2x_cl45_write(bp, phy,
10658 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10659
10660 /* Save spirom version */
10661 bnx2x_cl45_read(bp, phy,
10662 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10663
10664 bnx2x_cl45_read(bp, phy,
10665 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10666 bnx2x_save_spirom_version(bp, params->port,
10667 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10668 return 0;
10669 }
10670
10671 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10672 struct link_params *params,
10673 struct link_vars *vars)
10674 {
10675 struct bnx2x *bp = params->bp;
10676 u8 link_up;
10677 u16 val1, val2;
10678 bnx2x_cl45_read(bp, phy,
10679 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10680 bnx2x_cl45_read(bp, phy,
10681 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10682 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10683 val2, val1);
10684 bnx2x_cl45_read(bp, phy,
10685 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10686 bnx2x_cl45_read(bp, phy,
10687 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10688 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10689 val2, val1);
10690 link_up = ((val1 & 4) == 4);
10691 /* if link is up print the AN outcome of the SFX7101 PHY */
10692 if (link_up) {
10693 bnx2x_cl45_read(bp, phy,
10694 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10695 &val2);
10696 vars->line_speed = SPEED_10000;
10697 vars->duplex = DUPLEX_FULL;
10698 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10699 val2, (val2 & (1<<14)));
10700 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10701 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10702 }
10703 return link_up;
10704 }
10705
10706 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10707 {
10708 if (*len < 5)
10709 return -EINVAL;
10710 str[0] = (spirom_ver & 0xFF);
10711 str[1] = (spirom_ver & 0xFF00) >> 8;
10712 str[2] = (spirom_ver & 0xFF0000) >> 16;
10713 str[3] = (spirom_ver & 0xFF000000) >> 24;
10714 str[4] = '\0';
10715 *len -= 5;
10716 return 0;
10717 }
10718
10719 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10720 {
10721 u16 val, cnt;
10722
10723 bnx2x_cl45_read(bp, phy,
10724 MDIO_PMA_DEVAD,
10725 MDIO_PMA_REG_7101_RESET, &val);
10726
10727 for (cnt = 0; cnt < 10; cnt++) {
10728 msleep(50);
10729 /* Writes a self-clearing reset */
10730 bnx2x_cl45_write(bp, phy,
10731 MDIO_PMA_DEVAD,
10732 MDIO_PMA_REG_7101_RESET,
10733 (val | (1<<15)));
10734 /* Wait for clear */
10735 bnx2x_cl45_read(bp, phy,
10736 MDIO_PMA_DEVAD,
10737 MDIO_PMA_REG_7101_RESET, &val);
10738
10739 if ((val & (1<<15)) == 0)
10740 break;
10741 }
10742 }
10743
10744 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10745 struct link_params *params) {
10746 /* Low power mode is controlled by GPIO 2 */
10747 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10748 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10749 /* The PHY reset is controlled by GPIO 1 */
10750 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10751 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10752 }
10753
10754 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10755 struct link_params *params, u8 mode)
10756 {
10757 u16 val = 0;
10758 struct bnx2x *bp = params->bp;
10759 switch (mode) {
10760 case LED_MODE_FRONT_PANEL_OFF:
10761 case LED_MODE_OFF:
10762 val = 2;
10763 break;
10764 case LED_MODE_ON:
10765 val = 1;
10766 break;
10767 case LED_MODE_OPER:
10768 val = 0;
10769 break;
10770 }
10771 bnx2x_cl45_write(bp, phy,
10772 MDIO_PMA_DEVAD,
10773 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10774 val);
10775 }
10776
10777 /******************************************************************/
10778 /* STATIC PHY DECLARATION */
10779 /******************************************************************/
10780
10781 static struct bnx2x_phy phy_null = {
10782 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10783 .addr = 0,
10784 .def_md_devad = 0,
10785 .flags = FLAGS_INIT_XGXS_FIRST,
10786 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10787 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10788 .mdio_ctrl = 0,
10789 .supported = 0,
10790 .media_type = ETH_PHY_NOT_PRESENT,
10791 .ver_addr = 0,
10792 .req_flow_ctrl = 0,
10793 .req_line_speed = 0,
10794 .speed_cap_mask = 0,
10795 .req_duplex = 0,
10796 .rsrv = 0,
10797 .config_init = (config_init_t)NULL,
10798 .read_status = (read_status_t)NULL,
10799 .link_reset = (link_reset_t)NULL,
10800 .config_loopback = (config_loopback_t)NULL,
10801 .format_fw_ver = (format_fw_ver_t)NULL,
10802 .hw_reset = (hw_reset_t)NULL,
10803 .set_link_led = (set_link_led_t)NULL,
10804 .phy_specific_func = (phy_specific_func_t)NULL
10805 };
10806
10807 static struct bnx2x_phy phy_serdes = {
10808 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10809 .addr = 0xff,
10810 .def_md_devad = 0,
10811 .flags = 0,
10812 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10813 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10814 .mdio_ctrl = 0,
10815 .supported = (SUPPORTED_10baseT_Half |
10816 SUPPORTED_10baseT_Full |
10817 SUPPORTED_100baseT_Half |
10818 SUPPORTED_100baseT_Full |
10819 SUPPORTED_1000baseT_Full |
10820 SUPPORTED_2500baseX_Full |
10821 SUPPORTED_TP |
10822 SUPPORTED_Autoneg |
10823 SUPPORTED_Pause |
10824 SUPPORTED_Asym_Pause),
10825 .media_type = ETH_PHY_BASE_T,
10826 .ver_addr = 0,
10827 .req_flow_ctrl = 0,
10828 .req_line_speed = 0,
10829 .speed_cap_mask = 0,
10830 .req_duplex = 0,
10831 .rsrv = 0,
10832 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10833 .read_status = (read_status_t)bnx2x_link_settings_status,
10834 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10835 .config_loopback = (config_loopback_t)NULL,
10836 .format_fw_ver = (format_fw_ver_t)NULL,
10837 .hw_reset = (hw_reset_t)NULL,
10838 .set_link_led = (set_link_led_t)NULL,
10839 .phy_specific_func = (phy_specific_func_t)NULL
10840 };
10841
10842 static struct bnx2x_phy phy_xgxs = {
10843 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10844 .addr = 0xff,
10845 .def_md_devad = 0,
10846 .flags = 0,
10847 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10848 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10849 .mdio_ctrl = 0,
10850 .supported = (SUPPORTED_10baseT_Half |
10851 SUPPORTED_10baseT_Full |
10852 SUPPORTED_100baseT_Half |
10853 SUPPORTED_100baseT_Full |
10854 SUPPORTED_1000baseT_Full |
10855 SUPPORTED_2500baseX_Full |
10856 SUPPORTED_10000baseT_Full |
10857 SUPPORTED_FIBRE |
10858 SUPPORTED_Autoneg |
10859 SUPPORTED_Pause |
10860 SUPPORTED_Asym_Pause),
10861 .media_type = ETH_PHY_CX4,
10862 .ver_addr = 0,
10863 .req_flow_ctrl = 0,
10864 .req_line_speed = 0,
10865 .speed_cap_mask = 0,
10866 .req_duplex = 0,
10867 .rsrv = 0,
10868 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10869 .read_status = (read_status_t)bnx2x_link_settings_status,
10870 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10871 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10872 .format_fw_ver = (format_fw_ver_t)NULL,
10873 .hw_reset = (hw_reset_t)NULL,
10874 .set_link_led = (set_link_led_t)NULL,
10875 .phy_specific_func = (phy_specific_func_t)NULL
10876 };
10877 static struct bnx2x_phy phy_warpcore = {
10878 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10879 .addr = 0xff,
10880 .def_md_devad = 0,
10881 .flags = FLAGS_HW_LOCK_REQUIRED,
10882 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10883 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10884 .mdio_ctrl = 0,
10885 .supported = (SUPPORTED_10baseT_Half |
10886 SUPPORTED_10baseT_Full |
10887 SUPPORTED_100baseT_Half |
10888 SUPPORTED_100baseT_Full |
10889 SUPPORTED_1000baseT_Full |
10890 SUPPORTED_10000baseT_Full |
10891 SUPPORTED_20000baseKR2_Full |
10892 SUPPORTED_20000baseMLD2_Full |
10893 SUPPORTED_FIBRE |
10894 SUPPORTED_Autoneg |
10895 SUPPORTED_Pause |
10896 SUPPORTED_Asym_Pause),
10897 .media_type = ETH_PHY_UNSPECIFIED,
10898 .ver_addr = 0,
10899 .req_flow_ctrl = 0,
10900 .req_line_speed = 0,
10901 .speed_cap_mask = 0,
10902 /* req_duplex = */0,
10903 /* rsrv = */0,
10904 .config_init = (config_init_t)bnx2x_warpcore_config_init,
10905 .read_status = (read_status_t)bnx2x_warpcore_read_status,
10906 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
10907 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10908 .format_fw_ver = (format_fw_ver_t)NULL,
10909 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
10910 .set_link_led = (set_link_led_t)NULL,
10911 .phy_specific_func = (phy_specific_func_t)NULL
10912 };
10913
10914
10915 static struct bnx2x_phy phy_7101 = {
10916 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10917 .addr = 0xff,
10918 .def_md_devad = 0,
10919 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10920 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10921 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10922 .mdio_ctrl = 0,
10923 .supported = (SUPPORTED_10000baseT_Full |
10924 SUPPORTED_TP |
10925 SUPPORTED_Autoneg |
10926 SUPPORTED_Pause |
10927 SUPPORTED_Asym_Pause),
10928 .media_type = ETH_PHY_BASE_T,
10929 .ver_addr = 0,
10930 .req_flow_ctrl = 0,
10931 .req_line_speed = 0,
10932 .speed_cap_mask = 0,
10933 .req_duplex = 0,
10934 .rsrv = 0,
10935 .config_init = (config_init_t)bnx2x_7101_config_init,
10936 .read_status = (read_status_t)bnx2x_7101_read_status,
10937 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10938 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10939 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
10940 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
10941 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
10942 .phy_specific_func = (phy_specific_func_t)NULL
10943 };
10944 static struct bnx2x_phy phy_8073 = {
10945 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10946 .addr = 0xff,
10947 .def_md_devad = 0,
10948 .flags = FLAGS_HW_LOCK_REQUIRED,
10949 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10950 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10951 .mdio_ctrl = 0,
10952 .supported = (SUPPORTED_10000baseT_Full |
10953 SUPPORTED_2500baseX_Full |
10954 SUPPORTED_1000baseT_Full |
10955 SUPPORTED_FIBRE |
10956 SUPPORTED_Autoneg |
10957 SUPPORTED_Pause |
10958 SUPPORTED_Asym_Pause),
10959 .media_type = ETH_PHY_KR,
10960 .ver_addr = 0,
10961 .req_flow_ctrl = 0,
10962 .req_line_speed = 0,
10963 .speed_cap_mask = 0,
10964 .req_duplex = 0,
10965 .rsrv = 0,
10966 .config_init = (config_init_t)bnx2x_8073_config_init,
10967 .read_status = (read_status_t)bnx2x_8073_read_status,
10968 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
10969 .config_loopback = (config_loopback_t)NULL,
10970 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10971 .hw_reset = (hw_reset_t)NULL,
10972 .set_link_led = (set_link_led_t)NULL,
10973 .phy_specific_func = (phy_specific_func_t)NULL
10974 };
10975 static struct bnx2x_phy phy_8705 = {
10976 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10977 .addr = 0xff,
10978 .def_md_devad = 0,
10979 .flags = FLAGS_INIT_XGXS_FIRST,
10980 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10981 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10982 .mdio_ctrl = 0,
10983 .supported = (SUPPORTED_10000baseT_Full |
10984 SUPPORTED_FIBRE |
10985 SUPPORTED_Pause |
10986 SUPPORTED_Asym_Pause),
10987 .media_type = ETH_PHY_XFP_FIBER,
10988 .ver_addr = 0,
10989 .req_flow_ctrl = 0,
10990 .req_line_speed = 0,
10991 .speed_cap_mask = 0,
10992 .req_duplex = 0,
10993 .rsrv = 0,
10994 .config_init = (config_init_t)bnx2x_8705_config_init,
10995 .read_status = (read_status_t)bnx2x_8705_read_status,
10996 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10997 .config_loopback = (config_loopback_t)NULL,
10998 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
10999 .hw_reset = (hw_reset_t)NULL,
11000 .set_link_led = (set_link_led_t)NULL,
11001 .phy_specific_func = (phy_specific_func_t)NULL
11002 };
11003 static struct bnx2x_phy phy_8706 = {
11004 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11005 .addr = 0xff,
11006 .def_md_devad = 0,
11007 .flags = FLAGS_INIT_XGXS_FIRST,
11008 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11009 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11010 .mdio_ctrl = 0,
11011 .supported = (SUPPORTED_10000baseT_Full |
11012 SUPPORTED_1000baseT_Full |
11013 SUPPORTED_FIBRE |
11014 SUPPORTED_Pause |
11015 SUPPORTED_Asym_Pause),
11016 .media_type = ETH_PHY_SFP_FIBER,
11017 .ver_addr = 0,
11018 .req_flow_ctrl = 0,
11019 .req_line_speed = 0,
11020 .speed_cap_mask = 0,
11021 .req_duplex = 0,
11022 .rsrv = 0,
11023 .config_init = (config_init_t)bnx2x_8706_config_init,
11024 .read_status = (read_status_t)bnx2x_8706_read_status,
11025 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11026 .config_loopback = (config_loopback_t)NULL,
11027 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11028 .hw_reset = (hw_reset_t)NULL,
11029 .set_link_led = (set_link_led_t)NULL,
11030 .phy_specific_func = (phy_specific_func_t)NULL
11031 };
11032
11033 static struct bnx2x_phy phy_8726 = {
11034 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11035 .addr = 0xff,
11036 .def_md_devad = 0,
11037 .flags = (FLAGS_HW_LOCK_REQUIRED |
11038 FLAGS_INIT_XGXS_FIRST),
11039 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11040 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11041 .mdio_ctrl = 0,
11042 .supported = (SUPPORTED_10000baseT_Full |
11043 SUPPORTED_1000baseT_Full |
11044 SUPPORTED_Autoneg |
11045 SUPPORTED_FIBRE |
11046 SUPPORTED_Pause |
11047 SUPPORTED_Asym_Pause),
11048 .media_type = ETH_PHY_NOT_PRESENT,
11049 .ver_addr = 0,
11050 .req_flow_ctrl = 0,
11051 .req_line_speed = 0,
11052 .speed_cap_mask = 0,
11053 .req_duplex = 0,
11054 .rsrv = 0,
11055 .config_init = (config_init_t)bnx2x_8726_config_init,
11056 .read_status = (read_status_t)bnx2x_8726_read_status,
11057 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11058 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11059 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11060 .hw_reset = (hw_reset_t)NULL,
11061 .set_link_led = (set_link_led_t)NULL,
11062 .phy_specific_func = (phy_specific_func_t)NULL
11063 };
11064
11065 static struct bnx2x_phy phy_8727 = {
11066 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11067 .addr = 0xff,
11068 .def_md_devad = 0,
11069 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11070 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11071 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11072 .mdio_ctrl = 0,
11073 .supported = (SUPPORTED_10000baseT_Full |
11074 SUPPORTED_1000baseT_Full |
11075 SUPPORTED_FIBRE |
11076 SUPPORTED_Pause |
11077 SUPPORTED_Asym_Pause),
11078 .media_type = ETH_PHY_NOT_PRESENT,
11079 .ver_addr = 0,
11080 .req_flow_ctrl = 0,
11081 .req_line_speed = 0,
11082 .speed_cap_mask = 0,
11083 .req_duplex = 0,
11084 .rsrv = 0,
11085 .config_init = (config_init_t)bnx2x_8727_config_init,
11086 .read_status = (read_status_t)bnx2x_8727_read_status,
11087 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11088 .config_loopback = (config_loopback_t)NULL,
11089 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11090 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11091 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11092 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11093 };
11094 static struct bnx2x_phy phy_8481 = {
11095 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11096 .addr = 0xff,
11097 .def_md_devad = 0,
11098 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11099 FLAGS_REARM_LATCH_SIGNAL,
11100 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11101 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11102 .mdio_ctrl = 0,
11103 .supported = (SUPPORTED_10baseT_Half |
11104 SUPPORTED_10baseT_Full |
11105 SUPPORTED_100baseT_Half |
11106 SUPPORTED_100baseT_Full |
11107 SUPPORTED_1000baseT_Full |
11108 SUPPORTED_10000baseT_Full |
11109 SUPPORTED_TP |
11110 SUPPORTED_Autoneg |
11111 SUPPORTED_Pause |
11112 SUPPORTED_Asym_Pause),
11113 .media_type = ETH_PHY_BASE_T,
11114 .ver_addr = 0,
11115 .req_flow_ctrl = 0,
11116 .req_line_speed = 0,
11117 .speed_cap_mask = 0,
11118 .req_duplex = 0,
11119 .rsrv = 0,
11120 .config_init = (config_init_t)bnx2x_8481_config_init,
11121 .read_status = (read_status_t)bnx2x_848xx_read_status,
11122 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11123 .config_loopback = (config_loopback_t)NULL,
11124 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11125 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11126 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11127 .phy_specific_func = (phy_specific_func_t)NULL
11128 };
11129
11130 static struct bnx2x_phy phy_84823 = {
11131 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11132 .addr = 0xff,
11133 .def_md_devad = 0,
11134 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11135 FLAGS_REARM_LATCH_SIGNAL,
11136 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11137 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11138 .mdio_ctrl = 0,
11139 .supported = (SUPPORTED_10baseT_Half |
11140 SUPPORTED_10baseT_Full |
11141 SUPPORTED_100baseT_Half |
11142 SUPPORTED_100baseT_Full |
11143 SUPPORTED_1000baseT_Full |
11144 SUPPORTED_10000baseT_Full |
11145 SUPPORTED_TP |
11146 SUPPORTED_Autoneg |
11147 SUPPORTED_Pause |
11148 SUPPORTED_Asym_Pause),
11149 .media_type = ETH_PHY_BASE_T,
11150 .ver_addr = 0,
11151 .req_flow_ctrl = 0,
11152 .req_line_speed = 0,
11153 .speed_cap_mask = 0,
11154 .req_duplex = 0,
11155 .rsrv = 0,
11156 .config_init = (config_init_t)bnx2x_848x3_config_init,
11157 .read_status = (read_status_t)bnx2x_848xx_read_status,
11158 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11159 .config_loopback = (config_loopback_t)NULL,
11160 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11161 .hw_reset = (hw_reset_t)NULL,
11162 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11163 .phy_specific_func = (phy_specific_func_t)NULL
11164 };
11165
11166 static struct bnx2x_phy phy_84833 = {
11167 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11168 .addr = 0xff,
11169 .def_md_devad = 0,
11170 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11171 FLAGS_REARM_LATCH_SIGNAL,
11172 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11173 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11174 .mdio_ctrl = 0,
11175 .supported = (SUPPORTED_100baseT_Half |
11176 SUPPORTED_100baseT_Full |
11177 SUPPORTED_1000baseT_Full |
11178 SUPPORTED_10000baseT_Full |
11179 SUPPORTED_TP |
11180 SUPPORTED_Autoneg |
11181 SUPPORTED_Pause |
11182 SUPPORTED_Asym_Pause),
11183 .media_type = ETH_PHY_BASE_T,
11184 .ver_addr = 0,
11185 .req_flow_ctrl = 0,
11186 .req_line_speed = 0,
11187 .speed_cap_mask = 0,
11188 .req_duplex = 0,
11189 .rsrv = 0,
11190 .config_init = (config_init_t)bnx2x_848x3_config_init,
11191 .read_status = (read_status_t)bnx2x_848xx_read_status,
11192 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11193 .config_loopback = (config_loopback_t)NULL,
11194 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11195 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11196 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11197 .phy_specific_func = (phy_specific_func_t)NULL
11198 };
11199
11200 static struct bnx2x_phy phy_54618se = {
11201 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11202 .addr = 0xff,
11203 .def_md_devad = 0,
11204 .flags = FLAGS_INIT_XGXS_FIRST,
11205 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11206 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11207 .mdio_ctrl = 0,
11208 .supported = (SUPPORTED_10baseT_Half |
11209 SUPPORTED_10baseT_Full |
11210 SUPPORTED_100baseT_Half |
11211 SUPPORTED_100baseT_Full |
11212 SUPPORTED_1000baseT_Full |
11213 SUPPORTED_TP |
11214 SUPPORTED_Autoneg |
11215 SUPPORTED_Pause |
11216 SUPPORTED_Asym_Pause),
11217 .media_type = ETH_PHY_BASE_T,
11218 .ver_addr = 0,
11219 .req_flow_ctrl = 0,
11220 .req_line_speed = 0,
11221 .speed_cap_mask = 0,
11222 /* req_duplex = */0,
11223 /* rsrv = */0,
11224 .config_init = (config_init_t)bnx2x_54618se_config_init,
11225 .read_status = (read_status_t)bnx2x_54618se_read_status,
11226 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11227 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11228 .format_fw_ver = (format_fw_ver_t)NULL,
11229 .hw_reset = (hw_reset_t)NULL,
11230 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
11231 .phy_specific_func = (phy_specific_func_t)NULL
11232 };
11233 /*****************************************************************/
11234 /* */
11235 /* Populate the phy according. Main function: bnx2x_populate_phy */
11236 /* */
11237 /*****************************************************************/
11238
11239 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11240 struct bnx2x_phy *phy, u8 port,
11241 u8 phy_index)
11242 {
11243 /* Get the 4 lanes xgxs config rx and tx */
11244 u32 rx = 0, tx = 0, i;
11245 for (i = 0; i < 2; i++) {
11246 /*
11247 * INT_PHY and EXT_PHY1 share the same value location in the
11248 * shmem. When num_phys is greater than 1, than this value
11249 * applies only to EXT_PHY1
11250 */
11251 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11252 rx = REG_RD(bp, shmem_base +
11253 offsetof(struct shmem_region,
11254 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11255
11256 tx = REG_RD(bp, shmem_base +
11257 offsetof(struct shmem_region,
11258 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11259 } else {
11260 rx = REG_RD(bp, shmem_base +
11261 offsetof(struct shmem_region,
11262 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11263
11264 tx = REG_RD(bp, shmem_base +
11265 offsetof(struct shmem_region,
11266 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11267 }
11268
11269 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11270 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11271
11272 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11273 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11274 }
11275 }
11276
11277 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11278 u8 phy_index, u8 port)
11279 {
11280 u32 ext_phy_config = 0;
11281 switch (phy_index) {
11282 case EXT_PHY1:
11283 ext_phy_config = REG_RD(bp, shmem_base +
11284 offsetof(struct shmem_region,
11285 dev_info.port_hw_config[port].external_phy_config));
11286 break;
11287 case EXT_PHY2:
11288 ext_phy_config = REG_RD(bp, shmem_base +
11289 offsetof(struct shmem_region,
11290 dev_info.port_hw_config[port].external_phy_config2));
11291 break;
11292 default:
11293 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11294 return -EINVAL;
11295 }
11296
11297 return ext_phy_config;
11298 }
11299 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11300 struct bnx2x_phy *phy)
11301 {
11302 u32 phy_addr;
11303 u32 chip_id;
11304 u32 switch_cfg = (REG_RD(bp, shmem_base +
11305 offsetof(struct shmem_region,
11306 dev_info.port_feature_config[port].link_config)) &
11307 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11308 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11309 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11310
11311 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11312 if (USES_WARPCORE(bp)) {
11313 u32 serdes_net_if;
11314 phy_addr = REG_RD(bp,
11315 MISC_REG_WC0_CTRL_PHY_ADDR);
11316 *phy = phy_warpcore;
11317 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11318 phy->flags |= FLAGS_4_PORT_MODE;
11319 else
11320 phy->flags &= ~FLAGS_4_PORT_MODE;
11321 /* Check Dual mode */
11322 serdes_net_if = (REG_RD(bp, shmem_base +
11323 offsetof(struct shmem_region, dev_info.
11324 port_hw_config[port].default_cfg)) &
11325 PORT_HW_CFG_NET_SERDES_IF_MASK);
11326 /*
11327 * Set the appropriate supported and flags indications per
11328 * interface type of the chip
11329 */
11330 switch (serdes_net_if) {
11331 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11332 phy->supported &= (SUPPORTED_10baseT_Half |
11333 SUPPORTED_10baseT_Full |
11334 SUPPORTED_100baseT_Half |
11335 SUPPORTED_100baseT_Full |
11336 SUPPORTED_1000baseT_Full |
11337 SUPPORTED_FIBRE |
11338 SUPPORTED_Autoneg |
11339 SUPPORTED_Pause |
11340 SUPPORTED_Asym_Pause);
11341 phy->media_type = ETH_PHY_BASE_T;
11342 break;
11343 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11344 phy->media_type = ETH_PHY_XFP_FIBER;
11345 break;
11346 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11347 phy->supported &= (SUPPORTED_1000baseT_Full |
11348 SUPPORTED_10000baseT_Full |
11349 SUPPORTED_FIBRE |
11350 SUPPORTED_Pause |
11351 SUPPORTED_Asym_Pause);
11352 phy->media_type = ETH_PHY_SFP_FIBER;
11353 break;
11354 case PORT_HW_CFG_NET_SERDES_IF_KR:
11355 phy->media_type = ETH_PHY_KR;
11356 phy->supported &= (SUPPORTED_1000baseT_Full |
11357 SUPPORTED_10000baseT_Full |
11358 SUPPORTED_FIBRE |
11359 SUPPORTED_Autoneg |
11360 SUPPORTED_Pause |
11361 SUPPORTED_Asym_Pause);
11362 break;
11363 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11364 phy->media_type = ETH_PHY_KR;
11365 phy->flags |= FLAGS_WC_DUAL_MODE;
11366 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11367 SUPPORTED_FIBRE |
11368 SUPPORTED_Pause |
11369 SUPPORTED_Asym_Pause);
11370 break;
11371 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11372 phy->media_type = ETH_PHY_KR;
11373 phy->flags |= FLAGS_WC_DUAL_MODE;
11374 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11375 SUPPORTED_FIBRE |
11376 SUPPORTED_Pause |
11377 SUPPORTED_Asym_Pause);
11378 break;
11379 default:
11380 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11381 serdes_net_if);
11382 break;
11383 }
11384
11385 /*
11386 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11387 * was not set as expected. For B0, ECO will be enabled so there
11388 * won't be an issue there
11389 */
11390 if (CHIP_REV(bp) == CHIP_REV_Ax)
11391 phy->flags |= FLAGS_MDC_MDIO_WA;
11392 else
11393 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11394 } else {
11395 switch (switch_cfg) {
11396 case SWITCH_CFG_1G:
11397 phy_addr = REG_RD(bp,
11398 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11399 port * 0x10);
11400 *phy = phy_serdes;
11401 break;
11402 case SWITCH_CFG_10G:
11403 phy_addr = REG_RD(bp,
11404 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11405 port * 0x18);
11406 *phy = phy_xgxs;
11407 break;
11408 default:
11409 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11410 return -EINVAL;
11411 }
11412 }
11413 phy->addr = (u8)phy_addr;
11414 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11415 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11416 port);
11417 if (CHIP_IS_E2(bp))
11418 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11419 else
11420 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11421
11422 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11423 port, phy->addr, phy->mdio_ctrl);
11424
11425 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11426 return 0;
11427 }
11428
11429 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11430 u8 phy_index,
11431 u32 shmem_base,
11432 u32 shmem2_base,
11433 u8 port,
11434 struct bnx2x_phy *phy)
11435 {
11436 u32 ext_phy_config, phy_type, config2;
11437 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11438 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11439 phy_index, port);
11440 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11441 /* Select the phy type */
11442 switch (phy_type) {
11443 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11444 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11445 *phy = phy_8073;
11446 break;
11447 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11448 *phy = phy_8705;
11449 break;
11450 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11451 *phy = phy_8706;
11452 break;
11453 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11454 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11455 *phy = phy_8726;
11456 break;
11457 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11458 /* BCM8727_NOC => BCM8727 no over current */
11459 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11460 *phy = phy_8727;
11461 phy->flags |= FLAGS_NOC;
11462 break;
11463 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11464 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11465 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11466 *phy = phy_8727;
11467 break;
11468 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11469 *phy = phy_8481;
11470 break;
11471 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11472 *phy = phy_84823;
11473 break;
11474 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11475 *phy = phy_84833;
11476 break;
11477 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11478 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11479 *phy = phy_54618se;
11480 break;
11481 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11482 *phy = phy_7101;
11483 break;
11484 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11485 *phy = phy_null;
11486 return -EINVAL;
11487 default:
11488 *phy = phy_null;
11489 /* In case external PHY wasn't found */
11490 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11491 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11492 return -EINVAL;
11493 return 0;
11494 }
11495
11496 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11497 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11498
11499 /*
11500 * The shmem address of the phy version is located on different
11501 * structures. In case this structure is too old, do not set
11502 * the address
11503 */
11504 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11505 dev_info.shared_hw_config.config2));
11506 if (phy_index == EXT_PHY1) {
11507 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11508 port_mb[port].ext_phy_fw_version);
11509
11510 /* Check specific mdc mdio settings */
11511 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11512 mdc_mdio_access = config2 &
11513 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11514 } else {
11515 u32 size = REG_RD(bp, shmem2_base);
11516
11517 if (size >
11518 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11519 phy->ver_addr = shmem2_base +
11520 offsetof(struct shmem2_region,
11521 ext_phy_fw_version2[port]);
11522 }
11523 /* Check specific mdc mdio settings */
11524 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11525 mdc_mdio_access = (config2 &
11526 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11527 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11528 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11529 }
11530 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11531
11532 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
11533 (phy->ver_addr)) {
11534 /*
11535 * Remove 100Mb link supported for BCM84833 when phy fw
11536 * version lower than or equal to 1.39
11537 */
11538 u32 raw_ver = REG_RD(bp, phy->ver_addr);
11539 if (((raw_ver & 0x7F) <= 39) &&
11540 (((raw_ver & 0xF80) >> 7) <= 1))
11541 phy->supported &= ~(SUPPORTED_100baseT_Half |
11542 SUPPORTED_100baseT_Full);
11543 }
11544
11545 /*
11546 * In case mdc/mdio_access of the external phy is different than the
11547 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11548 * to prevent one port interfere with another port's CL45 operations.
11549 */
11550 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11551 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11552 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11553 phy_type, port, phy_index);
11554 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
11555 phy->addr, phy->mdio_ctrl);
11556 return 0;
11557 }
11558
11559 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11560 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11561 {
11562 int status = 0;
11563 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11564 if (phy_index == INT_PHY)
11565 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11566 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11567 port, phy);
11568 return status;
11569 }
11570
11571 static void bnx2x_phy_def_cfg(struct link_params *params,
11572 struct bnx2x_phy *phy,
11573 u8 phy_index)
11574 {
11575 struct bnx2x *bp = params->bp;
11576 u32 link_config;
11577 /* Populate the default phy configuration for MF mode */
11578 if (phy_index == EXT_PHY2) {
11579 link_config = REG_RD(bp, params->shmem_base +
11580 offsetof(struct shmem_region, dev_info.
11581 port_feature_config[params->port].link_config2));
11582 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11583 offsetof(struct shmem_region,
11584 dev_info.
11585 port_hw_config[params->port].speed_capability_mask2));
11586 } else {
11587 link_config = REG_RD(bp, params->shmem_base +
11588 offsetof(struct shmem_region, dev_info.
11589 port_feature_config[params->port].link_config));
11590 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11591 offsetof(struct shmem_region,
11592 dev_info.
11593 port_hw_config[params->port].speed_capability_mask));
11594 }
11595 DP(NETIF_MSG_LINK,
11596 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11597 phy_index, link_config, phy->speed_cap_mask);
11598
11599 phy->req_duplex = DUPLEX_FULL;
11600 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11601 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11602 phy->req_duplex = DUPLEX_HALF;
11603 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11604 phy->req_line_speed = SPEED_10;
11605 break;
11606 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11607 phy->req_duplex = DUPLEX_HALF;
11608 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11609 phy->req_line_speed = SPEED_100;
11610 break;
11611 case PORT_FEATURE_LINK_SPEED_1G:
11612 phy->req_line_speed = SPEED_1000;
11613 break;
11614 case PORT_FEATURE_LINK_SPEED_2_5G:
11615 phy->req_line_speed = SPEED_2500;
11616 break;
11617 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11618 phy->req_line_speed = SPEED_10000;
11619 break;
11620 default:
11621 phy->req_line_speed = SPEED_AUTO_NEG;
11622 break;
11623 }
11624
11625 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11626 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11627 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11628 break;
11629 case PORT_FEATURE_FLOW_CONTROL_TX:
11630 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11631 break;
11632 case PORT_FEATURE_FLOW_CONTROL_RX:
11633 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11634 break;
11635 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11636 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11637 break;
11638 default:
11639 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11640 break;
11641 }
11642 }
11643
11644 u32 bnx2x_phy_selection(struct link_params *params)
11645 {
11646 u32 phy_config_swapped, prio_cfg;
11647 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11648
11649 phy_config_swapped = params->multi_phy_config &
11650 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11651
11652 prio_cfg = params->multi_phy_config &
11653 PORT_HW_CFG_PHY_SELECTION_MASK;
11654
11655 if (phy_config_swapped) {
11656 switch (prio_cfg) {
11657 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11658 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11659 break;
11660 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11661 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11662 break;
11663 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11664 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11665 break;
11666 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11667 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11668 break;
11669 }
11670 } else
11671 return_cfg = prio_cfg;
11672
11673 return return_cfg;
11674 }
11675
11676
11677 int bnx2x_phy_probe(struct link_params *params)
11678 {
11679 u8 phy_index, actual_phy_idx;
11680 u32 phy_config_swapped, sync_offset, media_types;
11681 struct bnx2x *bp = params->bp;
11682 struct bnx2x_phy *phy;
11683 params->num_phys = 0;
11684 DP(NETIF_MSG_LINK, "Begin phy probe\n");
11685 phy_config_swapped = params->multi_phy_config &
11686 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11687
11688 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11689 phy_index++) {
11690 actual_phy_idx = phy_index;
11691 if (phy_config_swapped) {
11692 if (phy_index == EXT_PHY1)
11693 actual_phy_idx = EXT_PHY2;
11694 else if (phy_index == EXT_PHY2)
11695 actual_phy_idx = EXT_PHY1;
11696 }
11697 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11698 " actual_phy_idx %x\n", phy_config_swapped,
11699 phy_index, actual_phy_idx);
11700 phy = &params->phy[actual_phy_idx];
11701 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11702 params->shmem2_base, params->port,
11703 phy) != 0) {
11704 params->num_phys = 0;
11705 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11706 phy_index);
11707 for (phy_index = INT_PHY;
11708 phy_index < MAX_PHYS;
11709 phy_index++)
11710 *phy = phy_null;
11711 return -EINVAL;
11712 }
11713 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11714 break;
11715
11716 sync_offset = params->shmem_base +
11717 offsetof(struct shmem_region,
11718 dev_info.port_hw_config[params->port].media_type);
11719 media_types = REG_RD(bp, sync_offset);
11720
11721 /*
11722 * Update media type for non-PMF sync only for the first time
11723 * In case the media type changes afterwards, it will be updated
11724 * using the update_status function
11725 */
11726 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11727 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11728 actual_phy_idx))) == 0) {
11729 media_types |= ((phy->media_type &
11730 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11731 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11732 actual_phy_idx));
11733 }
11734 REG_WR(bp, sync_offset, media_types);
11735
11736 bnx2x_phy_def_cfg(params, phy, phy_index);
11737 params->num_phys++;
11738 }
11739
11740 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11741 return 0;
11742 }
11743
11744 void bnx2x_init_bmac_loopback(struct link_params *params,
11745 struct link_vars *vars)
11746 {
11747 struct bnx2x *bp = params->bp;
11748 vars->link_up = 1;
11749 vars->line_speed = SPEED_10000;
11750 vars->duplex = DUPLEX_FULL;
11751 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11752 vars->mac_type = MAC_TYPE_BMAC;
11753
11754 vars->phy_flags = PHY_XGXS_FLAG;
11755
11756 bnx2x_xgxs_deassert(params);
11757
11758 /* set bmac loopback */
11759 bnx2x_bmac_enable(params, vars, 1);
11760
11761 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11762 }
11763
11764 void bnx2x_init_emac_loopback(struct link_params *params,
11765 struct link_vars *vars)
11766 {
11767 struct bnx2x *bp = params->bp;
11768 vars->link_up = 1;
11769 vars->line_speed = SPEED_1000;
11770 vars->duplex = DUPLEX_FULL;
11771 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11772 vars->mac_type = MAC_TYPE_EMAC;
11773
11774 vars->phy_flags = PHY_XGXS_FLAG;
11775
11776 bnx2x_xgxs_deassert(params);
11777 /* set bmac loopback */
11778 bnx2x_emac_enable(params, vars, 1);
11779 bnx2x_emac_program(params, vars);
11780 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11781 }
11782
11783 void bnx2x_init_xmac_loopback(struct link_params *params,
11784 struct link_vars *vars)
11785 {
11786 struct bnx2x *bp = params->bp;
11787 vars->link_up = 1;
11788 if (!params->req_line_speed[0])
11789 vars->line_speed = SPEED_10000;
11790 else
11791 vars->line_speed = params->req_line_speed[0];
11792 vars->duplex = DUPLEX_FULL;
11793 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11794 vars->mac_type = MAC_TYPE_XMAC;
11795 vars->phy_flags = PHY_XGXS_FLAG;
11796 /*
11797 * Set WC to loopback mode since link is required to provide clock
11798 * to the XMAC in 20G mode
11799 */
11800 bnx2x_set_aer_mmd(params, &params->phy[0]);
11801 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11802 params->phy[INT_PHY].config_loopback(
11803 &params->phy[INT_PHY],
11804 params);
11805
11806 bnx2x_xmac_enable(params, vars, 1);
11807 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11808 }
11809
11810 void bnx2x_init_umac_loopback(struct link_params *params,
11811 struct link_vars *vars)
11812 {
11813 struct bnx2x *bp = params->bp;
11814 vars->link_up = 1;
11815 vars->line_speed = SPEED_1000;
11816 vars->duplex = DUPLEX_FULL;
11817 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11818 vars->mac_type = MAC_TYPE_UMAC;
11819 vars->phy_flags = PHY_XGXS_FLAG;
11820 bnx2x_umac_enable(params, vars, 1);
11821
11822 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11823 }
11824
11825 void bnx2x_init_xgxs_loopback(struct link_params *params,
11826 struct link_vars *vars)
11827 {
11828 struct bnx2x *bp = params->bp;
11829 vars->link_up = 1;
11830 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11831 vars->duplex = DUPLEX_FULL;
11832 if (params->req_line_speed[0] == SPEED_1000)
11833 vars->line_speed = SPEED_1000;
11834 else
11835 vars->line_speed = SPEED_10000;
11836
11837 if (!USES_WARPCORE(bp))
11838 bnx2x_xgxs_deassert(params);
11839 bnx2x_link_initialize(params, vars);
11840
11841 if (params->req_line_speed[0] == SPEED_1000) {
11842 if (USES_WARPCORE(bp))
11843 bnx2x_umac_enable(params, vars, 0);
11844 else {
11845 bnx2x_emac_program(params, vars);
11846 bnx2x_emac_enable(params, vars, 0);
11847 }
11848 } else {
11849 if (USES_WARPCORE(bp))
11850 bnx2x_xmac_enable(params, vars, 0);
11851 else
11852 bnx2x_bmac_enable(params, vars, 0);
11853 }
11854
11855 if (params->loopback_mode == LOOPBACK_XGXS) {
11856 /* set 10G XGXS loopback */
11857 params->phy[INT_PHY].config_loopback(
11858 &params->phy[INT_PHY],
11859 params);
11860
11861 } else {
11862 /* set external phy loopback */
11863 u8 phy_index;
11864 for (phy_index = EXT_PHY1;
11865 phy_index < params->num_phys; phy_index++) {
11866 if (params->phy[phy_index].config_loopback)
11867 params->phy[phy_index].config_loopback(
11868 &params->phy[phy_index],
11869 params);
11870 }
11871 }
11872 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11873
11874 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11875 }
11876
11877 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11878 {
11879 struct bnx2x *bp = params->bp;
11880 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11881 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11882 params->req_line_speed[0], params->req_flow_ctrl[0]);
11883 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11884 params->req_line_speed[1], params->req_flow_ctrl[1]);
11885 vars->link_status = 0;
11886 vars->phy_link_up = 0;
11887 vars->link_up = 0;
11888 vars->line_speed = 0;
11889 vars->duplex = DUPLEX_FULL;
11890 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11891 vars->mac_type = MAC_TYPE_NONE;
11892 vars->phy_flags = 0;
11893
11894 /* disable attentions */
11895 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11896 (NIG_MASK_XGXS0_LINK_STATUS |
11897 NIG_MASK_XGXS0_LINK10G |
11898 NIG_MASK_SERDES0_LINK_STATUS |
11899 NIG_MASK_MI_INT));
11900
11901 bnx2x_emac_init(params, vars);
11902
11903 if (params->num_phys == 0) {
11904 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11905 return -EINVAL;
11906 }
11907 set_phy_vars(params, vars);
11908
11909 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11910 switch (params->loopback_mode) {
11911 case LOOPBACK_BMAC:
11912 bnx2x_init_bmac_loopback(params, vars);
11913 break;
11914 case LOOPBACK_EMAC:
11915 bnx2x_init_emac_loopback(params, vars);
11916 break;
11917 case LOOPBACK_XMAC:
11918 bnx2x_init_xmac_loopback(params, vars);
11919 break;
11920 case LOOPBACK_UMAC:
11921 bnx2x_init_umac_loopback(params, vars);
11922 break;
11923 case LOOPBACK_XGXS:
11924 case LOOPBACK_EXT_PHY:
11925 bnx2x_init_xgxs_loopback(params, vars);
11926 break;
11927 default:
11928 if (!CHIP_IS_E3(bp)) {
11929 if (params->switch_cfg == SWITCH_CFG_10G)
11930 bnx2x_xgxs_deassert(params);
11931 else
11932 bnx2x_serdes_deassert(bp, params->port);
11933 }
11934 bnx2x_link_initialize(params, vars);
11935 msleep(30);
11936 bnx2x_link_int_enable(params);
11937 break;
11938 }
11939 return 0;
11940 }
11941
11942 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11943 u8 reset_ext_phy)
11944 {
11945 struct bnx2x *bp = params->bp;
11946 u8 phy_index, port = params->port, clear_latch_ind = 0;
11947 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11948 /* disable attentions */
11949 vars->link_status = 0;
11950 bnx2x_update_mng(params, vars->link_status);
11951 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11952 (NIG_MASK_XGXS0_LINK_STATUS |
11953 NIG_MASK_XGXS0_LINK10G |
11954 NIG_MASK_SERDES0_LINK_STATUS |
11955 NIG_MASK_MI_INT));
11956
11957 /* activate nig drain */
11958 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11959
11960 /* disable nig egress interface */
11961 if (!CHIP_IS_E3(bp)) {
11962 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11963 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11964 }
11965
11966 /* Stop BigMac rx */
11967 if (!CHIP_IS_E3(bp))
11968 bnx2x_bmac_rx_disable(bp, port);
11969 else {
11970 bnx2x_xmac_disable(params);
11971 bnx2x_umac_disable(params);
11972 }
11973 /* disable emac */
11974 if (!CHIP_IS_E3(bp))
11975 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11976
11977 msleep(10);
11978 /* The PHY reset is controlled by GPIO 1
11979 * Hold it as vars low
11980 */
11981 /* clear link led */
11982 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11983
11984 if (reset_ext_phy) {
11985 bnx2x_set_mdio_clk(bp, params->chip_id, port);
11986 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11987 phy_index++) {
11988 if (params->phy[phy_index].link_reset) {
11989 bnx2x_set_aer_mmd(params,
11990 &params->phy[phy_index]);
11991 params->phy[phy_index].link_reset(
11992 &params->phy[phy_index],
11993 params);
11994 }
11995 if (params->phy[phy_index].flags &
11996 FLAGS_REARM_LATCH_SIGNAL)
11997 clear_latch_ind = 1;
11998 }
11999 }
12000
12001 if (clear_latch_ind) {
12002 /* Clear latching indication */
12003 bnx2x_rearm_latch_signal(bp, port, 0);
12004 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12005 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12006 }
12007 if (params->phy[INT_PHY].link_reset)
12008 params->phy[INT_PHY].link_reset(
12009 &params->phy[INT_PHY], params);
12010
12011 /* disable nig ingress interface */
12012 if (!CHIP_IS_E3(bp)) {
12013 /* reset BigMac */
12014 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12015 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12016 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12017 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12018 } else {
12019 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12020 bnx2x_set_xumac_nig(params, 0, 0);
12021 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12022 MISC_REGISTERS_RESET_REG_2_XMAC)
12023 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12024 XMAC_CTRL_REG_SOFT_RESET);
12025 }
12026 vars->link_up = 0;
12027 vars->phy_flags = 0;
12028 return 0;
12029 }
12030
12031 /****************************************************************************/
12032 /* Common function */
12033 /****************************************************************************/
12034 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12035 u32 shmem_base_path[],
12036 u32 shmem2_base_path[], u8 phy_index,
12037 u32 chip_id)
12038 {
12039 struct bnx2x_phy phy[PORT_MAX];
12040 struct bnx2x_phy *phy_blk[PORT_MAX];
12041 u16 val;
12042 s8 port = 0;
12043 s8 port_of_path = 0;
12044 u32 swap_val, swap_override;
12045 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12046 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12047 port ^= (swap_val && swap_override);
12048 bnx2x_ext_phy_hw_reset(bp, port);
12049 /* PART1 - Reset both phys */
12050 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12051 u32 shmem_base, shmem2_base;
12052 /* In E2, same phy is using for port0 of the two paths */
12053 if (CHIP_IS_E1x(bp)) {
12054 shmem_base = shmem_base_path[0];
12055 shmem2_base = shmem2_base_path[0];
12056 port_of_path = port;
12057 } else {
12058 shmem_base = shmem_base_path[port];
12059 shmem2_base = shmem2_base_path[port];
12060 port_of_path = 0;
12061 }
12062
12063 /* Extract the ext phy address for the port */
12064 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12065 port_of_path, &phy[port]) !=
12066 0) {
12067 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12068 return -EINVAL;
12069 }
12070 /* disable attentions */
12071 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12072 port_of_path*4,
12073 (NIG_MASK_XGXS0_LINK_STATUS |
12074 NIG_MASK_XGXS0_LINK10G |
12075 NIG_MASK_SERDES0_LINK_STATUS |
12076 NIG_MASK_MI_INT));
12077
12078 /* Need to take the phy out of low power mode in order
12079 to write to access its registers */
12080 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12081 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12082 port);
12083
12084 /* Reset the phy */
12085 bnx2x_cl45_write(bp, &phy[port],
12086 MDIO_PMA_DEVAD,
12087 MDIO_PMA_REG_CTRL,
12088 1<<15);
12089 }
12090
12091 /* Add delay of 150ms after reset */
12092 msleep(150);
12093
12094 if (phy[PORT_0].addr & 0x1) {
12095 phy_blk[PORT_0] = &(phy[PORT_1]);
12096 phy_blk[PORT_1] = &(phy[PORT_0]);
12097 } else {
12098 phy_blk[PORT_0] = &(phy[PORT_0]);
12099 phy_blk[PORT_1] = &(phy[PORT_1]);
12100 }
12101
12102 /* PART2 - Download firmware to both phys */
12103 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12104 if (CHIP_IS_E1x(bp))
12105 port_of_path = port;
12106 else
12107 port_of_path = 0;
12108
12109 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12110 phy_blk[port]->addr);
12111 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12112 port_of_path))
12113 return -EINVAL;
12114
12115 /* Only set bit 10 = 1 (Tx power down) */
12116 bnx2x_cl45_read(bp, phy_blk[port],
12117 MDIO_PMA_DEVAD,
12118 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12119
12120 /* Phase1 of TX_POWER_DOWN reset */
12121 bnx2x_cl45_write(bp, phy_blk[port],
12122 MDIO_PMA_DEVAD,
12123 MDIO_PMA_REG_TX_POWER_DOWN,
12124 (val | 1<<10));
12125 }
12126
12127 /*
12128 * Toggle Transmitter: Power down and then up with 600ms delay
12129 * between
12130 */
12131 msleep(600);
12132
12133 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12134 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12135 /* Phase2 of POWER_DOWN_RESET */
12136 /* Release bit 10 (Release Tx power down) */
12137 bnx2x_cl45_read(bp, phy_blk[port],
12138 MDIO_PMA_DEVAD,
12139 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12140
12141 bnx2x_cl45_write(bp, phy_blk[port],
12142 MDIO_PMA_DEVAD,
12143 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12144 msleep(15);
12145
12146 /* Read modify write the SPI-ROM version select register */
12147 bnx2x_cl45_read(bp, phy_blk[port],
12148 MDIO_PMA_DEVAD,
12149 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12150 bnx2x_cl45_write(bp, phy_blk[port],
12151 MDIO_PMA_DEVAD,
12152 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12153
12154 /* set GPIO2 back to LOW */
12155 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12156 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12157 }
12158 return 0;
12159 }
12160 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12161 u32 shmem_base_path[],
12162 u32 shmem2_base_path[], u8 phy_index,
12163 u32 chip_id)
12164 {
12165 u32 val;
12166 s8 port;
12167 struct bnx2x_phy phy;
12168 /* Use port1 because of the static port-swap */
12169 /* Enable the module detection interrupt */
12170 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12171 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12172 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12173 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12174
12175 bnx2x_ext_phy_hw_reset(bp, 0);
12176 msleep(5);
12177 for (port = 0; port < PORT_MAX; port++) {
12178 u32 shmem_base, shmem2_base;
12179
12180 /* In E2, same phy is using for port0 of the two paths */
12181 if (CHIP_IS_E1x(bp)) {
12182 shmem_base = shmem_base_path[0];
12183 shmem2_base = shmem2_base_path[0];
12184 } else {
12185 shmem_base = shmem_base_path[port];
12186 shmem2_base = shmem2_base_path[port];
12187 }
12188 /* Extract the ext phy address for the port */
12189 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12190 port, &phy) !=
12191 0) {
12192 DP(NETIF_MSG_LINK, "populate phy failed\n");
12193 return -EINVAL;
12194 }
12195
12196 /* Reset phy*/
12197 bnx2x_cl45_write(bp, &phy,
12198 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12199
12200
12201 /* Set fault module detected LED on */
12202 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12203 MISC_REGISTERS_GPIO_HIGH,
12204 port);
12205 }
12206
12207 return 0;
12208 }
12209 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12210 u8 *io_gpio, u8 *io_port)
12211 {
12212
12213 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12214 offsetof(struct shmem_region,
12215 dev_info.port_hw_config[PORT_0].default_cfg));
12216 switch (phy_gpio_reset) {
12217 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12218 *io_gpio = 0;
12219 *io_port = 0;
12220 break;
12221 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12222 *io_gpio = 1;
12223 *io_port = 0;
12224 break;
12225 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12226 *io_gpio = 2;
12227 *io_port = 0;
12228 break;
12229 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12230 *io_gpio = 3;
12231 *io_port = 0;
12232 break;
12233 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12234 *io_gpio = 0;
12235 *io_port = 1;
12236 break;
12237 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12238 *io_gpio = 1;
12239 *io_port = 1;
12240 break;
12241 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12242 *io_gpio = 2;
12243 *io_port = 1;
12244 break;
12245 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12246 *io_gpio = 3;
12247 *io_port = 1;
12248 break;
12249 default:
12250 /* Don't override the io_gpio and io_port */
12251 break;
12252 }
12253 }
12254
12255 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12256 u32 shmem_base_path[],
12257 u32 shmem2_base_path[], u8 phy_index,
12258 u32 chip_id)
12259 {
12260 s8 port, reset_gpio;
12261 u32 swap_val, swap_override;
12262 struct bnx2x_phy phy[PORT_MAX];
12263 struct bnx2x_phy *phy_blk[PORT_MAX];
12264 s8 port_of_path;
12265 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12266 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12267
12268 reset_gpio = MISC_REGISTERS_GPIO_1;
12269 port = 1;
12270
12271 /*
12272 * Retrieve the reset gpio/port which control the reset.
12273 * Default is GPIO1, PORT1
12274 */
12275 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12276 (u8 *)&reset_gpio, (u8 *)&port);
12277
12278 /* Calculate the port based on port swap */
12279 port ^= (swap_val && swap_override);
12280
12281 /* Initiate PHY reset*/
12282 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12283 port);
12284 msleep(1);
12285 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12286 port);
12287
12288 msleep(5);
12289
12290 /* PART1 - Reset both phys */
12291 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12292 u32 shmem_base, shmem2_base;
12293
12294 /* In E2, same phy is using for port0 of the two paths */
12295 if (CHIP_IS_E1x(bp)) {
12296 shmem_base = shmem_base_path[0];
12297 shmem2_base = shmem2_base_path[0];
12298 port_of_path = port;
12299 } else {
12300 shmem_base = shmem_base_path[port];
12301 shmem2_base = shmem2_base_path[port];
12302 port_of_path = 0;
12303 }
12304
12305 /* Extract the ext phy address for the port */
12306 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12307 port_of_path, &phy[port]) !=
12308 0) {
12309 DP(NETIF_MSG_LINK, "populate phy failed\n");
12310 return -EINVAL;
12311 }
12312 /* disable attentions */
12313 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12314 port_of_path*4,
12315 (NIG_MASK_XGXS0_LINK_STATUS |
12316 NIG_MASK_XGXS0_LINK10G |
12317 NIG_MASK_SERDES0_LINK_STATUS |
12318 NIG_MASK_MI_INT));
12319
12320
12321 /* Reset the phy */
12322 bnx2x_cl45_write(bp, &phy[port],
12323 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12324 }
12325
12326 /* Add delay of 150ms after reset */
12327 msleep(150);
12328 if (phy[PORT_0].addr & 0x1) {
12329 phy_blk[PORT_0] = &(phy[PORT_1]);
12330 phy_blk[PORT_1] = &(phy[PORT_0]);
12331 } else {
12332 phy_blk[PORT_0] = &(phy[PORT_0]);
12333 phy_blk[PORT_1] = &(phy[PORT_1]);
12334 }
12335 /* PART2 - Download firmware to both phys */
12336 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12337 if (CHIP_IS_E1x(bp))
12338 port_of_path = port;
12339 else
12340 port_of_path = 0;
12341 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12342 phy_blk[port]->addr);
12343 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12344 port_of_path))
12345 return -EINVAL;
12346 /* Disable PHY transmitter output */
12347 bnx2x_cl45_write(bp, phy_blk[port],
12348 MDIO_PMA_DEVAD,
12349 MDIO_PMA_REG_TX_DISABLE, 1);
12350
12351 }
12352 return 0;
12353 }
12354
12355 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
12356 u32 shmem_base_path[],
12357 u32 shmem2_base_path[],
12358 u8 phy_index,
12359 u32 chip_id)
12360 {
12361 u8 reset_gpios;
12362 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
12363 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
12364 udelay(10);
12365 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12366 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
12367 reset_gpios);
12368 return 0;
12369 }
12370
12371 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
12372 struct bnx2x_phy *phy)
12373 {
12374 u16 val, cnt;
12375 /* Wait for FW completing its initialization. */
12376 for (cnt = 0; cnt < 1500; cnt++) {
12377 bnx2x_cl45_read(bp, phy,
12378 MDIO_PMA_DEVAD,
12379 MDIO_PMA_REG_CTRL, &val);
12380 if (!(val & (1<<15)))
12381 break;
12382 msleep(1);
12383 }
12384 if (cnt >= 1500) {
12385 DP(NETIF_MSG_LINK, "84833 reset timeout\n");
12386 return -EINVAL;
12387 }
12388
12389 /* Put the port in super isolate mode. */
12390 bnx2x_cl45_read(bp, phy,
12391 MDIO_CTL_DEVAD,
12392 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
12393 val |= MDIO_84833_SUPER_ISOLATE;
12394 bnx2x_cl45_write(bp, phy,
12395 MDIO_CTL_DEVAD,
12396 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
12397
12398 /* Save spirom version */
12399 bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
12400 return 0;
12401 }
12402
12403 int bnx2x_pre_init_phy(struct bnx2x *bp,
12404 u32 shmem_base,
12405 u32 shmem2_base,
12406 u32 chip_id)
12407 {
12408 int rc = 0;
12409 struct bnx2x_phy phy;
12410 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12411 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
12412 PORT_0, &phy)) {
12413 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12414 return -EINVAL;
12415 }
12416 switch (phy.type) {
12417 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12418 rc = bnx2x_84833_pre_init_phy(bp, &phy);
12419 break;
12420 default:
12421 break;
12422 }
12423 return rc;
12424 }
12425
12426 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12427 u32 shmem2_base_path[], u8 phy_index,
12428 u32 ext_phy_type, u32 chip_id)
12429 {
12430 int rc = 0;
12431
12432 switch (ext_phy_type) {
12433 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12434 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12435 shmem2_base_path,
12436 phy_index, chip_id);
12437 break;
12438 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12439 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12440 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12441 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12442 shmem2_base_path,
12443 phy_index, chip_id);
12444 break;
12445
12446 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12447 /*
12448 * GPIO1 affects both ports, so there's need to pull
12449 * it for single port alone
12450 */
12451 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12452 shmem2_base_path,
12453 phy_index, chip_id);
12454 break;
12455 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12456 /*
12457 * GPIO3's are linked, and so both need to be toggled
12458 * to obtain required 2us pulse.
12459 */
12460 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
12461 shmem2_base_path,
12462 phy_index, chip_id);
12463 break;
12464 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12465 rc = -EINVAL;
12466 break;
12467 default:
12468 DP(NETIF_MSG_LINK,
12469 "ext_phy 0x%x common init not required\n",
12470 ext_phy_type);
12471 break;
12472 }
12473
12474 if (rc != 0)
12475 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12476 " Port %d\n",
12477 0);
12478 return rc;
12479 }
12480
12481 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12482 u32 shmem2_base_path[], u32 chip_id)
12483 {
12484 int rc = 0;
12485 u32 phy_ver, val;
12486 u8 phy_index = 0;
12487 u32 ext_phy_type, ext_phy_config;
12488 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12489 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12490 DP(NETIF_MSG_LINK, "Begin common phy init\n");
12491 if (CHIP_IS_E3(bp)) {
12492 /* Enable EPIO */
12493 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12494 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12495 }
12496 /* Check if common init was already done */
12497 phy_ver = REG_RD(bp, shmem_base_path[0] +
12498 offsetof(struct shmem_region,
12499 port_mb[PORT_0].ext_phy_fw_version));
12500 if (phy_ver) {
12501 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12502 phy_ver);
12503 return 0;
12504 }
12505
12506 /* Read the ext_phy_type for arbitrary port(0) */
12507 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12508 phy_index++) {
12509 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12510 shmem_base_path[0],
12511 phy_index, 0);
12512 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12513 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12514 shmem2_base_path,
12515 phy_index, ext_phy_type,
12516 chip_id);
12517 }
12518 return rc;
12519 }
12520
12521 static void bnx2x_check_over_curr(struct link_params *params,
12522 struct link_vars *vars)
12523 {
12524 struct bnx2x *bp = params->bp;
12525 u32 cfg_pin;
12526 u8 port = params->port;
12527 u32 pin_val;
12528
12529 cfg_pin = (REG_RD(bp, params->shmem_base +
12530 offsetof(struct shmem_region,
12531 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12532 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12533 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12534
12535 /* Ignore check if no external input PIN available */
12536 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12537 return;
12538
12539 if (!pin_val) {
12540 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12541 netdev_err(bp->dev, "Error: Power fault on Port %d has"
12542 " been detected and the power to "
12543 "that SFP+ module has been removed"
12544 " to prevent failure of the card."
12545 " Please remove the SFP+ module and"
12546 " restart the system to clear this"
12547 " error.\n",
12548 params->port);
12549 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12550 }
12551 } else
12552 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12553 }
12554
12555 static void bnx2x_analyze_link_error(struct link_params *params,
12556 struct link_vars *vars, u32 lss_status)
12557 {
12558 struct bnx2x *bp = params->bp;
12559 /* Compare new value with previous value */
12560 u8 led_mode;
12561 u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12562
12563 if ((lss_status ^ half_open_conn) == 0)
12564 return;
12565
12566 /* If values differ */
12567 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12568 half_open_conn, lss_status);
12569
12570 /*
12571 * a. Update shmem->link_status accordingly
12572 * b. Update link_vars->link_up
12573 */
12574 if (lss_status) {
12575 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12576 vars->link_status &= ~LINK_STATUS_LINK_UP;
12577 vars->link_up = 0;
12578 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12579 /*
12580 * Set LED mode to off since the PHY doesn't know about these
12581 * errors
12582 */
12583 led_mode = LED_MODE_OFF;
12584 } else {
12585 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12586 vars->link_status |= LINK_STATUS_LINK_UP;
12587 vars->link_up = 1;
12588 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12589 led_mode = LED_MODE_OPER;
12590 }
12591 /* Update the LED according to the link state */
12592 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12593
12594 /* Update link status in the shared memory */
12595 bnx2x_update_mng(params, vars->link_status);
12596
12597 /* C. Trigger General Attention */
12598 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12599 bnx2x_notify_link_changed(bp);
12600 }
12601
12602 /******************************************************************************
12603 * Description:
12604 * This function checks for half opened connection change indication.
12605 * When such change occurs, it calls the bnx2x_analyze_link_error
12606 * to check if Remote Fault is set or cleared. Reception of remote fault
12607 * status message in the MAC indicates that the peer's MAC has detected
12608 * a fault, for example, due to break in the TX side of fiber.
12609 *
12610 ******************************************************************************/
12611 static void bnx2x_check_half_open_conn(struct link_params *params,
12612 struct link_vars *vars)
12613 {
12614 struct bnx2x *bp = params->bp;
12615 u32 lss_status = 0;
12616 u32 mac_base;
12617 /* In case link status is physically up @ 10G do */
12618 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12619 return;
12620
12621 if (CHIP_IS_E3(bp) &&
12622 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12623 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12624 /* Check E3 XMAC */
12625 /*
12626 * Note that link speed cannot be queried here, since it may be
12627 * zero while link is down. In case UMAC is active, LSS will
12628 * simply not be set
12629 */
12630 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12631
12632 /* Clear stick bits (Requires rising edge) */
12633 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12634 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12635 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12636 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12637 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12638 lss_status = 1;
12639
12640 bnx2x_analyze_link_error(params, vars, lss_status);
12641 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12642 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12643 /* Check E1X / E2 BMAC */
12644 u32 lss_status_reg;
12645 u32 wb_data[2];
12646 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12647 NIG_REG_INGRESS_BMAC0_MEM;
12648 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12649 if (CHIP_IS_E2(bp))
12650 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12651 else
12652 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12653
12654 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12655 lss_status = (wb_data[0] > 0);
12656
12657 bnx2x_analyze_link_error(params, vars, lss_status);
12658 }
12659 }
12660
12661 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12662 {
12663 struct bnx2x *bp = params->bp;
12664 u16 phy_idx;
12665 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12666 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12667 bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12668 bnx2x_check_half_open_conn(params, vars);
12669 break;
12670 }
12671 }
12672
12673 if (CHIP_IS_E3(bp)) {
12674 struct bnx2x_phy *phy = &params->phy[INT_PHY];
12675 bnx2x_set_aer_mmd(params, phy);
12676 bnx2x_check_over_curr(params, vars);
12677 bnx2x_warpcore_config_runtime(phy, params, vars);
12678 }
12679
12680 }
12681
12682 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12683 {
12684 u8 phy_index;
12685 struct bnx2x_phy phy;
12686 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12687 phy_index++) {
12688 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12689 0, &phy) != 0) {
12690 DP(NETIF_MSG_LINK, "populate phy failed\n");
12691 return 0;
12692 }
12693
12694 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12695 return 1;
12696 }
12697 return 0;
12698 }
12699
12700 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12701 u32 shmem_base,
12702 u32 shmem2_base,
12703 u8 port)
12704 {
12705 u8 phy_index, fan_failure_det_req = 0;
12706 struct bnx2x_phy phy;
12707 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12708 phy_index++) {
12709 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12710 port, &phy)
12711 != 0) {
12712 DP(NETIF_MSG_LINK, "populate phy failed\n");
12713 return 0;
12714 }
12715 fan_failure_det_req |= (phy.flags &
12716 FLAGS_FAN_FAILURE_DET_REQ);
12717 }
12718 return fan_failure_det_req;
12719 }
12720
12721 void bnx2x_hw_reset_phy(struct link_params *params)
12722 {
12723 u8 phy_index;
12724 struct bnx2x *bp = params->bp;
12725 bnx2x_update_mng(params, 0);
12726 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12727 (NIG_MASK_XGXS0_LINK_STATUS |
12728 NIG_MASK_XGXS0_LINK10G |
12729 NIG_MASK_SERDES0_LINK_STATUS |
12730 NIG_MASK_MI_INT));
12731
12732 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12733 phy_index++) {
12734 if (params->phy[phy_index].hw_reset) {
12735 params->phy[phy_index].hw_reset(
12736 &params->phy[phy_index],
12737 params);
12738 params->phy[phy_index] = phy_null;
12739 }
12740 }
12741 }
12742
12743 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12744 u32 chip_id, u32 shmem_base, u32 shmem2_base,
12745 u8 port)
12746 {
12747 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12748 u32 val;
12749 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12750 if (CHIP_IS_E3(bp)) {
12751 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12752 shmem_base,
12753 port,
12754 &gpio_num,
12755 &gpio_port) != 0)
12756 return;
12757 } else {
12758 struct bnx2x_phy phy;
12759 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12760 phy_index++) {
12761 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12762 shmem2_base, port, &phy)
12763 != 0) {
12764 DP(NETIF_MSG_LINK, "populate phy failed\n");
12765 return;
12766 }
12767 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12768 gpio_num = MISC_REGISTERS_GPIO_3;
12769 gpio_port = port;
12770 break;
12771 }
12772 }
12773 }
12774
12775 if (gpio_num == 0xff)
12776 return;
12777
12778 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12779 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12780
12781 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12782 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12783 gpio_port ^= (swap_val && swap_override);
12784
12785 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12786 (gpio_num + (gpio_port << 2));
12787
12788 sync_offset = shmem_base +
12789 offsetof(struct shmem_region,
12790 dev_info.port_hw_config[port].aeu_int_mask);
12791 REG_WR(bp, sync_offset, vars->aeu_int_mask);
12792
12793 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12794 gpio_num, gpio_port, vars->aeu_int_mask);
12795
12796 if (port == 0)
12797 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12798 else
12799 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12800
12801 /* Open appropriate AEU for interrupts */
12802 aeu_mask = REG_RD(bp, offset);
12803 aeu_mask |= vars->aeu_int_mask;
12804 REG_WR(bp, offset, aeu_mask);
12805
12806 /* Enable the GPIO to trigger interrupt */
12807 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12808 val |= 1 << (gpio_num + (gpio_port << 2));
12809 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12810 }