drivers/net/wireless/iwlwifi/iwl-io.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  19  *
  20  * The full GNU General Public License is included in this distribution in the
  21  * file called LICENSE.
  22  *
  23  * Contact Information:
  24  *  Intel Linux Wireless <ilw@linux.intel.com>
  25  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26  *
  27  *****************************************************************************/
  28 #include <linux/delay.h>
  29 #include <linux/device.h>
  30
  31 #include "iwl-io.h"
  32 #include"iwl-csr.h"
  33 #include "iwl-debug.h"
  34
  35 #define IWL_POLL_INTERVAL 10    /* microseconds */
  36
  37 static inline void __iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask)
  38 {
  39         iwl_write32(bus, reg, iwl_read32(bus, reg) | mask);
  40 }
  41
  42 static inline void __iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask)
  43 {
  44         iwl_write32(bus, reg, iwl_read32(bus, reg) & ~mask);
  45 }
  46
  47 void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask)
  48 {
  49         unsigned long flags;
  50
  51         spin_lock_irqsave(&bus->reg_lock, flags);
  52         __iwl_set_bit(bus, reg, mask);
  53         spin_unlock_irqrestore(&bus->reg_lock, flags);
  54 }
  55
  56 void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask)
  57 {
  58         unsigned long flags;
  59
  60         spin_lock_irqsave(&bus->reg_lock, flags);
  61         __iwl_clear_bit(bus, reg, mask);
  62         spin_unlock_irqrestore(&bus->reg_lock, flags);
  63 }
  64
  65 int iwl_poll_bit(struct iwl_bus *bus, u32 addr,
  66                  u32 bits, u32 mask, int timeout)
  67 {
  68         int t = 0;
  69
  70         do {
  71                 if ((iwl_read32(bus, addr) & mask) == (bits & mask))
  72                         return t;
  73                 udelay(IWL_POLL_INTERVAL);
  74                 t += IWL_POLL_INTERVAL;
  75         } while (t < timeout);
  76
  77         return -ETIMEDOUT;
  78 }
  79
  80 int iwl_grab_nic_access_silent(struct iwl_bus *bus)
  81 {
  82         int ret;
  83
  84         lockdep_assert_held(&bus->reg_lock);
  85
  86         /* this bit wakes up the NIC */
  87         __iwl_set_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  88
  89         /*
  90          * These bits say the device is running, and should keep running for
  91          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
  92          * but they do not indicate that embedded SRAM is restored yet;
  93          * 3945 and 4965 have volatile SRAM, and must save/restore contents
  94          * to/from host DRAM when sleeping/waking for power-saving.
  95          * Each direction takes approximately 1/4 millisecond; with this
  96          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
  97          * series of register accesses are expected (e.g. reading Event Log),
  98          * to keep device from sleeping.
  99          *
 100          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 101          * SRAM is okay/restored.  We don't check that here because this call
 102          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 103          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 104          *
 105          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 106          * and do not save/restore SRAM when power cycling.
 107          */
 108         ret = iwl_poll_bit(bus, CSR_GP_CNTRL,
 109                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 110                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 111                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 112         if (ret < 0) {
 113                 iwl_write32(bus, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 114                 return -EIO;
 115         }
 116
 117         return 0;
 118 }
 119
 120 int iwl_grab_nic_access(struct iwl_bus *bus)
 121 {
 122         int ret = iwl_grab_nic_access_silent(bus);
 123         if (ret) {
 124                 u32 val = iwl_read32(bus, CSR_GP_CNTRL);
 125                 IWL_ERR(bus,
 126                         "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
 127         }
 128
 129         return ret;
 130 }
 131
 132 void iwl_release_nic_access(struct iwl_bus *bus)
 133 {
 134         lockdep_assert_held(&bus->reg_lock);
 135         __iwl_clear_bit(bus, CSR_GP_CNTRL,
 136                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 137 }
 138
 139 u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg)
 140 {
 141         u32 value;
 142         unsigned long flags;
 143
 144         spin_lock_irqsave(&bus->reg_lock, flags);
 145         iwl_grab_nic_access(bus);
 146         value = iwl_read32(bus, reg);
 147         iwl_release_nic_access(bus);
 148         spin_unlock_irqrestore(&bus->reg_lock, flags);
 149
 150         return value;
 151 }
 152
 153 void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value)
 154 {
 155         unsigned long flags;
 156
 157         spin_lock_irqsave(&bus->reg_lock, flags);
 158         if (!iwl_grab_nic_access(bus)) {
 159                 iwl_write32(bus, reg, value);
 160                 iwl_release_nic_access(bus);
 161         }
 162         spin_unlock_irqrestore(&bus->reg_lock, flags);
 163 }
 164
 165 int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask,
 166                         int timeout)
 167 {
 168         int t = 0;
 169
 170         do {
 171                 if ((iwl_read_direct32(bus, addr) & mask) == mask)
 172                         return t;
 173                 udelay(IWL_POLL_INTERVAL);
 174                 t += IWL_POLL_INTERVAL;
 175         } while (t < timeout);
 176
 177         return -ETIMEDOUT;
 178 }
 179
 180 static inline u32 __iwl_read_prph(struct iwl_bus *bus, u32 reg)
 181 {
 182         iwl_write32(bus, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
 183         rmb();
 184         return iwl_read32(bus, HBUS_TARG_PRPH_RDAT);
 185 }
 186
 187 static inline void __iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val)
 188 {
 189         iwl_write32(bus, HBUS_TARG_PRPH_WADDR,
 190                     ((addr & 0x0000FFFF) | (3 << 24)));
 191         wmb();
 192         iwl_write32(bus, HBUS_TARG_PRPH_WDAT, val);
 193 }
 194
 195 u32 iwl_read_prph(struct iwl_bus *bus, u32 reg)
 196 {
 197         unsigned long flags;
 198         u32 val;
 199
 200         spin_lock_irqsave(&bus->reg_lock, flags);
 201         iwl_grab_nic_access(bus);
 202         val = __iwl_read_prph(bus, reg);
 203         iwl_release_nic_access(bus);
 204         spin_unlock_irqrestore(&bus->reg_lock, flags);
 205         return val;
 206 }
 207
 208 void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val)
 209 {
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&bus->reg_lock, flags);
 213         if (!iwl_grab_nic_access(bus)) {
 214                 __iwl_write_prph(bus, addr, val);
 215                 iwl_release_nic_access(bus);
 216         }
 217         spin_unlock_irqrestore(&bus->reg_lock, flags);
 218 }
 219
 220 void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask)
 221 {
 222         unsigned long flags;
 223
 224         spin_lock_irqsave(&bus->reg_lock, flags);
 225         iwl_grab_nic_access(bus);
 226         __iwl_write_prph(bus, reg, __iwl_read_prph(bus, reg) | mask);
 227         iwl_release_nic_access(bus);
 228         spin_unlock_irqrestore(&bus->reg_lock, flags);
 229 }
 230
 231 void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg,
 232                             u32 bits, u32 mask)
 233 {
 234         unsigned long flags;
 235
 236         spin_lock_irqsave(&bus->reg_lock, flags);
 237         iwl_grab_nic_access(bus);
 238         __iwl_write_prph(bus, reg,
 239                          (__iwl_read_prph(bus, reg) & mask) | bits);
 240         iwl_release_nic_access(bus);
 241         spin_unlock_irqrestore(&bus->reg_lock, flags);
 242 }
 243
 244 void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask)
 245 {
 246         unsigned long flags;
 247         u32 val;
 248
 249         spin_lock_irqsave(&bus->reg_lock, flags);
 250         iwl_grab_nic_access(bus);
 251         val = __iwl_read_prph(bus, reg);
 252         __iwl_write_prph(bus, reg, (val & ~mask));
 253         iwl_release_nic_access(bus);
 254         spin_unlock_irqrestore(&bus->reg_lock, flags);
 255 }
 256
 257 void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr,
 258                               void *buf, int words)
 259 {
 260         unsigned long flags;
 261         int offs;
 262         u32 *vals = buf;
 263
 264         spin_lock_irqsave(&bus->reg_lock, flags);
 265         iwl_grab_nic_access(bus);
 266
 267         iwl_write32(bus, HBUS_TARG_MEM_RADDR, addr);
 268         rmb();
 269
 270         for (offs = 0; offs < words; offs++)
 271                 vals[offs] = iwl_read32(bus, HBUS_TARG_MEM_RDAT);
 272
 273         iwl_release_nic_access(bus);
 274         spin_unlock_irqrestore(&bus->reg_lock, flags);
 275 }
 276
 277 u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr)
 278 {
 279         u32 value;
 280
 281         _iwl_read_targ_mem_words(bus, addr, &value, 1);
 282
 283         return value;
 284 }
 285
 286 int _iwl_write_targ_mem_words(struct iwl_bus *bus, u32 addr,
 287                                 void *buf, int words)
 288 {
 289         unsigned long flags;
 290         int offs, result = 0;
 291         u32 *vals = buf;
 292
 293         spin_lock_irqsave(&bus->reg_lock, flags);
 294         if (!iwl_grab_nic_access(bus)) {
 295                 iwl_write32(bus, HBUS_TARG_MEM_WADDR, addr);
 296                 wmb();
 297
 298                 for (offs = 0; offs < words; offs++)
 299                         iwl_write32(bus, HBUS_TARG_MEM_WDAT, vals[offs]);
 300                 iwl_release_nic_access(bus);
 301         } else
 302                 result = -EBUSY;
 303         spin_unlock_irqrestore(&bus->reg_lock, flags);
 304
 305         return result;
 306 }
 307
 308 int iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val)
 309 {
 310         return _iwl_write_targ_mem_words(bus, addr, &val, 1);
 311 }