?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
xhci: Clean up 32-bit build warnings.
[zen-stable.git] / arch / x86 / kvm / vmx.c
blob579a0b51696ac560b1768ae445bb8f2084172f8c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42 #include <asm/perf_event.h>
43
44 #include "trace.h"
45
46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 #define __ex_clear(x, reg) \
48 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49
50 MODULE_AUTHOR("Qumranet");
51 MODULE_LICENSE("GPL");
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
74
75 static int __read_mostly fasteoi = 1;
76 module_param(fasteoi, bool, S_IRUGO);
77
78 /*
79 * If nested=1, nested virtualization is supported, i.e., guests may use
80 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
81 * use VMX instructions.
82 */
83 static int __read_mostly nested = 0;
84 module_param(nested, bool, S_IRUGO);
85
86 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
87 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
88 #define KVM_GUEST_CR0_MASK \
89 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
90 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
91 (X86_CR0_WP | X86_CR0_NE)
92 #define KVM_VM_CR0_ALWAYS_ON \
93 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
94 #define KVM_CR4_GUEST_OWNED_BITS \
95 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
96 | X86_CR4_OSXMMEXCPT)
97
98 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
99 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100
101 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
102
103 /*
104 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
105 * ple_gap: upper bound on the amount of time between two successive
106 * executions of PAUSE in a loop. Also indicate if ple enabled.
107 * According to test, this time is usually smaller than 128 cycles.
108 * ple_window: upper bound on the amount of time a guest is allowed to execute
109 * in a PAUSE loop. Tests indicate that most spinlocks are held for
110 * less than 2^12 cycles
111 * Time is measured based on a counter that runs at the same rate as the TSC,
112 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 */
114 #define KVM_VMX_DEFAULT_PLE_GAP 128
115 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
116 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
117 module_param(ple_gap, int, S_IRUGO);
118
119 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
120 module_param(ple_window, int, S_IRUGO);
121
122 #define NR_AUTOLOAD_MSRS 8
123 #define VMCS02_POOL_SIZE 1
124
125 struct vmcs {
126 u32 revision_id;
127 u32 abort;
128 char data[0];
129 };
130
131 /*
132 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
133 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
134 * loaded on this CPU (so we can clear them if the CPU goes down).
135 */
136 struct loaded_vmcs {
137 struct vmcs *vmcs;
138 int cpu;
139 int launched;
140 struct list_head loaded_vmcss_on_cpu_link;
141 };
142
143 struct shared_msr_entry {
144 unsigned index;
145 u64 data;
146 u64 mask;
147 };
148
149 /*
150 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
151 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
152 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
153 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
154 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
155 * More than one of these structures may exist, if L1 runs multiple L2 guests.
156 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
157 * underlying hardware which will be used to run L2.
158 * This structure is packed to ensure that its layout is identical across
159 * machines (necessary for live migration).
160 * If there are changes in this struct, VMCS12_REVISION must be changed.
161 */
162 typedef u64 natural_width;
163 struct __packed vmcs12 {
164 /* According to the Intel spec, a VMCS region must start with the
165 * following two fields. Then follow implementation-specific data.
166 */
167 u32 revision_id;
168 u32 abort;
169
170 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
171 u32 padding[7]; /* room for future expansion */
172
173 u64 io_bitmap_a;
174 u64 io_bitmap_b;
175 u64 msr_bitmap;
176 u64 vm_exit_msr_store_addr;
177 u64 vm_exit_msr_load_addr;
178 u64 vm_entry_msr_load_addr;
179 u64 tsc_offset;
180 u64 virtual_apic_page_addr;
181 u64 apic_access_addr;
182 u64 ept_pointer;
183 u64 guest_physical_address;
184 u64 vmcs_link_pointer;
185 u64 guest_ia32_debugctl;
186 u64 guest_ia32_pat;
187 u64 guest_ia32_efer;
188 u64 guest_ia32_perf_global_ctrl;
189 u64 guest_pdptr0;
190 u64 guest_pdptr1;
191 u64 guest_pdptr2;
192 u64 guest_pdptr3;
193 u64 host_ia32_pat;
194 u64 host_ia32_efer;
195 u64 host_ia32_perf_global_ctrl;
196 u64 padding64[8]; /* room for future expansion */
197 /*
198 * To allow migration of L1 (complete with its L2 guests) between
199 * machines of different natural widths (32 or 64 bit), we cannot have
200 * unsigned long fields with no explict size. We use u64 (aliased
201 * natural_width) instead. Luckily, x86 is little-endian.
202 */
203 natural_width cr0_guest_host_mask;
204 natural_width cr4_guest_host_mask;
205 natural_width cr0_read_shadow;
206 natural_width cr4_read_shadow;
207 natural_width cr3_target_value0;
208 natural_width cr3_target_value1;
209 natural_width cr3_target_value2;
210 natural_width cr3_target_value3;
211 natural_width exit_qualification;
212 natural_width guest_linear_address;
213 natural_width guest_cr0;
214 natural_width guest_cr3;
215 natural_width guest_cr4;
216 natural_width guest_es_base;
217 natural_width guest_cs_base;
218 natural_width guest_ss_base;
219 natural_width guest_ds_base;
220 natural_width guest_fs_base;
221 natural_width guest_gs_base;
222 natural_width guest_ldtr_base;
223 natural_width guest_tr_base;
224 natural_width guest_gdtr_base;
225 natural_width guest_idtr_base;
226 natural_width guest_dr7;
227 natural_width guest_rsp;
228 natural_width guest_rip;
229 natural_width guest_rflags;
230 natural_width guest_pending_dbg_exceptions;
231 natural_width guest_sysenter_esp;
232 natural_width guest_sysenter_eip;
233 natural_width host_cr0;
234 natural_width host_cr3;
235 natural_width host_cr4;
236 natural_width host_fs_base;
237 natural_width host_gs_base;
238 natural_width host_tr_base;
239 natural_width host_gdtr_base;
240 natural_width host_idtr_base;
241 natural_width host_ia32_sysenter_esp;
242 natural_width host_ia32_sysenter_eip;
243 natural_width host_rsp;
244 natural_width host_rip;
245 natural_width paddingl[8]; /* room for future expansion */
246 u32 pin_based_vm_exec_control;
247 u32 cpu_based_vm_exec_control;
248 u32 exception_bitmap;
249 u32 page_fault_error_code_mask;
250 u32 page_fault_error_code_match;
251 u32 cr3_target_count;
252 u32 vm_exit_controls;
253 u32 vm_exit_msr_store_count;
254 u32 vm_exit_msr_load_count;
255 u32 vm_entry_controls;
256 u32 vm_entry_msr_load_count;
257 u32 vm_entry_intr_info_field;
258 u32 vm_entry_exception_error_code;
259 u32 vm_entry_instruction_len;
260 u32 tpr_threshold;
261 u32 secondary_vm_exec_control;
262 u32 vm_instruction_error;
263 u32 vm_exit_reason;
264 u32 vm_exit_intr_info;
265 u32 vm_exit_intr_error_code;
266 u32 idt_vectoring_info_field;
267 u32 idt_vectoring_error_code;
268 u32 vm_exit_instruction_len;
269 u32 vmx_instruction_info;
270 u32 guest_es_limit;
271 u32 guest_cs_limit;
272 u32 guest_ss_limit;
273 u32 guest_ds_limit;
274 u32 guest_fs_limit;
275 u32 guest_gs_limit;
276 u32 guest_ldtr_limit;
277 u32 guest_tr_limit;
278 u32 guest_gdtr_limit;
279 u32 guest_idtr_limit;
280 u32 guest_es_ar_bytes;
281 u32 guest_cs_ar_bytes;
282 u32 guest_ss_ar_bytes;
283 u32 guest_ds_ar_bytes;
284 u32 guest_fs_ar_bytes;
285 u32 guest_gs_ar_bytes;
286 u32 guest_ldtr_ar_bytes;
287 u32 guest_tr_ar_bytes;
288 u32 guest_interruptibility_info;
289 u32 guest_activity_state;
290 u32 guest_sysenter_cs;
291 u32 host_ia32_sysenter_cs;
292 u32 padding32[8]; /* room for future expansion */
293 u16 virtual_processor_id;
294 u16 guest_es_selector;
295 u16 guest_cs_selector;
296 u16 guest_ss_selector;
297 u16 guest_ds_selector;
298 u16 guest_fs_selector;
299 u16 guest_gs_selector;
300 u16 guest_ldtr_selector;
301 u16 guest_tr_selector;
302 u16 host_es_selector;
303 u16 host_cs_selector;
304 u16 host_ss_selector;
305 u16 host_ds_selector;
306 u16 host_fs_selector;
307 u16 host_gs_selector;
308 u16 host_tr_selector;
309 };
310
311 /*
312 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
313 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
314 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
315 */
316 #define VMCS12_REVISION 0x11e57ed0
317
318 /*
319 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
320 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
321 * current implementation, 4K are reserved to avoid future complications.
322 */
323 #define VMCS12_SIZE 0x1000
324
325 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
326 struct vmcs02_list {
327 struct list_head list;
328 gpa_t vmptr;
329 struct loaded_vmcs vmcs02;
330 };
331
332 /*
333 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
334 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
335 */
336 struct nested_vmx {
337 /* Has the level1 guest done vmxon? */
338 bool vmxon;
339
340 /* The guest-physical address of the current VMCS L1 keeps for L2 */
341 gpa_t current_vmptr;
342 /* The host-usable pointer to the above */
343 struct page *current_vmcs12_page;
344 struct vmcs12 *current_vmcs12;
345
346 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
347 struct list_head vmcs02_pool;
348 int vmcs02_num;
349 u64 vmcs01_tsc_offset;
350 /* L2 must run next, and mustn't decide to exit to L1. */
351 bool nested_run_pending;
352 /*
353 * Guest pages referred to in vmcs02 with host-physical pointers, so
354 * we must keep them pinned while L2 runs.
355 */
356 struct page *apic_access_page;
357 };
358
359 struct vcpu_vmx {
360 struct kvm_vcpu vcpu;
361 unsigned long host_rsp;
362 u8 fail;
363 u8 cpl;
364 bool nmi_known_unmasked;
365 u32 exit_intr_info;
366 u32 idt_vectoring_info;
367 ulong rflags;
368 struct shared_msr_entry *guest_msrs;
369 int nmsrs;
370 int save_nmsrs;
371 #ifdef CONFIG_X86_64
372 u64 msr_host_kernel_gs_base;
373 u64 msr_guest_kernel_gs_base;
374 #endif
375 /*
376 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
377 * non-nested (L1) guest, it always points to vmcs01. For a nested
378 * guest (L2), it points to a different VMCS.
379 */
380 struct loaded_vmcs vmcs01;
381 struct loaded_vmcs *loaded_vmcs;
382 bool __launched; /* temporary, used in vmx_vcpu_run */
383 struct msr_autoload {
384 unsigned nr;
385 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
386 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
387 } msr_autoload;
388 struct {
389 int loaded;
390 u16 fs_sel, gs_sel, ldt_sel;
391 int gs_ldt_reload_needed;
392 int fs_reload_needed;
393 } host_state;
394 struct {
395 int vm86_active;
396 ulong save_rflags;
397 struct kvm_save_segment {
398 u16 selector;
399 unsigned long base;
400 u32 limit;
401 u32 ar;
402 } tr, es, ds, fs, gs;
403 } rmode;
404 struct {
405 u32 bitmask; /* 4 bits per segment (1 bit per field) */
406 struct kvm_save_segment seg[8];
407 } segment_cache;
408 int vpid;
409 bool emulation_required;
410
411 /* Support for vnmi-less CPUs */
412 int soft_vnmi_blocked;
413 ktime_t entry_time;
414 s64 vnmi_blocked_time;
415 u32 exit_reason;
416
417 bool rdtscp_enabled;
418
419 /* Support for a guest hypervisor (nested VMX) */
420 struct nested_vmx nested;
421 };
422
423 enum segment_cache_field {
424 SEG_FIELD_SEL = 0,
425 SEG_FIELD_BASE = 1,
426 SEG_FIELD_LIMIT = 2,
427 SEG_FIELD_AR = 3,
428
429 SEG_FIELD_NR = 4
430 };
431
432 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
433 {
434 return container_of(vcpu, struct vcpu_vmx, vcpu);
435 }
436
437 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
438 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
439 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
440 [number##_HIGH] = VMCS12_OFFSET(name)+4
441
442 static unsigned short vmcs_field_to_offset_table[] = {
443 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
444 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
445 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
446 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
447 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
448 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
449 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
450 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
451 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
452 FIELD(HOST_ES_SELECTOR, host_es_selector),
453 FIELD(HOST_CS_SELECTOR, host_cs_selector),
454 FIELD(HOST_SS_SELECTOR, host_ss_selector),
455 FIELD(HOST_DS_SELECTOR, host_ds_selector),
456 FIELD(HOST_FS_SELECTOR, host_fs_selector),
457 FIELD(HOST_GS_SELECTOR, host_gs_selector),
458 FIELD(HOST_TR_SELECTOR, host_tr_selector),
459 FIELD64(IO_BITMAP_A, io_bitmap_a),
460 FIELD64(IO_BITMAP_B, io_bitmap_b),
461 FIELD64(MSR_BITMAP, msr_bitmap),
462 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
463 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
464 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
465 FIELD64(TSC_OFFSET, tsc_offset),
466 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
467 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
468 FIELD64(EPT_POINTER, ept_pointer),
469 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
470 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
471 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
472 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
473 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
474 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
475 FIELD64(GUEST_PDPTR0, guest_pdptr0),
476 FIELD64(GUEST_PDPTR1, guest_pdptr1),
477 FIELD64(GUEST_PDPTR2, guest_pdptr2),
478 FIELD64(GUEST_PDPTR3, guest_pdptr3),
479 FIELD64(HOST_IA32_PAT, host_ia32_pat),
480 FIELD64(HOST_IA32_EFER, host_ia32_efer),
481 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
482 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
483 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
484 FIELD(EXCEPTION_BITMAP, exception_bitmap),
485 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
486 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
487 FIELD(CR3_TARGET_COUNT, cr3_target_count),
488 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
489 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
490 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
491 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
492 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
493 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
494 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
495 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
496 FIELD(TPR_THRESHOLD, tpr_threshold),
497 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
498 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
499 FIELD(VM_EXIT_REASON, vm_exit_reason),
500 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
501 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
502 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
503 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
504 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
505 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
506 FIELD(GUEST_ES_LIMIT, guest_es_limit),
507 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
508 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
509 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
510 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
511 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
512 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
513 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
514 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
515 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
516 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
517 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
518 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
519 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
520 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
521 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
522 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
523 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
524 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
525 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
526 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
527 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
528 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
529 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
530 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
531 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
532 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
533 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
534 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
535 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
536 FIELD(EXIT_QUALIFICATION, exit_qualification),
537 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
538 FIELD(GUEST_CR0, guest_cr0),
539 FIELD(GUEST_CR3, guest_cr3),
540 FIELD(GUEST_CR4, guest_cr4),
541 FIELD(GUEST_ES_BASE, guest_es_base),
542 FIELD(GUEST_CS_BASE, guest_cs_base),
543 FIELD(GUEST_SS_BASE, guest_ss_base),
544 FIELD(GUEST_DS_BASE, guest_ds_base),
545 FIELD(GUEST_FS_BASE, guest_fs_base),
546 FIELD(GUEST_GS_BASE, guest_gs_base),
547 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
548 FIELD(GUEST_TR_BASE, guest_tr_base),
549 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
550 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
551 FIELD(GUEST_DR7, guest_dr7),
552 FIELD(GUEST_RSP, guest_rsp),
553 FIELD(GUEST_RIP, guest_rip),
554 FIELD(GUEST_RFLAGS, guest_rflags),
555 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
556 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
557 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
558 FIELD(HOST_CR0, host_cr0),
559 FIELD(HOST_CR3, host_cr3),
560 FIELD(HOST_CR4, host_cr4),
561 FIELD(HOST_FS_BASE, host_fs_base),
562 FIELD(HOST_GS_BASE, host_gs_base),
563 FIELD(HOST_TR_BASE, host_tr_base),
564 FIELD(HOST_GDTR_BASE, host_gdtr_base),
565 FIELD(HOST_IDTR_BASE, host_idtr_base),
566 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
567 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
568 FIELD(HOST_RSP, host_rsp),
569 FIELD(HOST_RIP, host_rip),
570 };
571 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
572
573 static inline short vmcs_field_to_offset(unsigned long field)
574 {
575 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
576 return -1;
577 return vmcs_field_to_offset_table[field];
578 }
579
580 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
581 {
582 return to_vmx(vcpu)->nested.current_vmcs12;
583 }
584
585 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
586 {
587 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
588 if (is_error_page(page)) {
589 kvm_release_page_clean(page);
590 return NULL;
591 }
592 return page;
593 }
594
595 static void nested_release_page(struct page *page)
596 {
597 kvm_release_page_dirty(page);
598 }
599
600 static void nested_release_page_clean(struct page *page)
601 {
602 kvm_release_page_clean(page);
603 }
604
605 static u64 construct_eptp(unsigned long root_hpa);
606 static void kvm_cpu_vmxon(u64 addr);
607 static void kvm_cpu_vmxoff(void);
608 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
609 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
610
611 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
612 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
613 /*
614 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
615 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
616 */
617 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
618 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
619
620 static unsigned long *vmx_io_bitmap_a;
621 static unsigned long *vmx_io_bitmap_b;
622 static unsigned long *vmx_msr_bitmap_legacy;
623 static unsigned long *vmx_msr_bitmap_longmode;
624
625 static bool cpu_has_load_ia32_efer;
626 static bool cpu_has_load_perf_global_ctrl;
627
628 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
629 static DEFINE_SPINLOCK(vmx_vpid_lock);
630
631 static struct vmcs_config {
632 int size;
633 int order;
634 u32 revision_id;
635 u32 pin_based_exec_ctrl;
636 u32 cpu_based_exec_ctrl;
637 u32 cpu_based_2nd_exec_ctrl;
638 u32 vmexit_ctrl;
639 u32 vmentry_ctrl;
640 } vmcs_config;
641
642 static struct vmx_capability {
643 u32 ept;
644 u32 vpid;
645 } vmx_capability;
646
647 #define VMX_SEGMENT_FIELD(seg) \
648 [VCPU_SREG_##seg] = { \
649 .selector = GUEST_##seg##_SELECTOR, \
650 .base = GUEST_##seg##_BASE, \
651 .limit = GUEST_##seg##_LIMIT, \
652 .ar_bytes = GUEST_##seg##_AR_BYTES, \
653 }
654
655 static struct kvm_vmx_segment_field {
656 unsigned selector;
657 unsigned base;
658 unsigned limit;
659 unsigned ar_bytes;
660 } kvm_vmx_segment_fields[] = {
661 VMX_SEGMENT_FIELD(CS),
662 VMX_SEGMENT_FIELD(DS),
663 VMX_SEGMENT_FIELD(ES),
664 VMX_SEGMENT_FIELD(FS),
665 VMX_SEGMENT_FIELD(GS),
666 VMX_SEGMENT_FIELD(SS),
667 VMX_SEGMENT_FIELD(TR),
668 VMX_SEGMENT_FIELD(LDTR),
669 };
670
671 static u64 host_efer;
672
673 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
674
675 /*
676 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
677 * away by decrementing the array size.
678 */
679 static const u32 vmx_msr_index[] = {
680 #ifdef CONFIG_X86_64
681 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
682 #endif
683 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
684 };
685 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
686
687 static inline bool is_page_fault(u32 intr_info)
688 {
689 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
690 INTR_INFO_VALID_MASK)) ==
691 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
692 }
693
694 static inline bool is_no_device(u32 intr_info)
695 {
696 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
697 INTR_INFO_VALID_MASK)) ==
698 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
699 }
700
701 static inline bool is_invalid_opcode(u32 intr_info)
702 {
703 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
704 INTR_INFO_VALID_MASK)) ==
705 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
706 }
707
708 static inline bool is_external_interrupt(u32 intr_info)
709 {
710 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
711 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
712 }
713
714 static inline bool is_machine_check(u32 intr_info)
715 {
716 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
717 INTR_INFO_VALID_MASK)) ==
718 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
719 }
720
721 static inline bool cpu_has_vmx_msr_bitmap(void)
722 {
723 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
724 }
725
726 static inline bool cpu_has_vmx_tpr_shadow(void)
727 {
728 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
729 }
730
731 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
732 {
733 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
734 }
735
736 static inline bool cpu_has_secondary_exec_ctrls(void)
737 {
738 return vmcs_config.cpu_based_exec_ctrl &
739 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
740 }
741
742 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
743 {
744 return vmcs_config.cpu_based_2nd_exec_ctrl &
745 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
746 }
747
748 static inline bool cpu_has_vmx_flexpriority(void)
749 {
750 return cpu_has_vmx_tpr_shadow() &&
751 cpu_has_vmx_virtualize_apic_accesses();
752 }
753
754 static inline bool cpu_has_vmx_ept_execute_only(void)
755 {
756 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
757 }
758
759 static inline bool cpu_has_vmx_eptp_uncacheable(void)
760 {
761 return vmx_capability.ept & VMX_EPTP_UC_BIT;
762 }
763
764 static inline bool cpu_has_vmx_eptp_writeback(void)
765 {
766 return vmx_capability.ept & VMX_EPTP_WB_BIT;
767 }
768
769 static inline bool cpu_has_vmx_ept_2m_page(void)
770 {
771 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
772 }
773
774 static inline bool cpu_has_vmx_ept_1g_page(void)
775 {
776 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
777 }
778
779 static inline bool cpu_has_vmx_ept_4levels(void)
780 {
781 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
782 }
783
784 static inline bool cpu_has_vmx_invept_individual_addr(void)
785 {
786 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
787 }
788
789 static inline bool cpu_has_vmx_invept_context(void)
790 {
791 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
792 }
793
794 static inline bool cpu_has_vmx_invept_global(void)
795 {
796 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
797 }
798
799 static inline bool cpu_has_vmx_invvpid_single(void)
800 {
801 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
802 }
803
804 static inline bool cpu_has_vmx_invvpid_global(void)
805 {
806 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
807 }
808
809 static inline bool cpu_has_vmx_ept(void)
810 {
811 return vmcs_config.cpu_based_2nd_exec_ctrl &
812 SECONDARY_EXEC_ENABLE_EPT;
813 }
814
815 static inline bool cpu_has_vmx_unrestricted_guest(void)
816 {
817 return vmcs_config.cpu_based_2nd_exec_ctrl &
818 SECONDARY_EXEC_UNRESTRICTED_GUEST;
819 }
820
821 static inline bool cpu_has_vmx_ple(void)
822 {
823 return vmcs_config.cpu_based_2nd_exec_ctrl &
824 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
825 }
826
827 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
828 {
829 return flexpriority_enabled && irqchip_in_kernel(kvm);
830 }
831
832 static inline bool cpu_has_vmx_vpid(void)
833 {
834 return vmcs_config.cpu_based_2nd_exec_ctrl &
835 SECONDARY_EXEC_ENABLE_VPID;
836 }
837
838 static inline bool cpu_has_vmx_rdtscp(void)
839 {
840 return vmcs_config.cpu_based_2nd_exec_ctrl &
841 SECONDARY_EXEC_RDTSCP;
842 }
843
844 static inline bool cpu_has_virtual_nmis(void)
845 {
846 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
847 }
848
849 static inline bool cpu_has_vmx_wbinvd_exit(void)
850 {
851 return vmcs_config.cpu_based_2nd_exec_ctrl &
852 SECONDARY_EXEC_WBINVD_EXITING;
853 }
854
855 static inline bool report_flexpriority(void)
856 {
857 return flexpriority_enabled;
858 }
859
860 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
861 {
862 return vmcs12->cpu_based_vm_exec_control & bit;
863 }
864
865 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
866 {
867 return (vmcs12->cpu_based_vm_exec_control &
868 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
869 (vmcs12->secondary_vm_exec_control & bit);
870 }
871
872 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
873 struct kvm_vcpu *vcpu)
874 {
875 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
876 }
877
878 static inline bool is_exception(u32 intr_info)
879 {
880 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
881 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
882 }
883
884 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
885 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
886 struct vmcs12 *vmcs12,
887 u32 reason, unsigned long qualification);
888
889 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
890 {
891 int i;
892
893 for (i = 0; i < vmx->nmsrs; ++i)
894 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
895 return i;
896 return -1;
897 }
898
899 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
900 {
901 struct {
902 u64 vpid : 16;
903 u64 rsvd : 48;
904 u64 gva;
905 } operand = { vpid, 0, gva };
906
907 asm volatile (__ex(ASM_VMX_INVVPID)
908 /* CF==1 or ZF==1 --> rc = -1 */
909 "; ja 1f ; ud2 ; 1:"
910 : : "a"(&operand), "c"(ext) : "cc", "memory");
911 }
912
913 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
914 {
915 struct {
916 u64 eptp, gpa;
917 } operand = {eptp, gpa};
918
919 asm volatile (__ex(ASM_VMX_INVEPT)
920 /* CF==1 or ZF==1 --> rc = -1 */
921 "; ja 1f ; ud2 ; 1:\n"
922 : : "a" (&operand), "c" (ext) : "cc", "memory");
923 }
924
925 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
926 {
927 int i;
928
929 i = __find_msr_index(vmx, msr);
930 if (i >= 0)
931 return &vmx->guest_msrs[i];
932 return NULL;
933 }
934
935 static void vmcs_clear(struct vmcs *vmcs)
936 {
937 u64 phys_addr = __pa(vmcs);
938 u8 error;
939
940 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
941 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
942 : "cc", "memory");
943 if (error)
944 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
945 vmcs, phys_addr);
946 }
947
948 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
949 {
950 vmcs_clear(loaded_vmcs->vmcs);
951 loaded_vmcs->cpu = -1;
952 loaded_vmcs->launched = 0;
953 }
954
955 static void vmcs_load(struct vmcs *vmcs)
956 {
957 u64 phys_addr = __pa(vmcs);
958 u8 error;
959
960 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
961 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
962 : "cc", "memory");
963 if (error)
964 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
965 vmcs, phys_addr);
966 }
967
968 static void __loaded_vmcs_clear(void *arg)
969 {
970 struct loaded_vmcs *loaded_vmcs = arg;
971 int cpu = raw_smp_processor_id();
972
973 if (loaded_vmcs->cpu != cpu)
974 return; /* vcpu migration can race with cpu offline */
975 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
976 per_cpu(current_vmcs, cpu) = NULL;
977 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
978 loaded_vmcs_init(loaded_vmcs);
979 }
980
981 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
982 {
983 if (loaded_vmcs->cpu != -1)
984 smp_call_function_single(
985 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
986 }
987
988 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
989 {
990 if (vmx->vpid == 0)
991 return;
992
993 if (cpu_has_vmx_invvpid_single())
994 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
995 }
996
997 static inline void vpid_sync_vcpu_global(void)
998 {
999 if (cpu_has_vmx_invvpid_global())
1000 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1001 }
1002
1003 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1004 {
1005 if (cpu_has_vmx_invvpid_single())
1006 vpid_sync_vcpu_single(vmx);
1007 else
1008 vpid_sync_vcpu_global();
1009 }
1010
1011 static inline void ept_sync_global(void)
1012 {
1013 if (cpu_has_vmx_invept_global())
1014 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1015 }
1016
1017 static inline void ept_sync_context(u64 eptp)
1018 {
1019 if (enable_ept) {
1020 if (cpu_has_vmx_invept_context())
1021 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1022 else
1023 ept_sync_global();
1024 }
1025 }
1026
1027 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1028 {
1029 if (enable_ept) {
1030 if (cpu_has_vmx_invept_individual_addr())
1031 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1032 eptp, gpa);
1033 else
1034 ept_sync_context(eptp);
1035 }
1036 }
1037
1038 static __always_inline unsigned long vmcs_readl(unsigned long field)
1039 {
1040 unsigned long value;
1041
1042 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1043 : "=a"(value) : "d"(field) : "cc");
1044 return value;
1045 }
1046
1047 static __always_inline u16 vmcs_read16(unsigned long field)
1048 {
1049 return vmcs_readl(field);
1050 }
1051
1052 static __always_inline u32 vmcs_read32(unsigned long field)
1053 {
1054 return vmcs_readl(field);
1055 }
1056
1057 static __always_inline u64 vmcs_read64(unsigned long field)
1058 {
1059 #ifdef CONFIG_X86_64
1060 return vmcs_readl(field);
1061 #else
1062 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1063 #endif
1064 }
1065
1066 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1067 {
1068 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1069 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1070 dump_stack();
1071 }
1072
1073 static void vmcs_writel(unsigned long field, unsigned long value)
1074 {
1075 u8 error;
1076
1077 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1078 : "=q"(error) : "a"(value), "d"(field) : "cc");
1079 if (unlikely(error))
1080 vmwrite_error(field, value);
1081 }
1082
1083 static void vmcs_write16(unsigned long field, u16 value)
1084 {
1085 vmcs_writel(field, value);
1086 }
1087
1088 static void vmcs_write32(unsigned long field, u32 value)
1089 {
1090 vmcs_writel(field, value);
1091 }
1092
1093 static void vmcs_write64(unsigned long field, u64 value)
1094 {
1095 vmcs_writel(field, value);
1096 #ifndef CONFIG_X86_64
1097 asm volatile ("");
1098 vmcs_writel(field+1, value >> 32);
1099 #endif
1100 }
1101
1102 static void vmcs_clear_bits(unsigned long field, u32 mask)
1103 {
1104 vmcs_writel(field, vmcs_readl(field) & ~mask);
1105 }
1106
1107 static void vmcs_set_bits(unsigned long field, u32 mask)
1108 {
1109 vmcs_writel(field, vmcs_readl(field) | mask);
1110 }
1111
1112 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1113 {
1114 vmx->segment_cache.bitmask = 0;
1115 }
1116
1117 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1118 unsigned field)
1119 {
1120 bool ret;
1121 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1122
1123 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1124 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1125 vmx->segment_cache.bitmask = 0;
1126 }
1127 ret = vmx->segment_cache.bitmask & mask;
1128 vmx->segment_cache.bitmask |= mask;
1129 return ret;
1130 }
1131
1132 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1133 {
1134 u16 *p = &vmx->segment_cache.seg[seg].selector;
1135
1136 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1137 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1138 return *p;
1139 }
1140
1141 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1142 {
1143 ulong *p = &vmx->segment_cache.seg[seg].base;
1144
1145 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1146 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1147 return *p;
1148 }
1149
1150 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1151 {
1152 u32 *p = &vmx->segment_cache.seg[seg].limit;
1153
1154 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1155 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1156 return *p;
1157 }
1158
1159 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1160 {
1161 u32 *p = &vmx->segment_cache.seg[seg].ar;
1162
1163 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1164 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1165 return *p;
1166 }
1167
1168 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1169 {
1170 u32 eb;
1171
1172 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1173 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1174 if ((vcpu->guest_debug &
1175 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1176 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1177 eb |= 1u << BP_VECTOR;
1178 if (to_vmx(vcpu)->rmode.vm86_active)
1179 eb = ~0;
1180 if (enable_ept)
1181 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1182 if (vcpu->fpu_active)
1183 eb &= ~(1u << NM_VECTOR);
1184
1185 /* When we are running a nested L2 guest and L1 specified for it a
1186 * certain exception bitmap, we must trap the same exceptions and pass
1187 * them to L1. When running L2, we will only handle the exceptions
1188 * specified above if L1 did not want them.
1189 */
1190 if (is_guest_mode(vcpu))
1191 eb |= get_vmcs12(vcpu)->exception_bitmap;
1192
1193 vmcs_write32(EXCEPTION_BITMAP, eb);
1194 }
1195
1196 static void clear_atomic_switch_msr_special(unsigned long entry,
1197 unsigned long exit)
1198 {
1199 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1200 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1201 }
1202
1203 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1204 {
1205 unsigned i;
1206 struct msr_autoload *m = &vmx->msr_autoload;
1207
1208 switch (msr) {
1209 case MSR_EFER:
1210 if (cpu_has_load_ia32_efer) {
1211 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1212 VM_EXIT_LOAD_IA32_EFER);
1213 return;
1214 }
1215 break;
1216 case MSR_CORE_PERF_GLOBAL_CTRL:
1217 if (cpu_has_load_perf_global_ctrl) {
1218 clear_atomic_switch_msr_special(
1219 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1220 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1221 return;
1222 }
1223 break;
1224 }
1225
1226 for (i = 0; i < m->nr; ++i)
1227 if (m->guest[i].index == msr)
1228 break;
1229
1230 if (i == m->nr)
1231 return;
1232 --m->nr;
1233 m->guest[i] = m->guest[m->nr];
1234 m->host[i] = m->host[m->nr];
1235 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237 }
1238
1239 static void add_atomic_switch_msr_special(unsigned long entry,
1240 unsigned long exit, unsigned long guest_val_vmcs,
1241 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1242 {
1243 vmcs_write64(guest_val_vmcs, guest_val);
1244 vmcs_write64(host_val_vmcs, host_val);
1245 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1246 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1247 }
1248
1249 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1250 u64 guest_val, u64 host_val)
1251 {
1252 unsigned i;
1253 struct msr_autoload *m = &vmx->msr_autoload;
1254
1255 switch (msr) {
1256 case MSR_EFER:
1257 if (cpu_has_load_ia32_efer) {
1258 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1259 VM_EXIT_LOAD_IA32_EFER,
1260 GUEST_IA32_EFER,
1261 HOST_IA32_EFER,
1262 guest_val, host_val);
1263 return;
1264 }
1265 break;
1266 case MSR_CORE_PERF_GLOBAL_CTRL:
1267 if (cpu_has_load_perf_global_ctrl) {
1268 add_atomic_switch_msr_special(
1269 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1270 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1271 GUEST_IA32_PERF_GLOBAL_CTRL,
1272 HOST_IA32_PERF_GLOBAL_CTRL,
1273 guest_val, host_val);
1274 return;
1275 }
1276 break;
1277 }
1278
1279 for (i = 0; i < m->nr; ++i)
1280 if (m->guest[i].index == msr)
1281 break;
1282
1283 if (i == NR_AUTOLOAD_MSRS) {
1284 printk_once(KERN_WARNING"Not enough mst switch entries. "
1285 "Can't add msr %x\n", msr);
1286 return;
1287 } else if (i == m->nr) {
1288 ++m->nr;
1289 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1290 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1291 }
1292
1293 m->guest[i].index = msr;
1294 m->guest[i].value = guest_val;
1295 m->host[i].index = msr;
1296 m->host[i].value = host_val;
1297 }
1298
1299 static void reload_tss(void)
1300 {
1301 /*
1302 * VT restores TR but not its size. Useless.
1303 */
1304 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1305 struct desc_struct *descs;
1306
1307 descs = (void *)gdt->address;
1308 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1309 load_TR_desc();
1310 }
1311
1312 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1313 {
1314 u64 guest_efer;
1315 u64 ignore_bits;
1316
1317 guest_efer = vmx->vcpu.arch.efer;
1318
1319 /*
1320 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1321 * outside long mode
1322 */
1323 ignore_bits = EFER_NX | EFER_SCE;
1324 #ifdef CONFIG_X86_64
1325 ignore_bits |= EFER_LMA | EFER_LME;
1326 /* SCE is meaningful only in long mode on Intel */
1327 if (guest_efer & EFER_LMA)
1328 ignore_bits &= ~(u64)EFER_SCE;
1329 #endif
1330 guest_efer &= ~ignore_bits;
1331 guest_efer |= host_efer & ignore_bits;
1332 vmx->guest_msrs[efer_offset].data = guest_efer;
1333 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1334
1335 clear_atomic_switch_msr(vmx, MSR_EFER);
1336 /* On ept, can't emulate nx, and must switch nx atomically */
1337 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1338 guest_efer = vmx->vcpu.arch.efer;
1339 if (!(guest_efer & EFER_LMA))
1340 guest_efer &= ~EFER_LME;
1341 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1342 return false;
1343 }
1344
1345 return true;
1346 }
1347
1348 static unsigned long segment_base(u16 selector)
1349 {
1350 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1351 struct desc_struct *d;
1352 unsigned long table_base;
1353 unsigned long v;
1354
1355 if (!(selector & ~3))
1356 return 0;
1357
1358 table_base = gdt->address;
1359
1360 if (selector & 4) { /* from ldt */
1361 u16 ldt_selector = kvm_read_ldt();
1362
1363 if (!(ldt_selector & ~3))
1364 return 0;
1365
1366 table_base = segment_base(ldt_selector);
1367 }
1368 d = (struct desc_struct *)(table_base + (selector & ~7));
1369 v = get_desc_base(d);
1370 #ifdef CONFIG_X86_64
1371 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1372 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1373 #endif
1374 return v;
1375 }
1376
1377 static inline unsigned long kvm_read_tr_base(void)
1378 {
1379 u16 tr;
1380 asm("str %0" : "=g"(tr));
1381 return segment_base(tr);
1382 }
1383
1384 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1385 {
1386 struct vcpu_vmx *vmx = to_vmx(vcpu);
1387 int i;
1388
1389 if (vmx->host_state.loaded)
1390 return;
1391
1392 vmx->host_state.loaded = 1;
1393 /*
1394 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1395 * allow segment selectors with cpl > 0 or ti == 1.
1396 */
1397 vmx->host_state.ldt_sel = kvm_read_ldt();
1398 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1399 savesegment(fs, vmx->host_state.fs_sel);
1400 if (!(vmx->host_state.fs_sel & 7)) {
1401 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1402 vmx->host_state.fs_reload_needed = 0;
1403 } else {
1404 vmcs_write16(HOST_FS_SELECTOR, 0);
1405 vmx->host_state.fs_reload_needed = 1;
1406 }
1407 savesegment(gs, vmx->host_state.gs_sel);
1408 if (!(vmx->host_state.gs_sel & 7))
1409 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1410 else {
1411 vmcs_write16(HOST_GS_SELECTOR, 0);
1412 vmx->host_state.gs_ldt_reload_needed = 1;
1413 }
1414
1415 #ifdef CONFIG_X86_64
1416 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1417 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1418 #else
1419 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1420 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1421 #endif
1422
1423 #ifdef CONFIG_X86_64
1424 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1425 if (is_long_mode(&vmx->vcpu))
1426 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1427 #endif
1428 for (i = 0; i < vmx->save_nmsrs; ++i)
1429 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1430 vmx->guest_msrs[i].data,
1431 vmx->guest_msrs[i].mask);
1432 }
1433
1434 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1435 {
1436 if (!vmx->host_state.loaded)
1437 return;
1438
1439 ++vmx->vcpu.stat.host_state_reload;
1440 vmx->host_state.loaded = 0;
1441 #ifdef CONFIG_X86_64
1442 if (is_long_mode(&vmx->vcpu))
1443 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1444 #endif
1445 if (vmx->host_state.gs_ldt_reload_needed) {
1446 kvm_load_ldt(vmx->host_state.ldt_sel);
1447 #ifdef CONFIG_X86_64
1448 load_gs_index(vmx->host_state.gs_sel);
1449 #else
1450 loadsegment(gs, vmx->host_state.gs_sel);
1451 #endif
1452 }
1453 if (vmx->host_state.fs_reload_needed)
1454 loadsegment(fs, vmx->host_state.fs_sel);
1455 reload_tss();
1456 #ifdef CONFIG_X86_64
1457 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1458 #endif
1459 if (current_thread_info()->status & TS_USEDFPU)
1460 clts();
1461 load_gdt(&__get_cpu_var(host_gdt));
1462 }
1463
1464 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1465 {
1466 preempt_disable();
1467 __vmx_load_host_state(vmx);
1468 preempt_enable();
1469 }
1470
1471 /*
1472 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1473 * vcpu mutex is already taken.
1474 */
1475 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1476 {
1477 struct vcpu_vmx *vmx = to_vmx(vcpu);
1478 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1479
1480 if (!vmm_exclusive)
1481 kvm_cpu_vmxon(phys_addr);
1482 else if (vmx->loaded_vmcs->cpu != cpu)
1483 loaded_vmcs_clear(vmx->loaded_vmcs);
1484
1485 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1486 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1487 vmcs_load(vmx->loaded_vmcs->vmcs);
1488 }
1489
1490 if (vmx->loaded_vmcs->cpu != cpu) {
1491 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1492 unsigned long sysenter_esp;
1493
1494 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1495 local_irq_disable();
1496 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1497 &per_cpu(loaded_vmcss_on_cpu, cpu));
1498 local_irq_enable();
1499
1500 /*
1501 * Linux uses per-cpu TSS and GDT, so set these when switching
1502 * processors.
1503 */
1504 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1505 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1506
1507 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1508 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1509 vmx->loaded_vmcs->cpu = cpu;
1510 }
1511 }
1512
1513 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1514 {
1515 __vmx_load_host_state(to_vmx(vcpu));
1516 if (!vmm_exclusive) {
1517 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1518 vcpu->cpu = -1;
1519 kvm_cpu_vmxoff();
1520 }
1521 }
1522
1523 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1524 {
1525 ulong cr0;
1526
1527 if (vcpu->fpu_active)
1528 return;
1529 vcpu->fpu_active = 1;
1530 cr0 = vmcs_readl(GUEST_CR0);
1531 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1532 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1533 vmcs_writel(GUEST_CR0, cr0);
1534 update_exception_bitmap(vcpu);
1535 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1536 if (is_guest_mode(vcpu))
1537 vcpu->arch.cr0_guest_owned_bits &=
1538 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1539 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1540 }
1541
1542 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1543
1544 /*
1545 * Return the cr0 value that a nested guest would read. This is a combination
1546 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1547 * its hypervisor (cr0_read_shadow).
1548 */
1549 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1550 {
1551 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1552 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1553 }
1554 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1555 {
1556 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1557 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1558 }
1559
1560 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1561 {
1562 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1563 * set this *before* calling this function.
1564 */
1565 vmx_decache_cr0_guest_bits(vcpu);
1566 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1567 update_exception_bitmap(vcpu);
1568 vcpu->arch.cr0_guest_owned_bits = 0;
1569 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1570 if (is_guest_mode(vcpu)) {
1571 /*
1572 * L1's specified read shadow might not contain the TS bit,
1573 * so now that we turned on shadowing of this bit, we need to
1574 * set this bit of the shadow. Like in nested_vmx_run we need
1575 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1576 * up-to-date here because we just decached cr0.TS (and we'll
1577 * only update vmcs12->guest_cr0 on nested exit).
1578 */
1579 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1580 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1581 (vcpu->arch.cr0 & X86_CR0_TS);
1582 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1583 } else
1584 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1585 }
1586
1587 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1588 {
1589 unsigned long rflags, save_rflags;
1590
1591 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1592 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1593 rflags = vmcs_readl(GUEST_RFLAGS);
1594 if (to_vmx(vcpu)->rmode.vm86_active) {
1595 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1596 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1597 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1598 }
1599 to_vmx(vcpu)->rflags = rflags;
1600 }
1601 return to_vmx(vcpu)->rflags;
1602 }
1603
1604 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1605 {
1606 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1607 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1608 to_vmx(vcpu)->rflags = rflags;
1609 if (to_vmx(vcpu)->rmode.vm86_active) {
1610 to_vmx(vcpu)->rmode.save_rflags = rflags;
1611 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1612 }
1613 vmcs_writel(GUEST_RFLAGS, rflags);
1614 }
1615
1616 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1617 {
1618 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1619 int ret = 0;
1620
1621 if (interruptibility & GUEST_INTR_STATE_STI)
1622 ret |= KVM_X86_SHADOW_INT_STI;
1623 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1624 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1625
1626 return ret & mask;
1627 }
1628
1629 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1630 {
1631 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1632 u32 interruptibility = interruptibility_old;
1633
1634 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1635
1636 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1637 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1638 else if (mask & KVM_X86_SHADOW_INT_STI)
1639 interruptibility |= GUEST_INTR_STATE_STI;
1640
1641 if ((interruptibility != interruptibility_old))
1642 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1643 }
1644
1645 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1646 {
1647 unsigned long rip;
1648
1649 rip = kvm_rip_read(vcpu);
1650 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1651 kvm_rip_write(vcpu, rip);
1652
1653 /* skipping an emulated instruction also counts */
1654 vmx_set_interrupt_shadow(vcpu, 0);
1655 }
1656
1657 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1658 {
1659 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1660 * explicitly skip the instruction because if the HLT state is set, then
1661 * the instruction is already executing and RIP has already been
1662 * advanced. */
1663 if (!yield_on_hlt &&
1664 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1665 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1666 }
1667
1668 /*
1669 * KVM wants to inject page-faults which it got to the guest. This function
1670 * checks whether in a nested guest, we need to inject them to L1 or L2.
1671 * This function assumes it is called with the exit reason in vmcs02 being
1672 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1673 * is running).
1674 */
1675 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1676 {
1677 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1678
1679 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1680 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1681 return 0;
1682
1683 nested_vmx_vmexit(vcpu);
1684 return 1;
1685 }
1686
1687 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1688 bool has_error_code, u32 error_code,
1689 bool reinject)
1690 {
1691 struct vcpu_vmx *vmx = to_vmx(vcpu);
1692 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1693
1694 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1695 nested_pf_handled(vcpu))
1696 return;
1697
1698 if (has_error_code) {
1699 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1700 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1701 }
1702
1703 if (vmx->rmode.vm86_active) {
1704 int inc_eip = 0;
1705 if (kvm_exception_is_soft(nr))
1706 inc_eip = vcpu->arch.event_exit_inst_len;
1707 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1708 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1709 return;
1710 }
1711
1712 if (kvm_exception_is_soft(nr)) {
1713 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1714 vmx->vcpu.arch.event_exit_inst_len);
1715 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1716 } else
1717 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1718
1719 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1720 vmx_clear_hlt(vcpu);
1721 }
1722
1723 static bool vmx_rdtscp_supported(void)
1724 {
1725 return cpu_has_vmx_rdtscp();
1726 }
1727
1728 /*
1729 * Swap MSR entry in host/guest MSR entry array.
1730 */
1731 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1732 {
1733 struct shared_msr_entry tmp;
1734
1735 tmp = vmx->guest_msrs[to];
1736 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1737 vmx->guest_msrs[from] = tmp;
1738 }
1739
1740 /*
1741 * Set up the vmcs to automatically save and restore system
1742 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1743 * mode, as fiddling with msrs is very expensive.
1744 */
1745 static void setup_msrs(struct vcpu_vmx *vmx)
1746 {
1747 int save_nmsrs, index;
1748 unsigned long *msr_bitmap;
1749
1750 vmx_load_host_state(vmx);
1751 save_nmsrs = 0;
1752 #ifdef CONFIG_X86_64
1753 if (is_long_mode(&vmx->vcpu)) {
1754 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1755 if (index >= 0)
1756 move_msr_up(vmx, index, save_nmsrs++);
1757 index = __find_msr_index(vmx, MSR_LSTAR);
1758 if (index >= 0)
1759 move_msr_up(vmx, index, save_nmsrs++);
1760 index = __find_msr_index(vmx, MSR_CSTAR);
1761 if (index >= 0)
1762 move_msr_up(vmx, index, save_nmsrs++);
1763 index = __find_msr_index(vmx, MSR_TSC_AUX);
1764 if (index >= 0 && vmx->rdtscp_enabled)
1765 move_msr_up(vmx, index, save_nmsrs++);
1766 /*
1767 * MSR_STAR is only needed on long mode guests, and only
1768 * if efer.sce is enabled.
1769 */
1770 index = __find_msr_index(vmx, MSR_STAR);
1771 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1772 move_msr_up(vmx, index, save_nmsrs++);
1773 }
1774 #endif
1775 index = __find_msr_index(vmx, MSR_EFER);
1776 if (index >= 0 && update_transition_efer(vmx, index))
1777 move_msr_up(vmx, index, save_nmsrs++);
1778
1779 vmx->save_nmsrs = save_nmsrs;
1780
1781 if (cpu_has_vmx_msr_bitmap()) {
1782 if (is_long_mode(&vmx->vcpu))
1783 msr_bitmap = vmx_msr_bitmap_longmode;
1784 else
1785 msr_bitmap = vmx_msr_bitmap_legacy;
1786
1787 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1788 }
1789 }
1790
1791 /*
1792 * reads and returns guest's timestamp counter "register"
1793 * guest_tsc = host_tsc + tsc_offset -- 21.3
1794 */
1795 static u64 guest_read_tsc(void)
1796 {
1797 u64 host_tsc, tsc_offset;
1798
1799 rdtscll(host_tsc);
1800 tsc_offset = vmcs_read64(TSC_OFFSET);
1801 return host_tsc + tsc_offset;
1802 }
1803
1804 /*
1805 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1806 * counter, even if a nested guest (L2) is currently running.
1807 */
1808 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1809 {
1810 u64 host_tsc, tsc_offset;
1811
1812 rdtscll(host_tsc);
1813 tsc_offset = is_guest_mode(vcpu) ?
1814 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1815 vmcs_read64(TSC_OFFSET);
1816 return host_tsc + tsc_offset;
1817 }
1818
1819 /*
1820 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1821 * ioctl. In this case the call-back should update internal vmx state to make
1822 * the changes effective.
1823 */
1824 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1825 {
1826 /* Nothing to do here */
1827 }
1828
1829 /*
1830 * writes 'offset' into guest's timestamp counter offset register
1831 */
1832 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1833 {
1834 if (is_guest_mode(vcpu)) {
1835 /*
1836 * We're here if L1 chose not to trap WRMSR to TSC. According
1837 * to the spec, this should set L1's TSC; The offset that L1
1838 * set for L2 remains unchanged, and still needs to be added
1839 * to the newly set TSC to get L2's TSC.
1840 */
1841 struct vmcs12 *vmcs12;
1842 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1843 /* recalculate vmcs02.TSC_OFFSET: */
1844 vmcs12 = get_vmcs12(vcpu);
1845 vmcs_write64(TSC_OFFSET, offset +
1846 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1847 vmcs12->tsc_offset : 0));
1848 } else {
1849 vmcs_write64(TSC_OFFSET, offset);
1850 }
1851 }
1852
1853 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1854 {
1855 u64 offset = vmcs_read64(TSC_OFFSET);
1856 vmcs_write64(TSC_OFFSET, offset + adjustment);
1857 if (is_guest_mode(vcpu)) {
1858 /* Even when running L2, the adjustment needs to apply to L1 */
1859 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1860 }
1861 }
1862
1863 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1864 {
1865 return target_tsc - native_read_tsc();
1866 }
1867
1868 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1869 {
1870 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1871 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1872 }
1873
1874 /*
1875 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1876 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1877 * all guests if the "nested" module option is off, and can also be disabled
1878 * for a single guest by disabling its VMX cpuid bit.
1879 */
1880 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1881 {
1882 return nested && guest_cpuid_has_vmx(vcpu);
1883 }
1884
1885 /*
1886 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1887 * returned for the various VMX controls MSRs when nested VMX is enabled.
1888 * The same values should also be used to verify that vmcs12 control fields are
1889 * valid during nested entry from L1 to L2.
1890 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1891 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1892 * bit in the high half is on if the corresponding bit in the control field
1893 * may be on. See also vmx_control_verify().
1894 * TODO: allow these variables to be modified (downgraded) by module options
1895 * or other means.
1896 */
1897 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1898 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1899 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1900 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1901 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1902 static __init void nested_vmx_setup_ctls_msrs(void)
1903 {
1904 /*
1905 * Note that as a general rule, the high half of the MSRs (bits in
1906 * the control fields which may be 1) should be initialized by the
1907 * intersection of the underlying hardware's MSR (i.e., features which
1908 * can be supported) and the list of features we want to expose -
1909 * because they are known to be properly supported in our code.
1910 * Also, usually, the low half of the MSRs (bits which must be 1) can
1911 * be set to 0, meaning that L1 may turn off any of these bits. The
1912 * reason is that if one of these bits is necessary, it will appear
1913 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1914 * fields of vmcs01 and vmcs02, will turn these bits off - and
1915 * nested_vmx_exit_handled() will not pass related exits to L1.
1916 * These rules have exceptions below.
1917 */
1918
1919 /* pin-based controls */
1920 /*
1921 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1922 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1923 */
1924 nested_vmx_pinbased_ctls_low = 0x16 ;
1925 nested_vmx_pinbased_ctls_high = 0x16 |
1926 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1927 PIN_BASED_VIRTUAL_NMIS;
1928
1929 /* exit controls */
1930 nested_vmx_exit_ctls_low = 0;
1931 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1932 #ifdef CONFIG_X86_64
1933 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1934 #else
1935 nested_vmx_exit_ctls_high = 0;
1936 #endif
1937
1938 /* entry controls */
1939 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1940 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1941 nested_vmx_entry_ctls_low = 0;
1942 nested_vmx_entry_ctls_high &=
1943 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1944
1945 /* cpu-based controls */
1946 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1947 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1948 nested_vmx_procbased_ctls_low = 0;
1949 nested_vmx_procbased_ctls_high &=
1950 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1951 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1952 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1953 CPU_BASED_CR3_STORE_EXITING |
1954 #ifdef CONFIG_X86_64
1955 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1956 #endif
1957 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1958 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1959 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1960 /*
1961 * We can allow some features even when not supported by the
1962 * hardware. For example, L1 can specify an MSR bitmap - and we
1963 * can use it to avoid exits to L1 - even when L0 runs L2
1964 * without MSR bitmaps.
1965 */
1966 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1967
1968 /* secondary cpu-based controls */
1969 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1970 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1971 nested_vmx_secondary_ctls_low = 0;
1972 nested_vmx_secondary_ctls_high &=
1973 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1974 }
1975
1976 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1977 {
1978 /*
1979 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1980 */
1981 return ((control & high) | low) == control;
1982 }
1983
1984 static inline u64 vmx_control_msr(u32 low, u32 high)
1985 {
1986 return low | ((u64)high << 32);
1987 }
1988
1989 /*
1990 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1991 * also let it use VMX-specific MSRs.
1992 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1993 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1994 * like all other MSRs).
1995 */
1996 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1997 {
1998 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1999 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2000 /*
2001 * According to the spec, processors which do not support VMX
2002 * should throw a #GP(0) when VMX capability MSRs are read.
2003 */
2004 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2005 return 1;
2006 }
2007
2008 switch (msr_index) {
2009 case MSR_IA32_FEATURE_CONTROL:
2010 *pdata = 0;
2011 break;
2012 case MSR_IA32_VMX_BASIC:
2013 /*
2014 * This MSR reports some information about VMX support. We
2015 * should return information about the VMX we emulate for the
2016 * guest, and the VMCS structure we give it - not about the
2017 * VMX support of the underlying hardware.
2018 */
2019 *pdata = VMCS12_REVISION |
2020 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2021 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2022 break;
2023 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2024 case MSR_IA32_VMX_PINBASED_CTLS:
2025 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2026 nested_vmx_pinbased_ctls_high);
2027 break;
2028 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2029 case MSR_IA32_VMX_PROCBASED_CTLS:
2030 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2031 nested_vmx_procbased_ctls_high);
2032 break;
2033 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2034 case MSR_IA32_VMX_EXIT_CTLS:
2035 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2036 nested_vmx_exit_ctls_high);
2037 break;
2038 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2039 case MSR_IA32_VMX_ENTRY_CTLS:
2040 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2041 nested_vmx_entry_ctls_high);
2042 break;
2043 case MSR_IA32_VMX_MISC:
2044 *pdata = 0;
2045 break;
2046 /*
2047 * These MSRs specify bits which the guest must keep fixed (on or off)
2048 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2049 * We picked the standard core2 setting.
2050 */
2051 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2052 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2053 case MSR_IA32_VMX_CR0_FIXED0:
2054 *pdata = VMXON_CR0_ALWAYSON;
2055 break;
2056 case MSR_IA32_VMX_CR0_FIXED1:
2057 *pdata = -1ULL;
2058 break;
2059 case MSR_IA32_VMX_CR4_FIXED0:
2060 *pdata = VMXON_CR4_ALWAYSON;
2061 break;
2062 case MSR_IA32_VMX_CR4_FIXED1:
2063 *pdata = -1ULL;
2064 break;
2065 case MSR_IA32_VMX_VMCS_ENUM:
2066 *pdata = 0x1f;
2067 break;
2068 case MSR_IA32_VMX_PROCBASED_CTLS2:
2069 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2070 nested_vmx_secondary_ctls_high);
2071 break;
2072 case MSR_IA32_VMX_EPT_VPID_CAP:
2073 /* Currently, no nested ept or nested vpid */
2074 *pdata = 0;
2075 break;
2076 default:
2077 return 0;
2078 }
2079
2080 return 1;
2081 }
2082
2083 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2084 {
2085 if (!nested_vmx_allowed(vcpu))
2086 return 0;
2087
2088 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2089 /* TODO: the right thing. */
2090 return 1;
2091 /*
2092 * No need to treat VMX capability MSRs specially: If we don't handle
2093 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2094 */
2095 return 0;
2096 }
2097
2098 /*
2099 * Reads an msr value (of 'msr_index') into 'pdata'.
2100 * Returns 0 on success, non-0 otherwise.
2101 * Assumes vcpu_load() was already called.
2102 */
2103 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2104 {
2105 u64 data;
2106 struct shared_msr_entry *msr;
2107
2108 if (!pdata) {
2109 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2110 return -EINVAL;
2111 }
2112
2113 switch (msr_index) {
2114 #ifdef CONFIG_X86_64
2115 case MSR_FS_BASE:
2116 data = vmcs_readl(GUEST_FS_BASE);
2117 break;
2118 case MSR_GS_BASE:
2119 data = vmcs_readl(GUEST_GS_BASE);
2120 break;
2121 case MSR_KERNEL_GS_BASE:
2122 vmx_load_host_state(to_vmx(vcpu));
2123 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2124 break;
2125 #endif
2126 case MSR_EFER:
2127 return kvm_get_msr_common(vcpu, msr_index, pdata);
2128 case MSR_IA32_TSC:
2129 data = guest_read_tsc();
2130 break;
2131 case MSR_IA32_SYSENTER_CS:
2132 data = vmcs_read32(GUEST_SYSENTER_CS);
2133 break;
2134 case MSR_IA32_SYSENTER_EIP:
2135 data = vmcs_readl(GUEST_SYSENTER_EIP);
2136 break;
2137 case MSR_IA32_SYSENTER_ESP:
2138 data = vmcs_readl(GUEST_SYSENTER_ESP);
2139 break;
2140 case MSR_TSC_AUX:
2141 if (!to_vmx(vcpu)->rdtscp_enabled)
2142 return 1;
2143 /* Otherwise falls through */
2144 default:
2145 vmx_load_host_state(to_vmx(vcpu));
2146 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2147 return 0;
2148 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2149 if (msr) {
2150 vmx_load_host_state(to_vmx(vcpu));
2151 data = msr->data;
2152 break;
2153 }
2154 return kvm_get_msr_common(vcpu, msr_index, pdata);
2155 }
2156
2157 *pdata = data;
2158 return 0;
2159 }
2160
2161 /*
2162 * Writes msr value into into the appropriate "register".
2163 * Returns 0 on success, non-0 otherwise.
2164 * Assumes vcpu_load() was already called.
2165 */
2166 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2167 {
2168 struct vcpu_vmx *vmx = to_vmx(vcpu);
2169 struct shared_msr_entry *msr;
2170 int ret = 0;
2171
2172 switch (msr_index) {
2173 case MSR_EFER:
2174 vmx_load_host_state(vmx);
2175 ret = kvm_set_msr_common(vcpu, msr_index, data);
2176 break;
2177 #ifdef CONFIG_X86_64
2178 case MSR_FS_BASE:
2179 vmx_segment_cache_clear(vmx);
2180 vmcs_writel(GUEST_FS_BASE, data);
2181 break;
2182 case MSR_GS_BASE:
2183 vmx_segment_cache_clear(vmx);
2184 vmcs_writel(GUEST_GS_BASE, data);
2185 break;
2186 case MSR_KERNEL_GS_BASE:
2187 vmx_load_host_state(vmx);
2188 vmx->msr_guest_kernel_gs_base = data;
2189 break;
2190 #endif
2191 case MSR_IA32_SYSENTER_CS:
2192 vmcs_write32(GUEST_SYSENTER_CS, data);
2193 break;
2194 case MSR_IA32_SYSENTER_EIP:
2195 vmcs_writel(GUEST_SYSENTER_EIP, data);
2196 break;
2197 case MSR_IA32_SYSENTER_ESP:
2198 vmcs_writel(GUEST_SYSENTER_ESP, data);
2199 break;
2200 case MSR_IA32_TSC:
2201 kvm_write_tsc(vcpu, data);
2202 break;
2203 case MSR_IA32_CR_PAT:
2204 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2205 vmcs_write64(GUEST_IA32_PAT, data);
2206 vcpu->arch.pat = data;
2207 break;
2208 }
2209 ret = kvm_set_msr_common(vcpu, msr_index, data);
2210 break;
2211 case MSR_TSC_AUX:
2212 if (!vmx->rdtscp_enabled)
2213 return 1;
2214 /* Check reserved bit, higher 32 bits should be zero */
2215 if ((data >> 32) != 0)
2216 return 1;
2217 /* Otherwise falls through */
2218 default:
2219 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2220 break;
2221 msr = find_msr_entry(vmx, msr_index);
2222 if (msr) {
2223 vmx_load_host_state(vmx);
2224 msr->data = data;
2225 break;
2226 }
2227 ret = kvm_set_msr_common(vcpu, msr_index, data);
2228 }
2229
2230 return ret;
2231 }
2232
2233 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2234 {
2235 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2236 switch (reg) {
2237 case VCPU_REGS_RSP:
2238 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2239 break;
2240 case VCPU_REGS_RIP:
2241 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2242 break;
2243 case VCPU_EXREG_PDPTR:
2244 if (enable_ept)
2245 ept_save_pdptrs(vcpu);
2246 break;
2247 default:
2248 break;
2249 }
2250 }
2251
2252 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2253 {
2254 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2255 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2256 else
2257 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2258
2259 update_exception_bitmap(vcpu);
2260 }
2261
2262 static __init int cpu_has_kvm_support(void)
2263 {
2264 return cpu_has_vmx();
2265 }
2266
2267 static __init int vmx_disabled_by_bios(void)
2268 {
2269 u64 msr;
2270
2271 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2272 if (msr & FEATURE_CONTROL_LOCKED) {
2273 /* launched w/ TXT and VMX disabled */
2274 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2275 && tboot_enabled())
2276 return 1;
2277 /* launched w/o TXT and VMX only enabled w/ TXT */
2278 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2279 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2280 && !tboot_enabled()) {
2281 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2282 "activate TXT before enabling KVM\n");
2283 return 1;
2284 }
2285 /* launched w/o TXT and VMX disabled */
2286 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2287 && !tboot_enabled())
2288 return 1;
2289 }
2290
2291 return 0;
2292 }
2293
2294 static void kvm_cpu_vmxon(u64 addr)
2295 {
2296 asm volatile (ASM_VMX_VMXON_RAX
2297 : : "a"(&addr), "m"(addr)
2298 : "memory", "cc");
2299 }
2300
2301 static int hardware_enable(void *garbage)
2302 {
2303 int cpu = raw_smp_processor_id();
2304 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2305 u64 old, test_bits;
2306
2307 if (read_cr4() & X86_CR4_VMXE)
2308 return -EBUSY;
2309
2310 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2311 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2312
2313 test_bits = FEATURE_CONTROL_LOCKED;
2314 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2315 if (tboot_enabled())
2316 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2317
2318 if ((old & test_bits) != test_bits) {
2319 /* enable and lock */
2320 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2321 }
2322 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2323
2324 if (vmm_exclusive) {
2325 kvm_cpu_vmxon(phys_addr);
2326 ept_sync_global();
2327 }
2328
2329 store_gdt(&__get_cpu_var(host_gdt));
2330
2331 return 0;
2332 }
2333
2334 static void vmclear_local_loaded_vmcss(void)
2335 {
2336 int cpu = raw_smp_processor_id();
2337 struct loaded_vmcs *v, *n;
2338
2339 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2340 loaded_vmcss_on_cpu_link)
2341 __loaded_vmcs_clear(v);
2342 }
2343
2344
2345 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2346 * tricks.
2347 */
2348 static void kvm_cpu_vmxoff(void)
2349 {
2350 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2351 }
2352
2353 static void hardware_disable(void *garbage)
2354 {
2355 if (vmm_exclusive) {
2356 vmclear_local_loaded_vmcss();
2357 kvm_cpu_vmxoff();
2358 }
2359 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2360 }
2361
2362 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2363 u32 msr, u32 *result)
2364 {
2365 u32 vmx_msr_low, vmx_msr_high;
2366 u32 ctl = ctl_min | ctl_opt;
2367
2368 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2369
2370 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2371 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2372
2373 /* Ensure minimum (required) set of control bits are supported. */
2374 if (ctl_min & ~ctl)
2375 return -EIO;
2376
2377 *result = ctl;
2378 return 0;
2379 }
2380
2381 static __init bool allow_1_setting(u32 msr, u32 ctl)
2382 {
2383 u32 vmx_msr_low, vmx_msr_high;
2384
2385 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2386 return vmx_msr_high & ctl;
2387 }
2388
2389 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2390 {
2391 u32 vmx_msr_low, vmx_msr_high;
2392 u32 min, opt, min2, opt2;
2393 u32 _pin_based_exec_control = 0;
2394 u32 _cpu_based_exec_control = 0;
2395 u32 _cpu_based_2nd_exec_control = 0;
2396 u32 _vmexit_control = 0;
2397 u32 _vmentry_control = 0;
2398
2399 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2400 opt = PIN_BASED_VIRTUAL_NMIS;
2401 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2402 &_pin_based_exec_control) < 0)
2403 return -EIO;
2404
2405 min =
2406 #ifdef CONFIG_X86_64
2407 CPU_BASED_CR8_LOAD_EXITING |
2408 CPU_BASED_CR8_STORE_EXITING |
2409 #endif
2410 CPU_BASED_CR3_LOAD_EXITING |
2411 CPU_BASED_CR3_STORE_EXITING |
2412 CPU_BASED_USE_IO_BITMAPS |
2413 CPU_BASED_MOV_DR_EXITING |
2414 CPU_BASED_USE_TSC_OFFSETING |
2415 CPU_BASED_MWAIT_EXITING |
2416 CPU_BASED_MONITOR_EXITING |
2417 CPU_BASED_INVLPG_EXITING;
2418
2419 if (yield_on_hlt)
2420 min |= CPU_BASED_HLT_EXITING;
2421
2422 opt = CPU_BASED_TPR_SHADOW |
2423 CPU_BASED_USE_MSR_BITMAPS |
2424 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2425 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2426 &_cpu_based_exec_control) < 0)
2427 return -EIO;
2428 #ifdef CONFIG_X86_64
2429 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2430 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2431 ~CPU_BASED_CR8_STORE_EXITING;
2432 #endif
2433 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2434 min2 = 0;
2435 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2436 SECONDARY_EXEC_WBINVD_EXITING |
2437 SECONDARY_EXEC_ENABLE_VPID |
2438 SECONDARY_EXEC_ENABLE_EPT |
2439 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2440 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2441 SECONDARY_EXEC_RDTSCP;
2442 if (adjust_vmx_controls(min2, opt2,
2443 MSR_IA32_VMX_PROCBASED_CTLS2,
2444 &_cpu_based_2nd_exec_control) < 0)
2445 return -EIO;
2446 }
2447 #ifndef CONFIG_X86_64
2448 if (!(_cpu_based_2nd_exec_control &
2449 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2450 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2451 #endif
2452 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2453 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2454 enabled */
2455 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2456 CPU_BASED_CR3_STORE_EXITING |
2457 CPU_BASED_INVLPG_EXITING);
2458 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2459 vmx_capability.ept, vmx_capability.vpid);
2460 }
2461
2462 min = 0;
2463 #ifdef CONFIG_X86_64
2464 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2465 #endif
2466 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2467 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2468 &_vmexit_control) < 0)
2469 return -EIO;
2470
2471 min = 0;
2472 opt = VM_ENTRY_LOAD_IA32_PAT;
2473 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2474 &_vmentry_control) < 0)
2475 return -EIO;
2476
2477 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2478
2479 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2480 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2481 return -EIO;
2482
2483 #ifdef CONFIG_X86_64
2484 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2485 if (vmx_msr_high & (1u<<16))
2486 return -EIO;
2487 #endif
2488
2489 /* Require Write-Back (WB) memory type for VMCS accesses. */
2490 if (((vmx_msr_high >> 18) & 15) != 6)
2491 return -EIO;
2492
2493 vmcs_conf->size = vmx_msr_high & 0x1fff;
2494 vmcs_conf->order = get_order(vmcs_config.size);
2495 vmcs_conf->revision_id = vmx_msr_low;
2496
2497 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2498 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2499 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2500 vmcs_conf->vmexit_ctrl = _vmexit_control;
2501 vmcs_conf->vmentry_ctrl = _vmentry_control;
2502
2503 cpu_has_load_ia32_efer =
2504 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2505 VM_ENTRY_LOAD_IA32_EFER)
2506 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2507 VM_EXIT_LOAD_IA32_EFER);
2508
2509 cpu_has_load_perf_global_ctrl =
2510 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2511 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2512 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2513 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2514
2515 /*
2516 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2517 * but due to arrata below it can't be used. Workaround is to use
2518 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2519 *
2520 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2521 *
2522 * AAK155 (model 26)
2523 * AAP115 (model 30)
2524 * AAT100 (model 37)
2525 * BC86,AAY89,BD102 (model 44)
2526 * BA97 (model 46)
2527 *
2528 */
2529 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2530 switch (boot_cpu_data.x86_model) {
2531 case 26:
2532 case 30:
2533 case 37:
2534 case 44:
2535 case 46:
2536 cpu_has_load_perf_global_ctrl = false;
2537 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2538 "does not work properly. Using workaround\n");
2539 break;
2540 default:
2541 break;
2542 }
2543 }
2544
2545 return 0;
2546 }
2547
2548 static struct vmcs *alloc_vmcs_cpu(int cpu)
2549 {
2550 int node = cpu_to_node(cpu);
2551 struct page *pages;
2552 struct vmcs *vmcs;
2553
2554 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2555 if (!pages)
2556 return NULL;
2557 vmcs = page_address(pages);
2558 memset(vmcs, 0, vmcs_config.size);
2559 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2560 return vmcs;
2561 }
2562
2563 static struct vmcs *alloc_vmcs(void)
2564 {
2565 return alloc_vmcs_cpu(raw_smp_processor_id());
2566 }
2567
2568 static void free_vmcs(struct vmcs *vmcs)
2569 {
2570 free_pages((unsigned long)vmcs, vmcs_config.order);
2571 }
2572
2573 /*
2574 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2575 */
2576 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2577 {
2578 if (!loaded_vmcs->vmcs)
2579 return;
2580 loaded_vmcs_clear(loaded_vmcs);
2581 free_vmcs(loaded_vmcs->vmcs);
2582 loaded_vmcs->vmcs = NULL;
2583 }
2584
2585 static void free_kvm_area(void)
2586 {
2587 int cpu;
2588
2589 for_each_possible_cpu(cpu) {
2590 free_vmcs(per_cpu(vmxarea, cpu));
2591 per_cpu(vmxarea, cpu) = NULL;
2592 }
2593 }
2594
2595 static __init int alloc_kvm_area(void)
2596 {
2597 int cpu;
2598
2599 for_each_possible_cpu(cpu) {
2600 struct vmcs *vmcs;
2601
2602 vmcs = alloc_vmcs_cpu(cpu);
2603 if (!vmcs) {
2604 free_kvm_area();
2605 return -ENOMEM;
2606 }
2607
2608 per_cpu(vmxarea, cpu) = vmcs;
2609 }
2610 return 0;
2611 }
2612
2613 static __init int hardware_setup(void)
2614 {
2615 if (setup_vmcs_config(&vmcs_config) < 0)
2616 return -EIO;
2617
2618 if (boot_cpu_has(X86_FEATURE_NX))
2619 kvm_enable_efer_bits(EFER_NX);
2620
2621 if (!cpu_has_vmx_vpid())
2622 enable_vpid = 0;
2623
2624 if (!cpu_has_vmx_ept() ||
2625 !cpu_has_vmx_ept_4levels()) {
2626 enable_ept = 0;
2627 enable_unrestricted_guest = 0;
2628 }
2629
2630 if (!cpu_has_vmx_unrestricted_guest())
2631 enable_unrestricted_guest = 0;
2632
2633 if (!cpu_has_vmx_flexpriority())
2634 flexpriority_enabled = 0;
2635
2636 if (!cpu_has_vmx_tpr_shadow())
2637 kvm_x86_ops->update_cr8_intercept = NULL;
2638
2639 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2640 kvm_disable_largepages();
2641
2642 if (!cpu_has_vmx_ple())
2643 ple_gap = 0;
2644
2645 if (nested)
2646 nested_vmx_setup_ctls_msrs();
2647
2648 return alloc_kvm_area();
2649 }
2650
2651 static __exit void hardware_unsetup(void)
2652 {
2653 free_kvm_area();
2654 }
2655
2656 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2657 {
2658 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2659
2660 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2661 vmcs_write16(sf->selector, save->selector);
2662 vmcs_writel(sf->base, save->base);
2663 vmcs_write32(sf->limit, save->limit);
2664 vmcs_write32(sf->ar_bytes, save->ar);
2665 } else {
2666 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2667 << AR_DPL_SHIFT;
2668 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2669 }
2670 }
2671
2672 static void enter_pmode(struct kvm_vcpu *vcpu)
2673 {
2674 unsigned long flags;
2675 struct vcpu_vmx *vmx = to_vmx(vcpu);
2676
2677 vmx->emulation_required = 1;
2678 vmx->rmode.vm86_active = 0;
2679
2680 vmx_segment_cache_clear(vmx);
2681
2682 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2683 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2684 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2685 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2686
2687 flags = vmcs_readl(GUEST_RFLAGS);
2688 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2689 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2690 vmcs_writel(GUEST_RFLAGS, flags);
2691
2692 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2693 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2694
2695 update_exception_bitmap(vcpu);
2696
2697 if (emulate_invalid_guest_state)
2698 return;
2699
2700 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2701 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2702 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2703 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2704
2705 vmx_segment_cache_clear(vmx);
2706
2707 vmcs_write16(GUEST_SS_SELECTOR, 0);
2708 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2709
2710 vmcs_write16(GUEST_CS_SELECTOR,
2711 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2712 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2713 }
2714
2715 static gva_t rmode_tss_base(struct kvm *kvm)
2716 {
2717 if (!kvm->arch.tss_addr) {
2718 struct kvm_memslots *slots;
2719 gfn_t base_gfn;
2720
2721 slots = kvm_memslots(kvm);
2722 base_gfn = slots->memslots[0].base_gfn +
2723 kvm->memslots->memslots[0].npages - 3;
2724 return base_gfn << PAGE_SHIFT;
2725 }
2726 return kvm->arch.tss_addr;
2727 }
2728
2729 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2730 {
2731 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2732
2733 save->selector = vmcs_read16(sf->selector);
2734 save->base = vmcs_readl(sf->base);
2735 save->limit = vmcs_read32(sf->limit);
2736 save->ar = vmcs_read32(sf->ar_bytes);
2737 vmcs_write16(sf->selector, save->base >> 4);
2738 vmcs_write32(sf->base, save->base & 0xffff0);
2739 vmcs_write32(sf->limit, 0xffff);
2740 vmcs_write32(sf->ar_bytes, 0xf3);
2741 if (save->base & 0xf)
2742 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2743 " aligned when entering protected mode (seg=%d)",
2744 seg);
2745 }
2746
2747 static void enter_rmode(struct kvm_vcpu *vcpu)
2748 {
2749 unsigned long flags;
2750 struct vcpu_vmx *vmx = to_vmx(vcpu);
2751
2752 if (enable_unrestricted_guest)
2753 return;
2754
2755 vmx->emulation_required = 1;
2756 vmx->rmode.vm86_active = 1;
2757
2758 /*
2759 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2760 * vcpu. Call it here with phys address pointing 16M below 4G.
2761 */
2762 if (!vcpu->kvm->arch.tss_addr) {
2763 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2764 "called before entering vcpu\n");
2765 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2766 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2767 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2768 }
2769
2770 vmx_segment_cache_clear(vmx);
2771
2772 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2773 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2774 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2775
2776 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2777 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2778
2779 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2780 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2781
2782 flags = vmcs_readl(GUEST_RFLAGS);
2783 vmx->rmode.save_rflags = flags;
2784
2785 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2786
2787 vmcs_writel(GUEST_RFLAGS, flags);
2788 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2789 update_exception_bitmap(vcpu);
2790
2791 if (emulate_invalid_guest_state)
2792 goto continue_rmode;
2793
2794 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2795 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2796 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2797
2798 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2799 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2800 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2801 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2802 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2803
2804 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2805 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2806 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2807 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2808
2809 continue_rmode:
2810 kvm_mmu_reset_context(vcpu);
2811 }
2812
2813 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2814 {
2815 struct vcpu_vmx *vmx = to_vmx(vcpu);
2816 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2817
2818 if (!msr)
2819 return;
2820
2821 /*
2822 * Force kernel_gs_base reloading before EFER changes, as control
2823 * of this msr depends on is_long_mode().
2824 */
2825 vmx_load_host_state(to_vmx(vcpu));
2826 vcpu->arch.efer = efer;
2827 if (efer & EFER_LMA) {
2828 vmcs_write32(VM_ENTRY_CONTROLS,
2829 vmcs_read32(VM_ENTRY_CONTROLS) |
2830 VM_ENTRY_IA32E_MODE);
2831 msr->data = efer;
2832 } else {
2833 vmcs_write32(VM_ENTRY_CONTROLS,
2834 vmcs_read32(VM_ENTRY_CONTROLS) &
2835 ~VM_ENTRY_IA32E_MODE);
2836
2837 msr->data = efer & ~EFER_LME;
2838 }
2839 setup_msrs(vmx);
2840 }
2841
2842 #ifdef CONFIG_X86_64
2843
2844 static void enter_lmode(struct kvm_vcpu *vcpu)
2845 {
2846 u32 guest_tr_ar;
2847
2848 vmx_segment_cache_clear(to_vmx(vcpu));
2849
2850 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2851 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2852 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2853 __func__);
2854 vmcs_write32(GUEST_TR_AR_BYTES,
2855 (guest_tr_ar & ~AR_TYPE_MASK)
2856 | AR_TYPE_BUSY_64_TSS);
2857 }
2858 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2859 }
2860
2861 static void exit_lmode(struct kvm_vcpu *vcpu)
2862 {
2863 vmcs_write32(VM_ENTRY_CONTROLS,
2864 vmcs_read32(VM_ENTRY_CONTROLS)
2865 & ~VM_ENTRY_IA32E_MODE);
2866 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2867 }
2868
2869 #endif
2870
2871 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2872 {
2873 vpid_sync_context(to_vmx(vcpu));
2874 if (enable_ept) {
2875 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2876 return;
2877 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2878 }
2879 }
2880
2881 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2882 {
2883 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2884
2885 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2886 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2887 }
2888
2889 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2890 {
2891 if (enable_ept && is_paging(vcpu))
2892 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2893 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2894 }
2895
2896 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2897 {
2898 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2899
2900 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2901 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2902 }
2903
2904 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2905 {
2906 if (!test_bit(VCPU_EXREG_PDPTR,
2907 (unsigned long *)&vcpu->arch.regs_dirty))
2908 return;
2909
2910 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2911 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2912 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2913 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2914 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2915 }
2916 }
2917
2918 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2919 {
2920 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2921 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2922 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2923 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2924 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2925 }
2926
2927 __set_bit(VCPU_EXREG_PDPTR,
2928 (unsigned long *)&vcpu->arch.regs_avail);
2929 __set_bit(VCPU_EXREG_PDPTR,
2930 (unsigned long *)&vcpu->arch.regs_dirty);
2931 }
2932
2933 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2934
2935 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2936 unsigned long cr0,
2937 struct kvm_vcpu *vcpu)
2938 {
2939 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2940 vmx_decache_cr3(vcpu);
2941 if (!(cr0 & X86_CR0_PG)) {
2942 /* From paging/starting to nonpaging */
2943 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2944 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2945 (CPU_BASED_CR3_LOAD_EXITING |
2946 CPU_BASED_CR3_STORE_EXITING));
2947 vcpu->arch.cr0 = cr0;
2948 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2949 } else if (!is_paging(vcpu)) {
2950 /* From nonpaging to paging */
2951 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2952 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2953 ~(CPU_BASED_CR3_LOAD_EXITING |
2954 CPU_BASED_CR3_STORE_EXITING));
2955 vcpu->arch.cr0 = cr0;
2956 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2957 }
2958
2959 if (!(cr0 & X86_CR0_WP))
2960 *hw_cr0 &= ~X86_CR0_WP;
2961 }
2962
2963 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2964 {
2965 struct vcpu_vmx *vmx = to_vmx(vcpu);
2966 unsigned long hw_cr0;
2967
2968 if (enable_unrestricted_guest)
2969 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2970 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2971 else
2972 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2973
2974 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2975 enter_pmode(vcpu);
2976
2977 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2978 enter_rmode(vcpu);
2979
2980 #ifdef CONFIG_X86_64
2981 if (vcpu->arch.efer & EFER_LME) {
2982 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2983 enter_lmode(vcpu);
2984 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2985 exit_lmode(vcpu);
2986 }
2987 #endif
2988
2989 if (enable_ept)
2990 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2991
2992 if (!vcpu->fpu_active)
2993 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2994
2995 vmcs_writel(CR0_READ_SHADOW, cr0);
2996 vmcs_writel(GUEST_CR0, hw_cr0);
2997 vcpu->arch.cr0 = cr0;
2998 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2999 }
3000
3001 static u64 construct_eptp(unsigned long root_hpa)
3002 {
3003 u64 eptp;
3004
3005 /* TODO write the value reading from MSR */
3006 eptp = VMX_EPT_DEFAULT_MT |
3007 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3008 eptp |= (root_hpa & PAGE_MASK);
3009
3010 return eptp;
3011 }
3012
3013 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3014 {
3015 unsigned long guest_cr3;
3016 u64 eptp;
3017
3018 guest_cr3 = cr3;
3019 if (enable_ept) {
3020 eptp = construct_eptp(cr3);
3021 vmcs_write64(EPT_POINTER, eptp);
3022 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3023 vcpu->kvm->arch.ept_identity_map_addr;
3024 ept_load_pdptrs(vcpu);
3025 }
3026
3027 vmx_flush_tlb(vcpu);
3028 vmcs_writel(GUEST_CR3, guest_cr3);
3029 }
3030
3031 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3032 {
3033 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3034 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3035
3036 if (cr4 & X86_CR4_VMXE) {
3037 /*
3038 * To use VMXON (and later other VMX instructions), a guest
3039 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3040 * So basically the check on whether to allow nested VMX
3041 * is here.
3042 */
3043 if (!nested_vmx_allowed(vcpu))
3044 return 1;
3045 } else if (to_vmx(vcpu)->nested.vmxon)
3046 return 1;
3047
3048 vcpu->arch.cr4 = cr4;
3049 if (enable_ept) {
3050 if (!is_paging(vcpu)) {
3051 hw_cr4 &= ~X86_CR4_PAE;
3052 hw_cr4 |= X86_CR4_PSE;
3053 } else if (!(cr4 & X86_CR4_PAE)) {
3054 hw_cr4 &= ~X86_CR4_PAE;
3055 }
3056 }
3057
3058 vmcs_writel(CR4_READ_SHADOW, cr4);
3059 vmcs_writel(GUEST_CR4, hw_cr4);
3060 return 0;
3061 }
3062
3063 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3064 struct kvm_segment *var, int seg)
3065 {
3066 struct vcpu_vmx *vmx = to_vmx(vcpu);
3067 struct kvm_save_segment *save;
3068 u32 ar;
3069
3070 if (vmx->rmode.vm86_active
3071 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3072 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3073 || seg == VCPU_SREG_GS)
3074 && !emulate_invalid_guest_state) {
3075 switch (seg) {
3076 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3077 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3078 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3079 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3080 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3081 default: BUG();
3082 }
3083 var->selector = save->selector;
3084 var->base = save->base;
3085 var->limit = save->limit;
3086 ar = save->ar;
3087 if (seg == VCPU_SREG_TR
3088 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3089 goto use_saved_rmode_seg;
3090 }
3091 var->base = vmx_read_guest_seg_base(vmx, seg);
3092 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3093 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3094 ar = vmx_read_guest_seg_ar(vmx, seg);
3095 use_saved_rmode_seg:
3096 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3097 ar = 0;
3098 var->type = ar & 15;
3099 var->s = (ar >> 4) & 1;
3100 var->dpl = (ar >> 5) & 3;
3101 var->present = (ar >> 7) & 1;
3102 var->avl = (ar >> 12) & 1;
3103 var->l = (ar >> 13) & 1;
3104 var->db = (ar >> 14) & 1;
3105 var->g = (ar >> 15) & 1;
3106 var->unusable = (ar >> 16) & 1;
3107 }
3108
3109 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3110 {
3111 struct kvm_segment s;
3112
3113 if (to_vmx(vcpu)->rmode.vm86_active) {
3114 vmx_get_segment(vcpu, &s, seg);
3115 return s.base;
3116 }
3117 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3118 }
3119
3120 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3121 {
3122 if (!is_protmode(vcpu))
3123 return 0;
3124
3125 if (!is_long_mode(vcpu)
3126 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3127 return 3;
3128
3129 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3130 }
3131
3132 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3133 {
3134 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3135 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3136 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3137 }
3138 return to_vmx(vcpu)->cpl;
3139 }
3140
3141
3142 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3143 {
3144 u32 ar;
3145
3146 if (var->unusable)
3147 ar = 1 << 16;
3148 else {
3149 ar = var->type & 15;
3150 ar |= (var->s & 1) << 4;
3151 ar |= (var->dpl & 3) << 5;
3152 ar |= (var->present & 1) << 7;
3153 ar |= (var->avl & 1) << 12;
3154 ar |= (var->l & 1) << 13;
3155 ar |= (var->db & 1) << 14;
3156 ar |= (var->g & 1) << 15;
3157 }
3158 if (ar == 0) /* a 0 value means unusable */
3159 ar = AR_UNUSABLE_MASK;
3160
3161 return ar;
3162 }
3163
3164 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3165 struct kvm_segment *var, int seg)
3166 {
3167 struct vcpu_vmx *vmx = to_vmx(vcpu);
3168 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3169 u32 ar;
3170
3171 vmx_segment_cache_clear(vmx);
3172
3173 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3174 vmcs_write16(sf->selector, var->selector);
3175 vmx->rmode.tr.selector = var->selector;
3176 vmx->rmode.tr.base = var->base;
3177 vmx->rmode.tr.limit = var->limit;
3178 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3179 return;
3180 }
3181 vmcs_writel(sf->base, var->base);
3182 vmcs_write32(sf->limit, var->limit);
3183 vmcs_write16(sf->selector, var->selector);
3184 if (vmx->rmode.vm86_active && var->s) {
3185 /*
3186 * Hack real-mode segments into vm86 compatibility.
3187 */
3188 if (var->base == 0xffff0000 && var->selector == 0xf000)
3189 vmcs_writel(sf->base, 0xf0000);
3190 ar = 0xf3;
3191 } else
3192 ar = vmx_segment_access_rights(var);
3193
3194 /*
3195 * Fix the "Accessed" bit in AR field of segment registers for older
3196 * qemu binaries.
3197 * IA32 arch specifies that at the time of processor reset the
3198 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3199 * is setting it to 0 in the usedland code. This causes invalid guest
3200 * state vmexit when "unrestricted guest" mode is turned on.
3201 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3202 * tree. Newer qemu binaries with that qemu fix would not need this
3203 * kvm hack.
3204 */
3205 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3206 ar |= 0x1; /* Accessed */
3207
3208 vmcs_write32(sf->ar_bytes, ar);
3209 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3210 }
3211
3212 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3213 {
3214 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3215
3216 *db = (ar >> 14) & 1;
3217 *l = (ar >> 13) & 1;
3218 }
3219
3220 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3221 {
3222 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3223 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3224 }
3225
3226 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3227 {
3228 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3229 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3230 }
3231
3232 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3233 {
3234 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3235 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3236 }
3237
3238 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3239 {
3240 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3241 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3242 }
3243
3244 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3245 {
3246 struct kvm_segment var;
3247 u32 ar;
3248
3249 vmx_get_segment(vcpu, &var, seg);
3250 ar = vmx_segment_access_rights(&var);
3251
3252 if (var.base != (var.selector << 4))
3253 return false;
3254 if (var.limit != 0xffff)
3255 return false;
3256 if (ar != 0xf3)
3257 return false;
3258
3259 return true;
3260 }
3261
3262 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3263 {
3264 struct kvm_segment cs;
3265 unsigned int cs_rpl;
3266
3267 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3268 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3269
3270 if (cs.unusable)
3271 return false;
3272 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3273 return false;
3274 if (!cs.s)
3275 return false;
3276 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3277 if (cs.dpl > cs_rpl)
3278 return false;
3279 } else {
3280 if (cs.dpl != cs_rpl)
3281 return false;
3282 }
3283 if (!cs.present)
3284 return false;
3285
3286 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3287 return true;
3288 }
3289
3290 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3291 {
3292 struct kvm_segment ss;
3293 unsigned int ss_rpl;
3294
3295 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3296 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3297
3298 if (ss.unusable)
3299 return true;
3300 if (ss.type != 3 && ss.type != 7)
3301 return false;
3302 if (!ss.s)
3303 return false;
3304 if (ss.dpl != ss_rpl) /* DPL != RPL */
3305 return false;
3306 if (!ss.present)
3307 return false;
3308
3309 return true;
3310 }
3311
3312 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3313 {
3314 struct kvm_segment var;
3315 unsigned int rpl;
3316
3317 vmx_get_segment(vcpu, &var, seg);
3318 rpl = var.selector & SELECTOR_RPL_MASK;
3319
3320 if (var.unusable)
3321 return true;
3322 if (!var.s)
3323 return false;
3324 if (!var.present)
3325 return false;
3326 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3327 if (var.dpl < rpl) /* DPL < RPL */
3328 return false;
3329 }
3330
3331 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3332 * rights flags
3333 */
3334 return true;
3335 }
3336
3337 static bool tr_valid(struct kvm_vcpu *vcpu)
3338 {
3339 struct kvm_segment tr;
3340
3341 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3342
3343 if (tr.unusable)
3344 return false;
3345 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3346 return false;
3347 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3348 return false;
3349 if (!tr.present)
3350 return false;
3351
3352 return true;
3353 }
3354
3355 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3356 {
3357 struct kvm_segment ldtr;
3358
3359 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3360
3361 if (ldtr.unusable)
3362 return true;
3363 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3364 return false;
3365 if (ldtr.type != 2)
3366 return false;
3367 if (!ldtr.present)
3368 return false;
3369
3370 return true;
3371 }
3372
3373 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3374 {
3375 struct kvm_segment cs, ss;
3376
3377 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3378 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3379
3380 return ((cs.selector & SELECTOR_RPL_MASK) ==
3381 (ss.selector & SELECTOR_RPL_MASK));
3382 }
3383
3384 /*
3385 * Check if guest state is valid. Returns true if valid, false if
3386 * not.
3387 * We assume that registers are always usable
3388 */
3389 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3390 {
3391 /* real mode guest state checks */
3392 if (!is_protmode(vcpu)) {
3393 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3394 return false;
3395 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3396 return false;
3397 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3398 return false;
3399 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3400 return false;
3401 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3402 return false;
3403 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3404 return false;
3405 } else {
3406 /* protected mode guest state checks */
3407 if (!cs_ss_rpl_check(vcpu))
3408 return false;
3409 if (!code_segment_valid(vcpu))
3410 return false;
3411 if (!stack_segment_valid(vcpu))
3412 return false;
3413 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3414 return false;
3415 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3416 return false;
3417 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3418 return false;
3419 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3420 return false;
3421 if (!tr_valid(vcpu))
3422 return false;
3423 if (!ldtr_valid(vcpu))
3424 return false;
3425 }
3426 /* TODO:
3427 * - Add checks on RIP
3428 * - Add checks on RFLAGS
3429 */
3430
3431 return true;
3432 }
3433
3434 static int init_rmode_tss(struct kvm *kvm)
3435 {
3436 gfn_t fn;
3437 u16 data = 0;
3438 int r, idx, ret = 0;
3439
3440 idx = srcu_read_lock(&kvm->srcu);
3441 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3442 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3443 if (r < 0)
3444 goto out;
3445 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3446 r = kvm_write_guest_page(kvm, fn++, &data,
3447 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3448 if (r < 0)
3449 goto out;
3450 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3451 if (r < 0)
3452 goto out;
3453 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3454 if (r < 0)
3455 goto out;
3456 data = ~0;
3457 r = kvm_write_guest_page(kvm, fn, &data,
3458 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3459 sizeof(u8));
3460 if (r < 0)
3461 goto out;
3462
3463 ret = 1;
3464 out:
3465 srcu_read_unlock(&kvm->srcu, idx);
3466 return ret;
3467 }
3468
3469 static int init_rmode_identity_map(struct kvm *kvm)
3470 {
3471 int i, idx, r, ret;
3472 pfn_t identity_map_pfn;
3473 u32 tmp;
3474
3475 if (!enable_ept)
3476 return 1;
3477 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3478 printk(KERN_ERR "EPT: identity-mapping pagetable "
3479 "haven't been allocated!\n");
3480 return 0;
3481 }
3482 if (likely(kvm->arch.ept_identity_pagetable_done))
3483 return 1;
3484 ret = 0;
3485 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3486 idx = srcu_read_lock(&kvm->srcu);
3487 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3488 if (r < 0)
3489 goto out;
3490 /* Set up identity-mapping pagetable for EPT in real mode */
3491 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3492 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3493 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3494 r = kvm_write_guest_page(kvm, identity_map_pfn,
3495 &tmp, i * sizeof(tmp), sizeof(tmp));
3496 if (r < 0)
3497 goto out;
3498 }
3499 kvm->arch.ept_identity_pagetable_done = true;
3500 ret = 1;
3501 out:
3502 srcu_read_unlock(&kvm->srcu, idx);
3503 return ret;
3504 }
3505
3506 static void seg_setup(int seg)
3507 {
3508 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3509 unsigned int ar;
3510
3511 vmcs_write16(sf->selector, 0);
3512 vmcs_writel(sf->base, 0);
3513 vmcs_write32(sf->limit, 0xffff);
3514 if (enable_unrestricted_guest) {
3515 ar = 0x93;
3516 if (seg == VCPU_SREG_CS)
3517 ar |= 0x08; /* code segment */
3518 } else
3519 ar = 0xf3;
3520
3521 vmcs_write32(sf->ar_bytes, ar);
3522 }
3523
3524 static int alloc_apic_access_page(struct kvm *kvm)
3525 {
3526 struct kvm_userspace_memory_region kvm_userspace_mem;
3527 int r = 0;
3528
3529 mutex_lock(&kvm->slots_lock);
3530 if (kvm->arch.apic_access_page)
3531 goto out;
3532 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3533 kvm_userspace_mem.flags = 0;
3534 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3535 kvm_userspace_mem.memory_size = PAGE_SIZE;
3536 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3537 if (r)
3538 goto out;
3539
3540 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3541 out:
3542 mutex_unlock(&kvm->slots_lock);
3543 return r;
3544 }
3545
3546 static int alloc_identity_pagetable(struct kvm *kvm)
3547 {
3548 struct kvm_userspace_memory_region kvm_userspace_mem;
3549 int r = 0;
3550
3551 mutex_lock(&kvm->slots_lock);
3552 if (kvm->arch.ept_identity_pagetable)
3553 goto out;
3554 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3555 kvm_userspace_mem.flags = 0;
3556 kvm_userspace_mem.guest_phys_addr =
3557 kvm->arch.ept_identity_map_addr;
3558 kvm_userspace_mem.memory_size = PAGE_SIZE;
3559 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3560 if (r)
3561 goto out;
3562
3563 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3564 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3565 out:
3566 mutex_unlock(&kvm->slots_lock);
3567 return r;
3568 }
3569
3570 static void allocate_vpid(struct vcpu_vmx *vmx)
3571 {
3572 int vpid;
3573
3574 vmx->vpid = 0;
3575 if (!enable_vpid)
3576 return;
3577 spin_lock(&vmx_vpid_lock);
3578 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3579 if (vpid < VMX_NR_VPIDS) {
3580 vmx->vpid = vpid;
3581 __set_bit(vpid, vmx_vpid_bitmap);
3582 }
3583 spin_unlock(&vmx_vpid_lock);
3584 }
3585
3586 static void free_vpid(struct vcpu_vmx *vmx)
3587 {
3588 if (!enable_vpid)
3589 return;
3590 spin_lock(&vmx_vpid_lock);
3591 if (vmx->vpid != 0)
3592 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3593 spin_unlock(&vmx_vpid_lock);
3594 }
3595
3596 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3597 {
3598 int f = sizeof(unsigned long);
3599
3600 if (!cpu_has_vmx_msr_bitmap())
3601 return;
3602
3603 /*
3604 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3605 * have the write-low and read-high bitmap offsets the wrong way round.
3606 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3607 */
3608 if (msr <= 0x1fff) {
3609 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3610 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3611 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3612 msr &= 0x1fff;
3613 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3614 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3615 }
3616 }
3617
3618 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3619 {
3620 if (!longmode_only)
3621 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3622 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3623 }
3624
3625 /*
3626 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3627 * will not change in the lifetime of the guest.
3628 * Note that host-state that does change is set elsewhere. E.g., host-state
3629 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3630 */
3631 static void vmx_set_constant_host_state(void)
3632 {
3633 u32 low32, high32;
3634 unsigned long tmpl;
3635 struct desc_ptr dt;
3636
3637 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3638 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3639 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3640
3641 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3642 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3643 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3644 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3645 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3646
3647 native_store_idt(&dt);
3648 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3649
3650 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3651 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3652
3653 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3654 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3655 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3656 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3657
3658 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3659 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3660 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3661 }
3662 }
3663
3664 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3665 {
3666 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3667 if (enable_ept)
3668 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3669 if (is_guest_mode(&vmx->vcpu))
3670 vmx->vcpu.arch.cr4_guest_owned_bits &=
3671 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3672 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3673 }
3674
3675 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3676 {
3677 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3678 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3679 exec_control &= ~CPU_BASED_TPR_SHADOW;
3680 #ifdef CONFIG_X86_64
3681 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3682 CPU_BASED_CR8_LOAD_EXITING;
3683 #endif
3684 }
3685 if (!enable_ept)
3686 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3687 CPU_BASED_CR3_LOAD_EXITING |
3688 CPU_BASED_INVLPG_EXITING;
3689 return exec_control;
3690 }
3691
3692 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3693 {
3694 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3695 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3696 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3697 if (vmx->vpid == 0)
3698 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3699 if (!enable_ept) {
3700 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3701 enable_unrestricted_guest = 0;
3702 }
3703 if (!enable_unrestricted_guest)
3704 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3705 if (!ple_gap)
3706 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3707 return exec_control;
3708 }
3709
3710 static void ept_set_mmio_spte_mask(void)
3711 {
3712 /*
3713 * EPT Misconfigurations can be generated if the value of bits 2:0
3714 * of an EPT paging-structure entry is 110b (write/execute).
3715 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3716 * spte.
3717 */
3718 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3719 }
3720
3721 /*
3722 * Sets up the vmcs for emulated real mode.
3723 */
3724 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3725 {
3726 #ifdef CONFIG_X86_64
3727 unsigned long a;
3728 #endif
3729 int i;
3730
3731 /* I/O */
3732 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3733 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3734
3735 if (cpu_has_vmx_msr_bitmap())
3736 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3737
3738 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3739
3740 /* Control */
3741 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3742 vmcs_config.pin_based_exec_ctrl);
3743
3744 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3745
3746 if (cpu_has_secondary_exec_ctrls()) {
3747 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3748 vmx_secondary_exec_control(vmx));
3749 }
3750
3751 if (ple_gap) {
3752 vmcs_write32(PLE_GAP, ple_gap);
3753 vmcs_write32(PLE_WINDOW, ple_window);
3754 }
3755
3756 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3757 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3758 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3759
3760 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3761 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3762 vmx_set_constant_host_state();
3763 #ifdef CONFIG_X86_64
3764 rdmsrl(MSR_FS_BASE, a);
3765 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3766 rdmsrl(MSR_GS_BASE, a);
3767 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3768 #else
3769 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3770 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3771 #endif
3772
3773 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3774 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3775 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3776 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3777 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3778
3779 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3780 u32 msr_low, msr_high;
3781 u64 host_pat;
3782 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3783 host_pat = msr_low | ((u64) msr_high << 32);
3784 /* Write the default value follow host pat */
3785 vmcs_write64(GUEST_IA32_PAT, host_pat);
3786 /* Keep arch.pat sync with GUEST_IA32_PAT */
3787 vmx->vcpu.arch.pat = host_pat;
3788 }
3789
3790 for (i = 0; i < NR_VMX_MSR; ++i) {
3791 u32 index = vmx_msr_index[i];
3792 u32 data_low, data_high;
3793 int j = vmx->nmsrs;
3794
3795 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3796 continue;
3797 if (wrmsr_safe(index, data_low, data_high) < 0)
3798 continue;
3799 vmx->guest_msrs[j].index = i;
3800 vmx->guest_msrs[j].data = 0;
3801 vmx->guest_msrs[j].mask = -1ull;
3802 ++vmx->nmsrs;
3803 }
3804
3805 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3806
3807 /* 22.2.1, 20.8.1 */
3808 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3809
3810 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3811 set_cr4_guest_host_mask(vmx);
3812
3813 kvm_write_tsc(&vmx->vcpu, 0);
3814
3815 return 0;
3816 }
3817
3818 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3819 {
3820 struct vcpu_vmx *vmx = to_vmx(vcpu);
3821 u64 msr;
3822 int ret;
3823
3824 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3825
3826 vmx->rmode.vm86_active = 0;
3827
3828 vmx->soft_vnmi_blocked = 0;
3829
3830 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3831 kvm_set_cr8(&vmx->vcpu, 0);
3832 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3833 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3834 msr |= MSR_IA32_APICBASE_BSP;
3835 kvm_set_apic_base(&vmx->vcpu, msr);
3836
3837 ret = fx_init(&vmx->vcpu);
3838 if (ret != 0)
3839 goto out;
3840
3841 vmx_segment_cache_clear(vmx);
3842
3843 seg_setup(VCPU_SREG_CS);
3844 /*
3845 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3846 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3847 */
3848 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3849 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3850 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3851 } else {
3852 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3853 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3854 }
3855
3856 seg_setup(VCPU_SREG_DS);
3857 seg_setup(VCPU_SREG_ES);
3858 seg_setup(VCPU_SREG_FS);
3859 seg_setup(VCPU_SREG_GS);
3860 seg_setup(VCPU_SREG_SS);
3861
3862 vmcs_write16(GUEST_TR_SELECTOR, 0);
3863 vmcs_writel(GUEST_TR_BASE, 0);
3864 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3865 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3866
3867 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3868 vmcs_writel(GUEST_LDTR_BASE, 0);
3869 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3870 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3871
3872 vmcs_write32(GUEST_SYSENTER_CS, 0);
3873 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3874 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3875
3876 vmcs_writel(GUEST_RFLAGS, 0x02);
3877 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3878 kvm_rip_write(vcpu, 0xfff0);
3879 else
3880 kvm_rip_write(vcpu, 0);
3881 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3882
3883 vmcs_writel(GUEST_DR7, 0x400);
3884
3885 vmcs_writel(GUEST_GDTR_BASE, 0);
3886 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3887
3888 vmcs_writel(GUEST_IDTR_BASE, 0);
3889 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3890
3891 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3892 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3893 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3894
3895 /* Special registers */
3896 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3897
3898 setup_msrs(vmx);
3899
3900 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3901
3902 if (cpu_has_vmx_tpr_shadow()) {
3903 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3904 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3905 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3906 __pa(vmx->vcpu.arch.apic->regs));
3907 vmcs_write32(TPR_THRESHOLD, 0);
3908 }
3909
3910 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3911 vmcs_write64(APIC_ACCESS_ADDR,
3912 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3913
3914 if (vmx->vpid != 0)
3915 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3916
3917 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3918 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3919 vmx_set_cr4(&vmx->vcpu, 0);
3920 vmx_set_efer(&vmx->vcpu, 0);
3921 vmx_fpu_activate(&vmx->vcpu);
3922 update_exception_bitmap(&vmx->vcpu);
3923
3924 vpid_sync_context(vmx);
3925
3926 ret = 0;
3927
3928 /* HACK: Don't enable emulation on guest boot/reset */
3929 vmx->emulation_required = 0;
3930
3931 out:
3932 return ret;
3933 }
3934
3935 /*
3936 * In nested virtualization, check if L1 asked to exit on external interrupts.
3937 * For most existing hypervisors, this will always return true.
3938 */
3939 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3940 {
3941 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3942 PIN_BASED_EXT_INTR_MASK;
3943 }
3944
3945 static void enable_irq_window(struct kvm_vcpu *vcpu)
3946 {
3947 u32 cpu_based_vm_exec_control;
3948 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3949 /* We can get here when nested_run_pending caused
3950 * vmx_interrupt_allowed() to return false. In this case, do
3951 * nothing - the interrupt will be injected later.
3952 */
3953 return;
3954
3955 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3956 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3957 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3958 }
3959
3960 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3961 {
3962 u32 cpu_based_vm_exec_control;
3963
3964 if (!cpu_has_virtual_nmis()) {
3965 enable_irq_window(vcpu);
3966 return;
3967 }
3968
3969 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3970 enable_irq_window(vcpu);
3971 return;
3972 }
3973 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3974 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3975 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3976 }
3977
3978 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3979 {
3980 struct vcpu_vmx *vmx = to_vmx(vcpu);
3981 uint32_t intr;
3982 int irq = vcpu->arch.interrupt.nr;
3983
3984 trace_kvm_inj_virq(irq);
3985
3986 ++vcpu->stat.irq_injections;
3987 if (vmx->rmode.vm86_active) {
3988 int inc_eip = 0;
3989 if (vcpu->arch.interrupt.soft)
3990 inc_eip = vcpu->arch.event_exit_inst_len;
3991 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3992 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3993 return;
3994 }
3995 intr = irq | INTR_INFO_VALID_MASK;
3996 if (vcpu->arch.interrupt.soft) {
3997 intr |= INTR_TYPE_SOFT_INTR;
3998 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3999 vmx->vcpu.arch.event_exit_inst_len);
4000 } else
4001 intr |= INTR_TYPE_EXT_INTR;
4002 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4003 vmx_clear_hlt(vcpu);
4004 }
4005
4006 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4007 {
4008 struct vcpu_vmx *vmx = to_vmx(vcpu);
4009
4010 if (is_guest_mode(vcpu))
4011 return;
4012
4013 if (!cpu_has_virtual_nmis()) {
4014 /*
4015 * Tracking the NMI-blocked state in software is built upon
4016 * finding the next open IRQ window. This, in turn, depends on
4017 * well-behaving guests: They have to keep IRQs disabled at
4018 * least as long as the NMI handler runs. Otherwise we may
4019 * cause NMI nesting, maybe breaking the guest. But as this is
4020 * highly unlikely, we can live with the residual risk.
4021 */
4022 vmx->soft_vnmi_blocked = 1;
4023 vmx->vnmi_blocked_time = 0;
4024 }
4025
4026 ++vcpu->stat.nmi_injections;
4027 vmx->nmi_known_unmasked = false;
4028 if (vmx->rmode.vm86_active) {
4029 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4030 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4031 return;
4032 }
4033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4034 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4035 vmx_clear_hlt(vcpu);
4036 }
4037
4038 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4039 {
4040 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4041 return 0;
4042
4043 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4044 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4045 | GUEST_INTR_STATE_NMI));
4046 }
4047
4048 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4049 {
4050 if (!cpu_has_virtual_nmis())
4051 return to_vmx(vcpu)->soft_vnmi_blocked;
4052 if (to_vmx(vcpu)->nmi_known_unmasked)
4053 return false;
4054 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4055 }
4056
4057 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4058 {
4059 struct vcpu_vmx *vmx = to_vmx(vcpu);
4060
4061 if (!cpu_has_virtual_nmis()) {
4062 if (vmx->soft_vnmi_blocked != masked) {
4063 vmx->soft_vnmi_blocked = masked;
4064 vmx->vnmi_blocked_time = 0;
4065 }
4066 } else {
4067 vmx->nmi_known_unmasked = !masked;
4068 if (masked)
4069 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4070 GUEST_INTR_STATE_NMI);
4071 else
4072 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4073 GUEST_INTR_STATE_NMI);
4074 }
4075 }
4076
4077 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4078 {
4079 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4080 struct vmcs12 *vmcs12;
4081 if (to_vmx(vcpu)->nested.nested_run_pending)
4082 return 0;
4083 nested_vmx_vmexit(vcpu);
4084 vmcs12 = get_vmcs12(vcpu);
4085 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4086 vmcs12->vm_exit_intr_info = 0;
4087 /* fall through to normal code, but now in L1, not L2 */
4088 }
4089
4090 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4091 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4092 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4093 }
4094
4095 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4096 {
4097 int ret;
4098 struct kvm_userspace_memory_region tss_mem = {
4099 .slot = TSS_PRIVATE_MEMSLOT,
4100 .guest_phys_addr = addr,
4101 .memory_size = PAGE_SIZE * 3,
4102 .flags = 0,
4103 };
4104
4105 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4106 if (ret)
4107 return ret;
4108 kvm->arch.tss_addr = addr;
4109 if (!init_rmode_tss(kvm))
4110 return -ENOMEM;
4111
4112 return 0;
4113 }
4114
4115 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4116 int vec, u32 err_code)
4117 {
4118 /*
4119 * Instruction with address size override prefix opcode 0x67
4120 * Cause the #SS fault with 0 error code in VM86 mode.
4121 */
4122 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4123 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4124 return 1;
4125 /*
4126 * Forward all other exceptions that are valid in real mode.
4127 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4128 * the required debugging infrastructure rework.
4129 */
4130 switch (vec) {
4131 case DB_VECTOR:
4132 if (vcpu->guest_debug &
4133 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4134 return 0;
4135 kvm_queue_exception(vcpu, vec);
4136 return 1;
4137 case BP_VECTOR:
4138 /*
4139 * Update instruction length as we may reinject the exception
4140 * from user space while in guest debugging mode.
4141 */
4142 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4143 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4144 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4145 return 0;
4146 /* fall through */
4147 case DE_VECTOR:
4148 case OF_VECTOR:
4149 case BR_VECTOR:
4150 case UD_VECTOR:
4151 case DF_VECTOR:
4152 case SS_VECTOR:
4153 case GP_VECTOR:
4154 case MF_VECTOR:
4155 kvm_queue_exception(vcpu, vec);
4156 return 1;
4157 }
4158 return 0;
4159 }
4160
4161 /*
4162 * Trigger machine check on the host. We assume all the MSRs are already set up
4163 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4164 * We pass a fake environment to the machine check handler because we want
4165 * the guest to be always treated like user space, no matter what context
4166 * it used internally.
4167 */
4168 static void kvm_machine_check(void)
4169 {
4170 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4171 struct pt_regs regs = {
4172 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4173 .flags = X86_EFLAGS_IF,
4174 };
4175
4176 do_machine_check(&regs, 0);
4177 #endif
4178 }
4179
4180 static int handle_machine_check(struct kvm_vcpu *vcpu)
4181 {
4182 /* already handled by vcpu_run */
4183 return 1;
4184 }
4185
4186 static int handle_exception(struct kvm_vcpu *vcpu)
4187 {
4188 struct vcpu_vmx *vmx = to_vmx(vcpu);
4189 struct kvm_run *kvm_run = vcpu->run;
4190 u32 intr_info, ex_no, error_code;
4191 unsigned long cr2, rip, dr6;
4192 u32 vect_info;
4193 enum emulation_result er;
4194
4195 vect_info = vmx->idt_vectoring_info;
4196 intr_info = vmx->exit_intr_info;
4197
4198 if (is_machine_check(intr_info))
4199 return handle_machine_check(vcpu);
4200
4201 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4202 !is_page_fault(intr_info)) {
4203 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4204 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4205 vcpu->run->internal.ndata = 2;
4206 vcpu->run->internal.data[0] = vect_info;
4207 vcpu->run->internal.data[1] = intr_info;
4208 return 0;
4209 }
4210
4211 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4212 return 1; /* already handled by vmx_vcpu_run() */
4213
4214 if (is_no_device(intr_info)) {
4215 vmx_fpu_activate(vcpu);
4216 return 1;
4217 }
4218
4219 if (is_invalid_opcode(intr_info)) {
4220 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4221 if (er != EMULATE_DONE)
4222 kvm_queue_exception(vcpu, UD_VECTOR);
4223 return 1;
4224 }
4225
4226 error_code = 0;
4227 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4228 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4229 if (is_page_fault(intr_info)) {
4230 /* EPT won't cause page fault directly */
4231 BUG_ON(enable_ept);
4232 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4233 trace_kvm_page_fault(cr2, error_code);
4234
4235 if (kvm_event_needs_reinjection(vcpu))
4236 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4237 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4238 }
4239
4240 if (vmx->rmode.vm86_active &&
4241 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4242 error_code)) {
4243 if (vcpu->arch.halt_request) {
4244 vcpu->arch.halt_request = 0;
4245 return kvm_emulate_halt(vcpu);
4246 }
4247 return 1;
4248 }
4249
4250 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4251 switch (ex_no) {
4252 case DB_VECTOR:
4253 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4254 if (!(vcpu->guest_debug &
4255 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4256 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4257 kvm_queue_exception(vcpu, DB_VECTOR);
4258 return 1;
4259 }
4260 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4261 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4262 /* fall through */
4263 case BP_VECTOR:
4264 /*
4265 * Update instruction length as we may reinject #BP from
4266 * user space while in guest debugging mode. Reading it for
4267 * #DB as well causes no harm, it is not used in that case.
4268 */
4269 vmx->vcpu.arch.event_exit_inst_len =
4270 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4271 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4272 rip = kvm_rip_read(vcpu);
4273 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4274 kvm_run->debug.arch.exception = ex_no;
4275 break;
4276 default:
4277 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4278 kvm_run->ex.exception = ex_no;
4279 kvm_run->ex.error_code = error_code;
4280 break;
4281 }
4282 return 0;
4283 }
4284
4285 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4286 {
4287 ++vcpu->stat.irq_exits;
4288 return 1;
4289 }
4290
4291 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4292 {
4293 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4294 return 0;
4295 }
4296
4297 static int handle_io(struct kvm_vcpu *vcpu)
4298 {
4299 unsigned long exit_qualification;
4300 int size, in, string;
4301 unsigned port;
4302
4303 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4304 string = (exit_qualification & 16) != 0;
4305 in = (exit_qualification & 8) != 0;
4306
4307 ++vcpu->stat.io_exits;
4308
4309 if (string || in)
4310 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4311
4312 port = exit_qualification >> 16;
4313 size = (exit_qualification & 7) + 1;
4314 skip_emulated_instruction(vcpu);
4315
4316 return kvm_fast_pio_out(vcpu, size, port);
4317 }
4318
4319 static void
4320 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4321 {
4322 /*
4323 * Patch in the VMCALL instruction:
4324 */
4325 hypercall[0] = 0x0f;
4326 hypercall[1] = 0x01;
4327 hypercall[2] = 0xc1;
4328 }
4329
4330 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4331 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4332 {
4333 if (to_vmx(vcpu)->nested.vmxon &&
4334 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4335 return 1;
4336
4337 if (is_guest_mode(vcpu)) {
4338 /*
4339 * We get here when L2 changed cr0 in a way that did not change
4340 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4341 * but did change L0 shadowed bits. This can currently happen
4342 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4343 * loading) while pretending to allow the guest to change it.
4344 */
4345 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4346 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4347 return 1;
4348 vmcs_writel(CR0_READ_SHADOW, val);
4349 return 0;
4350 } else
4351 return kvm_set_cr0(vcpu, val);
4352 }
4353
4354 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4355 {
4356 if (is_guest_mode(vcpu)) {
4357 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4358 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4359 return 1;
4360 vmcs_writel(CR4_READ_SHADOW, val);
4361 return 0;
4362 } else
4363 return kvm_set_cr4(vcpu, val);
4364 }
4365
4366 /* called to set cr0 as approriate for clts instruction exit. */
4367 static void handle_clts(struct kvm_vcpu *vcpu)
4368 {
4369 if (is_guest_mode(vcpu)) {
4370 /*
4371 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4372 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4373 * just pretend it's off (also in arch.cr0 for fpu_activate).
4374 */
4375 vmcs_writel(CR0_READ_SHADOW,
4376 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4377 vcpu->arch.cr0 &= ~X86_CR0_TS;
4378 } else
4379 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4380 }
4381
4382 static int handle_cr(struct kvm_vcpu *vcpu)
4383 {
4384 unsigned long exit_qualification, val;
4385 int cr;
4386 int reg;
4387 int err;
4388
4389 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4390 cr = exit_qualification & 15;
4391 reg = (exit_qualification >> 8) & 15;
4392 switch ((exit_qualification >> 4) & 3) {
4393 case 0: /* mov to cr */
4394 val = kvm_register_read(vcpu, reg);
4395 trace_kvm_cr_write(cr, val);
4396 switch (cr) {
4397 case 0:
4398 err = handle_set_cr0(vcpu, val);
4399 kvm_complete_insn_gp(vcpu, err);
4400 return 1;
4401 case 3:
4402 err = kvm_set_cr3(vcpu, val);
4403 kvm_complete_insn_gp(vcpu, err);
4404 return 1;
4405 case 4:
4406 err = handle_set_cr4(vcpu, val);
4407 kvm_complete_insn_gp(vcpu, err);
4408 return 1;
4409 case 8: {
4410 u8 cr8_prev = kvm_get_cr8(vcpu);
4411 u8 cr8 = kvm_register_read(vcpu, reg);
4412 err = kvm_set_cr8(vcpu, cr8);
4413 kvm_complete_insn_gp(vcpu, err);
4414 if (irqchip_in_kernel(vcpu->kvm))
4415 return 1;
4416 if (cr8_prev <= cr8)
4417 return 1;
4418 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4419 return 0;
4420 }
4421 };
4422 break;
4423 case 2: /* clts */
4424 handle_clts(vcpu);
4425 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4426 skip_emulated_instruction(vcpu);
4427 vmx_fpu_activate(vcpu);
4428 return 1;
4429 case 1: /*mov from cr*/
4430 switch (cr) {
4431 case 3:
4432 val = kvm_read_cr3(vcpu);
4433 kvm_register_write(vcpu, reg, val);
4434 trace_kvm_cr_read(cr, val);
4435 skip_emulated_instruction(vcpu);
4436 return 1;
4437 case 8:
4438 val = kvm_get_cr8(vcpu);
4439 kvm_register_write(vcpu, reg, val);
4440 trace_kvm_cr_read(cr, val);
4441 skip_emulated_instruction(vcpu);
4442 return 1;
4443 }
4444 break;
4445 case 3: /* lmsw */
4446 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4447 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4448 kvm_lmsw(vcpu, val);
4449
4450 skip_emulated_instruction(vcpu);
4451 return 1;
4452 default:
4453 break;
4454 }
4455 vcpu->run->exit_reason = 0;
4456 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4457 (int)(exit_qualification >> 4) & 3, cr);
4458 return 0;
4459 }
4460
4461 static int handle_dr(struct kvm_vcpu *vcpu)
4462 {
4463 unsigned long exit_qualification;
4464 int dr, reg;
4465
4466 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4467 if (!kvm_require_cpl(vcpu, 0))
4468 return 1;
4469 dr = vmcs_readl(GUEST_DR7);
4470 if (dr & DR7_GD) {
4471 /*
4472 * As the vm-exit takes precedence over the debug trap, we
4473 * need to emulate the latter, either for the host or the
4474 * guest debugging itself.
4475 */
4476 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4477 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4478 vcpu->run->debug.arch.dr7 = dr;
4479 vcpu->run->debug.arch.pc =
4480 vmcs_readl(GUEST_CS_BASE) +
4481 vmcs_readl(GUEST_RIP);
4482 vcpu->run->debug.arch.exception = DB_VECTOR;
4483 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4484 return 0;
4485 } else {
4486 vcpu->arch.dr7 &= ~DR7_GD;
4487 vcpu->arch.dr6 |= DR6_BD;
4488 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4489 kvm_queue_exception(vcpu, DB_VECTOR);
4490 return 1;
4491 }
4492 }
4493
4494 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4495 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4496 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4497 if (exit_qualification & TYPE_MOV_FROM_DR) {
4498 unsigned long val;
4499 if (!kvm_get_dr(vcpu, dr, &val))
4500 kvm_register_write(vcpu, reg, val);
4501 } else
4502 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4503 skip_emulated_instruction(vcpu);
4504 return 1;
4505 }
4506
4507 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4508 {
4509 vmcs_writel(GUEST_DR7, val);
4510 }
4511
4512 static int handle_cpuid(struct kvm_vcpu *vcpu)
4513 {
4514 kvm_emulate_cpuid(vcpu);
4515 return 1;
4516 }
4517
4518 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4519 {
4520 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4521 u64 data;
4522
4523 if (vmx_get_msr(vcpu, ecx, &data)) {
4524 trace_kvm_msr_read_ex(ecx);
4525 kvm_inject_gp(vcpu, 0);
4526 return 1;
4527 }
4528
4529 trace_kvm_msr_read(ecx, data);
4530
4531 /* FIXME: handling of bits 32:63 of rax, rdx */
4532 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4533 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4534 skip_emulated_instruction(vcpu);
4535 return 1;
4536 }
4537
4538 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4539 {
4540 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4541 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4542 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4543
4544 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4545 trace_kvm_msr_write_ex(ecx, data);
4546 kvm_inject_gp(vcpu, 0);
4547 return 1;
4548 }
4549
4550 trace_kvm_msr_write(ecx, data);
4551 skip_emulated_instruction(vcpu);
4552 return 1;
4553 }
4554
4555 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4556 {
4557 kvm_make_request(KVM_REQ_EVENT, vcpu);
4558 return 1;
4559 }
4560
4561 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4562 {
4563 u32 cpu_based_vm_exec_control;
4564
4565 /* clear pending irq */
4566 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4567 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4568 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4569
4570 kvm_make_request(KVM_REQ_EVENT, vcpu);
4571
4572 ++vcpu->stat.irq_window_exits;
4573
4574 /*
4575 * If the user space waits to inject interrupts, exit as soon as
4576 * possible
4577 */
4578 if (!irqchip_in_kernel(vcpu->kvm) &&
4579 vcpu->run->request_interrupt_window &&
4580 !kvm_cpu_has_interrupt(vcpu)) {
4581 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4582 return 0;
4583 }
4584 return 1;
4585 }
4586
4587 static int handle_halt(struct kvm_vcpu *vcpu)
4588 {
4589 skip_emulated_instruction(vcpu);
4590 return kvm_emulate_halt(vcpu);
4591 }
4592
4593 static int handle_vmcall(struct kvm_vcpu *vcpu)
4594 {
4595 skip_emulated_instruction(vcpu);
4596 kvm_emulate_hypercall(vcpu);
4597 return 1;
4598 }
4599
4600 static int handle_invd(struct kvm_vcpu *vcpu)
4601 {
4602 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4603 }
4604
4605 static int handle_invlpg(struct kvm_vcpu *vcpu)
4606 {
4607 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4608
4609 kvm_mmu_invlpg(vcpu, exit_qualification);
4610 skip_emulated_instruction(vcpu);
4611 return 1;
4612 }
4613
4614 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4615 {
4616 skip_emulated_instruction(vcpu);
4617 kvm_emulate_wbinvd(vcpu);
4618 return 1;
4619 }
4620
4621 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4622 {
4623 u64 new_bv = kvm_read_edx_eax(vcpu);
4624 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4625
4626 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4627 skip_emulated_instruction(vcpu);
4628 return 1;
4629 }
4630
4631 static int handle_apic_access(struct kvm_vcpu *vcpu)
4632 {
4633 if (likely(fasteoi)) {
4634 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4635 int access_type, offset;
4636
4637 access_type = exit_qualification & APIC_ACCESS_TYPE;
4638 offset = exit_qualification & APIC_ACCESS_OFFSET;
4639 /*
4640 * Sane guest uses MOV to write EOI, with written value
4641 * not cared. So make a short-circuit here by avoiding
4642 * heavy instruction emulation.
4643 */
4644 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4645 (offset == APIC_EOI)) {
4646 kvm_lapic_set_eoi(vcpu);
4647 skip_emulated_instruction(vcpu);
4648 return 1;
4649 }
4650 }
4651 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4652 }
4653
4654 static int handle_task_switch(struct kvm_vcpu *vcpu)
4655 {
4656 struct vcpu_vmx *vmx = to_vmx(vcpu);
4657 unsigned long exit_qualification;
4658 bool has_error_code = false;
4659 u32 error_code = 0;
4660 u16 tss_selector;
4661 int reason, type, idt_v;
4662
4663 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4664 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4665
4666 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4667
4668 reason = (u32)exit_qualification >> 30;
4669 if (reason == TASK_SWITCH_GATE && idt_v) {
4670 switch (type) {
4671 case INTR_TYPE_NMI_INTR:
4672 vcpu->arch.nmi_injected = false;
4673 vmx_set_nmi_mask(vcpu, true);
4674 break;
4675 case INTR_TYPE_EXT_INTR:
4676 case INTR_TYPE_SOFT_INTR:
4677 kvm_clear_interrupt_queue(vcpu);
4678 break;
4679 case INTR_TYPE_HARD_EXCEPTION:
4680 if (vmx->idt_vectoring_info &
4681 VECTORING_INFO_DELIVER_CODE_MASK) {
4682 has_error_code = true;
4683 error_code =
4684 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4685 }
4686 /* fall through */
4687 case INTR_TYPE_SOFT_EXCEPTION:
4688 kvm_clear_exception_queue(vcpu);
4689 break;
4690 default:
4691 break;
4692 }
4693 }
4694 tss_selector = exit_qualification;
4695
4696 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4697 type != INTR_TYPE_EXT_INTR &&
4698 type != INTR_TYPE_NMI_INTR))
4699 skip_emulated_instruction(vcpu);
4700
4701 if (kvm_task_switch(vcpu, tss_selector, reason,
4702 has_error_code, error_code) == EMULATE_FAIL) {
4703 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4704 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4705 vcpu->run->internal.ndata = 0;
4706 return 0;
4707 }
4708
4709 /* clear all local breakpoint enable flags */
4710 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4711
4712 /*
4713 * TODO: What about debug traps on tss switch?
4714 * Are we supposed to inject them and update dr6?
4715 */
4716
4717 return 1;
4718 }
4719
4720 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4721 {
4722 unsigned long exit_qualification;
4723 gpa_t gpa;
4724 int gla_validity;
4725
4726 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4727
4728 if (exit_qualification & (1 << 6)) {
4729 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4730 return -EINVAL;
4731 }
4732
4733 gla_validity = (exit_qualification >> 7) & 0x3;
4734 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4735 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4736 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4737 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4738 vmcs_readl(GUEST_LINEAR_ADDRESS));
4739 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4740 (long unsigned int)exit_qualification);
4741 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4742 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4743 return 0;
4744 }
4745
4746 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4747 trace_kvm_page_fault(gpa, exit_qualification);
4748 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4749 }
4750
4751 static u64 ept_rsvd_mask(u64 spte, int level)
4752 {
4753 int i;
4754 u64 mask = 0;
4755
4756 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4757 mask |= (1ULL << i);
4758
4759 if (level > 2)
4760 /* bits 7:3 reserved */
4761 mask |= 0xf8;
4762 else if (level == 2) {
4763 if (spte & (1ULL << 7))
4764 /* 2MB ref, bits 20:12 reserved */
4765 mask |= 0x1ff000;
4766 else
4767 /* bits 6:3 reserved */
4768 mask |= 0x78;
4769 }
4770
4771 return mask;
4772 }
4773
4774 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4775 int level)
4776 {
4777 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4778
4779 /* 010b (write-only) */
4780 WARN_ON((spte & 0x7) == 0x2);
4781
4782 /* 110b (write/execute) */
4783 WARN_ON((spte & 0x7) == 0x6);
4784
4785 /* 100b (execute-only) and value not supported by logical processor */
4786 if (!cpu_has_vmx_ept_execute_only())
4787 WARN_ON((spte & 0x7) == 0x4);
4788
4789 /* not 000b */
4790 if ((spte & 0x7)) {
4791 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4792
4793 if (rsvd_bits != 0) {
4794 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4795 __func__, rsvd_bits);
4796 WARN_ON(1);
4797 }
4798
4799 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4800 u64 ept_mem_type = (spte & 0x38) >> 3;
4801
4802 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4803 ept_mem_type == 7) {
4804 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4805 __func__, ept_mem_type);
4806 WARN_ON(1);
4807 }
4808 }
4809 }
4810 }
4811
4812 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4813 {
4814 u64 sptes[4];
4815 int nr_sptes, i, ret;
4816 gpa_t gpa;
4817
4818 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4819
4820 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4821 if (likely(ret == 1))
4822 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4823 EMULATE_DONE;
4824 if (unlikely(!ret))
4825 return 1;
4826
4827 /* It is the real ept misconfig */
4828 printk(KERN_ERR "EPT: Misconfiguration.\n");
4829 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4830
4831 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4832
4833 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4834 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4835
4836 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4837 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4838
4839 return 0;
4840 }
4841
4842 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4843 {
4844 u32 cpu_based_vm_exec_control;
4845
4846 /* clear pending NMI */
4847 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4848 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4849 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4850 ++vcpu->stat.nmi_window_exits;
4851 kvm_make_request(KVM_REQ_EVENT, vcpu);
4852
4853 return 1;
4854 }
4855
4856 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4857 {
4858 struct vcpu_vmx *vmx = to_vmx(vcpu);
4859 enum emulation_result err = EMULATE_DONE;
4860 int ret = 1;
4861 u32 cpu_exec_ctrl;
4862 bool intr_window_requested;
4863
4864 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4865 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4866
4867 while (!guest_state_valid(vcpu)) {
4868 if (intr_window_requested
4869 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4870 return handle_interrupt_window(&vmx->vcpu);
4871
4872 err = emulate_instruction(vcpu, 0);
4873
4874 if (err == EMULATE_DO_MMIO) {
4875 ret = 0;
4876 goto out;
4877 }
4878
4879 if (err != EMULATE_DONE)
4880 return 0;
4881
4882 if (signal_pending(current))
4883 goto out;
4884 if (need_resched())
4885 schedule();
4886 }
4887
4888 vmx->emulation_required = 0;
4889 out:
4890 return ret;
4891 }
4892
4893 /*
4894 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4895 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4896 */
4897 static int handle_pause(struct kvm_vcpu *vcpu)
4898 {
4899 skip_emulated_instruction(vcpu);
4900 kvm_vcpu_on_spin(vcpu);
4901
4902 return 1;
4903 }
4904
4905 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4906 {
4907 kvm_queue_exception(vcpu, UD_VECTOR);
4908 return 1;
4909 }
4910
4911 /*
4912 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4913 * We could reuse a single VMCS for all the L2 guests, but we also want the
4914 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4915 * allows keeping them loaded on the processor, and in the future will allow
4916 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4917 * every entry if they never change.
4918 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4919 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4920 *
4921 * The following functions allocate and free a vmcs02 in this pool.
4922 */
4923
4924 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4925 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4926 {
4927 struct vmcs02_list *item;
4928 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4929 if (item->vmptr == vmx->nested.current_vmptr) {
4930 list_move(&item->list, &vmx->nested.vmcs02_pool);
4931 return &item->vmcs02;
4932 }
4933
4934 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4935 /* Recycle the least recently used VMCS. */
4936 item = list_entry(vmx->nested.vmcs02_pool.prev,
4937 struct vmcs02_list, list);
4938 item->vmptr = vmx->nested.current_vmptr;
4939 list_move(&item->list, &vmx->nested.vmcs02_pool);
4940 return &item->vmcs02;
4941 }
4942
4943 /* Create a new VMCS */
4944 item = (struct vmcs02_list *)
4945 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4946 if (!item)
4947 return NULL;
4948 item->vmcs02.vmcs = alloc_vmcs();
4949 if (!item->vmcs02.vmcs) {
4950 kfree(item);
4951 return NULL;
4952 }
4953 loaded_vmcs_init(&item->vmcs02);
4954 item->vmptr = vmx->nested.current_vmptr;
4955 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4956 vmx->nested.vmcs02_num++;
4957 return &item->vmcs02;
4958 }
4959
4960 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4961 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4962 {
4963 struct vmcs02_list *item;
4964 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4965 if (item->vmptr == vmptr) {
4966 free_loaded_vmcs(&item->vmcs02);
4967 list_del(&item->list);
4968 kfree(item);
4969 vmx->nested.vmcs02_num--;
4970 return;
4971 }
4972 }
4973
4974 /*
4975 * Free all VMCSs saved for this vcpu, except the one pointed by
4976 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4977 * currently used, if running L2), and vmcs01 when running L2.
4978 */
4979 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4980 {
4981 struct vmcs02_list *item, *n;
4982 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4983 if (vmx->loaded_vmcs != &item->vmcs02)
4984 free_loaded_vmcs(&item->vmcs02);
4985 list_del(&item->list);
4986 kfree(item);
4987 }
4988 vmx->nested.vmcs02_num = 0;
4989
4990 if (vmx->loaded_vmcs != &vmx->vmcs01)
4991 free_loaded_vmcs(&vmx->vmcs01);
4992 }
4993
4994 /*
4995 * Emulate the VMXON instruction.
4996 * Currently, we just remember that VMX is active, and do not save or even
4997 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4998 * do not currently need to store anything in that guest-allocated memory
4999 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5000 * argument is different from the VMXON pointer (which the spec says they do).
5001 */
5002 static int handle_vmon(struct kvm_vcpu *vcpu)
5003 {
5004 struct kvm_segment cs;
5005 struct vcpu_vmx *vmx = to_vmx(vcpu);
5006
5007 /* The Intel VMX Instruction Reference lists a bunch of bits that
5008 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5009 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5010 * Otherwise, we should fail with #UD. We test these now:
5011 */
5012 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5013 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5014 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5015 kvm_queue_exception(vcpu, UD_VECTOR);
5016 return 1;
5017 }
5018
5019 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5020 if (is_long_mode(vcpu) && !cs.l) {
5021 kvm_queue_exception(vcpu, UD_VECTOR);
5022 return 1;
5023 }
5024
5025 if (vmx_get_cpl(vcpu)) {
5026 kvm_inject_gp(vcpu, 0);
5027 return 1;
5028 }
5029
5030 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5031 vmx->nested.vmcs02_num = 0;
5032
5033 vmx->nested.vmxon = true;
5034
5035 skip_emulated_instruction(vcpu);
5036 return 1;
5037 }
5038
5039 /*
5040 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5041 * for running VMX instructions (except VMXON, whose prerequisites are
5042 * slightly different). It also specifies what exception to inject otherwise.
5043 */
5044 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5045 {
5046 struct kvm_segment cs;
5047 struct vcpu_vmx *vmx = to_vmx(vcpu);
5048
5049 if (!vmx->nested.vmxon) {
5050 kvm_queue_exception(vcpu, UD_VECTOR);
5051 return 0;
5052 }
5053
5054 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5055 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5056 (is_long_mode(vcpu) && !cs.l)) {
5057 kvm_queue_exception(vcpu, UD_VECTOR);
5058 return 0;
5059 }
5060
5061 if (vmx_get_cpl(vcpu)) {
5062 kvm_inject_gp(vcpu, 0);
5063 return 0;
5064 }
5065
5066 return 1;
5067 }
5068
5069 /*
5070 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5071 * just stops using VMX.
5072 */
5073 static void free_nested(struct vcpu_vmx *vmx)
5074 {
5075 if (!vmx->nested.vmxon)
5076 return;
5077 vmx->nested.vmxon = false;
5078 if (vmx->nested.current_vmptr != -1ull) {
5079 kunmap(vmx->nested.current_vmcs12_page);
5080 nested_release_page(vmx->nested.current_vmcs12_page);
5081 vmx->nested.current_vmptr = -1ull;
5082 vmx->nested.current_vmcs12 = NULL;
5083 }
5084 /* Unpin physical memory we referred to in current vmcs02 */
5085 if (vmx->nested.apic_access_page) {
5086 nested_release_page(vmx->nested.apic_access_page);
5087 vmx->nested.apic_access_page = 0;
5088 }
5089
5090 nested_free_all_saved_vmcss(vmx);
5091 }
5092
5093 /* Emulate the VMXOFF instruction */
5094 static int handle_vmoff(struct kvm_vcpu *vcpu)
5095 {
5096 if (!nested_vmx_check_permission(vcpu))
5097 return 1;
5098 free_nested(to_vmx(vcpu));
5099 skip_emulated_instruction(vcpu);
5100 return 1;
5101 }
5102
5103 /*
5104 * Decode the memory-address operand of a vmx instruction, as recorded on an
5105 * exit caused by such an instruction (run by a guest hypervisor).
5106 * On success, returns 0. When the operand is invalid, returns 1 and throws
5107 * #UD or #GP.
5108 */
5109 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5110 unsigned long exit_qualification,
5111 u32 vmx_instruction_info, gva_t *ret)
5112 {
5113 /*
5114 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5115 * Execution", on an exit, vmx_instruction_info holds most of the
5116 * addressing components of the operand. Only the displacement part
5117 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5118 * For how an actual address is calculated from all these components,
5119 * refer to Vol. 1, "Operand Addressing".
5120 */
5121 int scaling = vmx_instruction_info & 3;
5122 int addr_size = (vmx_instruction_info >> 7) & 7;
5123 bool is_reg = vmx_instruction_info & (1u << 10);
5124 int seg_reg = (vmx_instruction_info >> 15) & 7;
5125 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5126 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5127 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5128 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5129
5130 if (is_reg) {
5131 kvm_queue_exception(vcpu, UD_VECTOR);
5132 return 1;
5133 }
5134
5135 /* Addr = segment_base + offset */
5136 /* offset = base + [index * scale] + displacement */
5137 *ret = vmx_get_segment_base(vcpu, seg_reg);
5138 if (base_is_valid)
5139 *ret += kvm_register_read(vcpu, base_reg);
5140 if (index_is_valid)
5141 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5142 *ret += exit_qualification; /* holds the displacement */
5143
5144 if (addr_size == 1) /* 32 bit */
5145 *ret &= 0xffffffff;
5146
5147 /*
5148 * TODO: throw #GP (and return 1) in various cases that the VM*
5149 * instructions require it - e.g., offset beyond segment limit,
5150 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5151 * address, and so on. Currently these are not checked.
5152 */
5153 return 0;
5154 }
5155
5156 /*
5157 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5158 * set the success or error code of an emulated VMX instruction, as specified
5159 * by Vol 2B, VMX Instruction Reference, "Conventions".
5160 */
5161 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5162 {
5163 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5164 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5165 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5166 }
5167
5168 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5169 {
5170 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5171 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5172 X86_EFLAGS_SF | X86_EFLAGS_OF))
5173 | X86_EFLAGS_CF);
5174 }
5175
5176 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5177 u32 vm_instruction_error)
5178 {
5179 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5180 /*
5181 * failValid writes the error number to the current VMCS, which
5182 * can't be done there isn't a current VMCS.
5183 */
5184 nested_vmx_failInvalid(vcpu);
5185 return;
5186 }
5187 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5188 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5189 X86_EFLAGS_SF | X86_EFLAGS_OF))
5190 | X86_EFLAGS_ZF);
5191 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5192 }
5193
5194 /* Emulate the VMCLEAR instruction */
5195 static int handle_vmclear(struct kvm_vcpu *vcpu)
5196 {
5197 struct vcpu_vmx *vmx = to_vmx(vcpu);
5198 gva_t gva;
5199 gpa_t vmptr;
5200 struct vmcs12 *vmcs12;
5201 struct page *page;
5202 struct x86_exception e;
5203
5204 if (!nested_vmx_check_permission(vcpu))
5205 return 1;
5206
5207 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5208 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5209 return 1;
5210
5211 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5212 sizeof(vmptr), &e)) {
5213 kvm_inject_page_fault(vcpu, &e);
5214 return 1;
5215 }
5216
5217 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5218 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5219 skip_emulated_instruction(vcpu);
5220 return 1;
5221 }
5222
5223 if (vmptr == vmx->nested.current_vmptr) {
5224 kunmap(vmx->nested.current_vmcs12_page);
5225 nested_release_page(vmx->nested.current_vmcs12_page);
5226 vmx->nested.current_vmptr = -1ull;
5227 vmx->nested.current_vmcs12 = NULL;
5228 }
5229
5230 page = nested_get_page(vcpu, vmptr);
5231 if (page == NULL) {
5232 /*
5233 * For accurate processor emulation, VMCLEAR beyond available
5234 * physical memory should do nothing at all. However, it is
5235 * possible that a nested vmx bug, not a guest hypervisor bug,
5236 * resulted in this case, so let's shut down before doing any
5237 * more damage:
5238 */
5239 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5240 return 1;
5241 }
5242 vmcs12 = kmap(page);
5243 vmcs12->launch_state = 0;
5244 kunmap(page);
5245 nested_release_page(page);
5246
5247 nested_free_vmcs02(vmx, vmptr);
5248
5249 skip_emulated_instruction(vcpu);
5250 nested_vmx_succeed(vcpu);
5251 return 1;
5252 }
5253
5254 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5255
5256 /* Emulate the VMLAUNCH instruction */
5257 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5258 {
5259 return nested_vmx_run(vcpu, true);
5260 }
5261
5262 /* Emulate the VMRESUME instruction */
5263 static int handle_vmresume(struct kvm_vcpu *vcpu)
5264 {
5265
5266 return nested_vmx_run(vcpu, false);
5267 }
5268
5269 enum vmcs_field_type {
5270 VMCS_FIELD_TYPE_U16 = 0,
5271 VMCS_FIELD_TYPE_U64 = 1,
5272 VMCS_FIELD_TYPE_U32 = 2,
5273 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5274 };
5275
5276 static inline int vmcs_field_type(unsigned long field)
5277 {
5278 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5279 return VMCS_FIELD_TYPE_U32;
5280 return (field >> 13) & 0x3 ;
5281 }
5282
5283 static inline int vmcs_field_readonly(unsigned long field)
5284 {
5285 return (((field >> 10) & 0x3) == 1);
5286 }
5287
5288 /*
5289 * Read a vmcs12 field. Since these can have varying lengths and we return
5290 * one type, we chose the biggest type (u64) and zero-extend the return value
5291 * to that size. Note that the caller, handle_vmread, might need to use only
5292 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5293 * 64-bit fields are to be returned).
5294 */
5295 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5296 unsigned long field, u64 *ret)
5297 {
5298 short offset = vmcs_field_to_offset(field);
5299 char *p;
5300
5301 if (offset < 0)
5302 return 0;
5303
5304 p = ((char *)(get_vmcs12(vcpu))) + offset;
5305
5306 switch (vmcs_field_type(field)) {
5307 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5308 *ret = *((natural_width *)p);
5309 return 1;
5310 case VMCS_FIELD_TYPE_U16:
5311 *ret = *((u16 *)p);
5312 return 1;
5313 case VMCS_FIELD_TYPE_U32:
5314 *ret = *((u32 *)p);
5315 return 1;
5316 case VMCS_FIELD_TYPE_U64:
5317 *ret = *((u64 *)p);
5318 return 1;
5319 default:
5320 return 0; /* can never happen. */
5321 }
5322 }
5323
5324 /*
5325 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5326 * used before) all generate the same failure when it is missing.
5327 */
5328 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5329 {
5330 struct vcpu_vmx *vmx = to_vmx(vcpu);
5331 if (vmx->nested.current_vmptr == -1ull) {
5332 nested_vmx_failInvalid(vcpu);
5333 skip_emulated_instruction(vcpu);
5334 return 0;
5335 }
5336 return 1;
5337 }
5338
5339 static int handle_vmread(struct kvm_vcpu *vcpu)
5340 {
5341 unsigned long field;
5342 u64 field_value;
5343 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5344 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5345 gva_t gva = 0;
5346
5347 if (!nested_vmx_check_permission(vcpu) ||
5348 !nested_vmx_check_vmcs12(vcpu))
5349 return 1;
5350
5351 /* Decode instruction info and find the field to read */
5352 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5353 /* Read the field, zero-extended to a u64 field_value */
5354 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5355 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5356 skip_emulated_instruction(vcpu);
5357 return 1;
5358 }
5359 /*
5360 * Now copy part of this value to register or memory, as requested.
5361 * Note that the number of bits actually copied is 32 or 64 depending
5362 * on the guest's mode (32 or 64 bit), not on the given field's length.
5363 */
5364 if (vmx_instruction_info & (1u << 10)) {
5365 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5366 field_value);
5367 } else {
5368 if (get_vmx_mem_address(vcpu, exit_qualification,
5369 vmx_instruction_info, &gva))
5370 return 1;
5371 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5372 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5373 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5374 }
5375
5376 nested_vmx_succeed(vcpu);
5377 skip_emulated_instruction(vcpu);
5378 return 1;
5379 }
5380
5381
5382 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5383 {
5384 unsigned long field;
5385 gva_t gva;
5386 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5387 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5388 char *p;
5389 short offset;
5390 /* The value to write might be 32 or 64 bits, depending on L1's long
5391 * mode, and eventually we need to write that into a field of several
5392 * possible lengths. The code below first zero-extends the value to 64
5393 * bit (field_value), and then copies only the approriate number of
5394 * bits into the vmcs12 field.
5395 */
5396 u64 field_value = 0;
5397 struct x86_exception e;
5398
5399 if (!nested_vmx_check_permission(vcpu) ||
5400 !nested_vmx_check_vmcs12(vcpu))
5401 return 1;
5402
5403 if (vmx_instruction_info & (1u << 10))
5404 field_value = kvm_register_read(vcpu,
5405 (((vmx_instruction_info) >> 3) & 0xf));
5406 else {
5407 if (get_vmx_mem_address(vcpu, exit_qualification,
5408 vmx_instruction_info, &gva))
5409 return 1;
5410 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5411 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5412 kvm_inject_page_fault(vcpu, &e);
5413 return 1;
5414 }
5415 }
5416
5417
5418 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5419 if (vmcs_field_readonly(field)) {
5420 nested_vmx_failValid(vcpu,
5421 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5422 skip_emulated_instruction(vcpu);
5423 return 1;
5424 }
5425
5426 offset = vmcs_field_to_offset(field);
5427 if (offset < 0) {
5428 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5429 skip_emulated_instruction(vcpu);
5430 return 1;
5431 }
5432 p = ((char *) get_vmcs12(vcpu)) + offset;
5433
5434 switch (vmcs_field_type(field)) {
5435 case VMCS_FIELD_TYPE_U16:
5436 *(u16 *)p = field_value;
5437 break;
5438 case VMCS_FIELD_TYPE_U32:
5439 *(u32 *)p = field_value;
5440 break;
5441 case VMCS_FIELD_TYPE_U64:
5442 *(u64 *)p = field_value;
5443 break;
5444 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5445 *(natural_width *)p = field_value;
5446 break;
5447 default:
5448 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5449 skip_emulated_instruction(vcpu);
5450 return 1;
5451 }
5452
5453 nested_vmx_succeed(vcpu);
5454 skip_emulated_instruction(vcpu);
5455 return 1;
5456 }
5457
5458 /* Emulate the VMPTRLD instruction */
5459 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5460 {
5461 struct vcpu_vmx *vmx = to_vmx(vcpu);
5462 gva_t gva;
5463 gpa_t vmptr;
5464 struct x86_exception e;
5465
5466 if (!nested_vmx_check_permission(vcpu))
5467 return 1;
5468
5469 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5470 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5471 return 1;
5472
5473 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5474 sizeof(vmptr), &e)) {
5475 kvm_inject_page_fault(vcpu, &e);
5476 return 1;
5477 }
5478
5479 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5480 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5481 skip_emulated_instruction(vcpu);
5482 return 1;
5483 }
5484
5485 if (vmx->nested.current_vmptr != vmptr) {
5486 struct vmcs12 *new_vmcs12;
5487 struct page *page;
5488 page = nested_get_page(vcpu, vmptr);
5489 if (page == NULL) {
5490 nested_vmx_failInvalid(vcpu);
5491 skip_emulated_instruction(vcpu);
5492 return 1;
5493 }
5494 new_vmcs12 = kmap(page);
5495 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5496 kunmap(page);
5497 nested_release_page_clean(page);
5498 nested_vmx_failValid(vcpu,
5499 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5500 skip_emulated_instruction(vcpu);
5501 return 1;
5502 }
5503 if (vmx->nested.current_vmptr != -1ull) {
5504 kunmap(vmx->nested.current_vmcs12_page);
5505 nested_release_page(vmx->nested.current_vmcs12_page);
5506 }
5507
5508 vmx->nested.current_vmptr = vmptr;
5509 vmx->nested.current_vmcs12 = new_vmcs12;
5510 vmx->nested.current_vmcs12_page = page;
5511 }
5512
5513 nested_vmx_succeed(vcpu);
5514 skip_emulated_instruction(vcpu);
5515 return 1;
5516 }
5517
5518 /* Emulate the VMPTRST instruction */
5519 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5520 {
5521 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5522 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5523 gva_t vmcs_gva;
5524 struct x86_exception e;
5525
5526 if (!nested_vmx_check_permission(vcpu))
5527 return 1;
5528
5529 if (get_vmx_mem_address(vcpu, exit_qualification,
5530 vmx_instruction_info, &vmcs_gva))
5531 return 1;
5532 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5533 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5534 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5535 sizeof(u64), &e)) {
5536 kvm_inject_page_fault(vcpu, &e);
5537 return 1;
5538 }
5539 nested_vmx_succeed(vcpu);
5540 skip_emulated_instruction(vcpu);
5541 return 1;
5542 }
5543
5544 /*
5545 * The exit handlers return 1 if the exit was handled fully and guest execution
5546 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5547 * to be done to userspace and return 0.
5548 */
5549 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5550 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5551 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5552 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5553 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5554 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5555 [EXIT_REASON_CR_ACCESS] = handle_cr,
5556 [EXIT_REASON_DR_ACCESS] = handle_dr,
5557 [EXIT_REASON_CPUID] = handle_cpuid,
5558 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5559 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5560 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5561 [EXIT_REASON_HLT] = handle_halt,
5562 [EXIT_REASON_INVD] = handle_invd,
5563 [EXIT_REASON_INVLPG] = handle_invlpg,
5564 [EXIT_REASON_VMCALL] = handle_vmcall,
5565 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5566 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5567 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5568 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5569 [EXIT_REASON_VMREAD] = handle_vmread,
5570 [EXIT_REASON_VMRESUME] = handle_vmresume,
5571 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5572 [EXIT_REASON_VMOFF] = handle_vmoff,
5573 [EXIT_REASON_VMON] = handle_vmon,
5574 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5575 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5576 [EXIT_REASON_WBINVD] = handle_wbinvd,
5577 [EXIT_REASON_XSETBV] = handle_xsetbv,
5578 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5579 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5580 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5581 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5582 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5583 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5584 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5585 };
5586
5587 static const int kvm_vmx_max_exit_handlers =
5588 ARRAY_SIZE(kvm_vmx_exit_handlers);
5589
5590 /*
5591 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5592 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5593 * disinterest in the current event (read or write a specific MSR) by using an
5594 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5595 */
5596 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5597 struct vmcs12 *vmcs12, u32 exit_reason)
5598 {
5599 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5600 gpa_t bitmap;
5601
5602 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5603 return 1;
5604
5605 /*
5606 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5607 * for the four combinations of read/write and low/high MSR numbers.
5608 * First we need to figure out which of the four to use:
5609 */
5610 bitmap = vmcs12->msr_bitmap;
5611 if (exit_reason == EXIT_REASON_MSR_WRITE)
5612 bitmap += 2048;
5613 if (msr_index >= 0xc0000000) {
5614 msr_index -= 0xc0000000;
5615 bitmap += 1024;
5616 }
5617
5618 /* Then read the msr_index'th bit from this bitmap: */
5619 if (msr_index < 1024*8) {
5620 unsigned char b;
5621 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5622 return 1 & (b >> (msr_index & 7));
5623 } else
5624 return 1; /* let L1 handle the wrong parameter */
5625 }
5626
5627 /*
5628 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5629 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5630 * intercept (via guest_host_mask etc.) the current event.
5631 */
5632 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5633 struct vmcs12 *vmcs12)
5634 {
5635 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5636 int cr = exit_qualification & 15;
5637 int reg = (exit_qualification >> 8) & 15;
5638 unsigned long val = kvm_register_read(vcpu, reg);
5639
5640 switch ((exit_qualification >> 4) & 3) {
5641 case 0: /* mov to cr */
5642 switch (cr) {
5643 case 0:
5644 if (vmcs12->cr0_guest_host_mask &
5645 (val ^ vmcs12->cr0_read_shadow))
5646 return 1;
5647 break;
5648 case 3:
5649 if ((vmcs12->cr3_target_count >= 1 &&
5650 vmcs12->cr3_target_value0 == val) ||
5651 (vmcs12->cr3_target_count >= 2 &&
5652 vmcs12->cr3_target_value1 == val) ||
5653 (vmcs12->cr3_target_count >= 3 &&
5654 vmcs12->cr3_target_value2 == val) ||
5655 (vmcs12->cr3_target_count >= 4 &&
5656 vmcs12->cr3_target_value3 == val))
5657 return 0;
5658 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5659 return 1;
5660 break;
5661 case 4:
5662 if (vmcs12->cr4_guest_host_mask &
5663 (vmcs12->cr4_read_shadow ^ val))
5664 return 1;
5665 break;
5666 case 8:
5667 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5668 return 1;
5669 break;
5670 }
5671 break;
5672 case 2: /* clts */
5673 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5674 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5675 return 1;
5676 break;
5677 case 1: /* mov from cr */
5678 switch (cr) {
5679 case 3:
5680 if (vmcs12->cpu_based_vm_exec_control &
5681 CPU_BASED_CR3_STORE_EXITING)
5682 return 1;
5683 break;
5684 case 8:
5685 if (vmcs12->cpu_based_vm_exec_control &
5686 CPU_BASED_CR8_STORE_EXITING)
5687 return 1;
5688 break;
5689 }
5690 break;
5691 case 3: /* lmsw */
5692 /*
5693 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5694 * cr0. Other attempted changes are ignored, with no exit.
5695 */
5696 if (vmcs12->cr0_guest_host_mask & 0xe &
5697 (val ^ vmcs12->cr0_read_shadow))
5698 return 1;
5699 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5700 !(vmcs12->cr0_read_shadow & 0x1) &&
5701 (val & 0x1))
5702 return 1;
5703 break;
5704 }
5705 return 0;
5706 }
5707
5708 /*
5709 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5710 * should handle it ourselves in L0 (and then continue L2). Only call this
5711 * when in is_guest_mode (L2).
5712 */
5713 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5714 {
5715 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5716 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5717 struct vcpu_vmx *vmx = to_vmx(vcpu);
5718 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5719
5720 if (vmx->nested.nested_run_pending)
5721 return 0;
5722
5723 if (unlikely(vmx->fail)) {
5724 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5725 vmcs_read32(VM_INSTRUCTION_ERROR));
5726 return 1;
5727 }
5728
5729 switch (exit_reason) {
5730 case EXIT_REASON_EXCEPTION_NMI:
5731 if (!is_exception(intr_info))
5732 return 0;
5733 else if (is_page_fault(intr_info))
5734 return enable_ept;
5735 return vmcs12->exception_bitmap &
5736 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5737 case EXIT_REASON_EXTERNAL_INTERRUPT:
5738 return 0;
5739 case EXIT_REASON_TRIPLE_FAULT:
5740 return 1;
5741 case EXIT_REASON_PENDING_INTERRUPT:
5742 case EXIT_REASON_NMI_WINDOW:
5743 /*
5744 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5745 * (aka Interrupt Window Exiting) only when L1 turned it on,
5746 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5747 * Same for NMI Window Exiting.
5748 */
5749 return 1;
5750 case EXIT_REASON_TASK_SWITCH:
5751 return 1;
5752 case EXIT_REASON_CPUID:
5753 return 1;
5754 case EXIT_REASON_HLT:
5755 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5756 case EXIT_REASON_INVD:
5757 return 1;
5758 case EXIT_REASON_INVLPG:
5759 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5760 case EXIT_REASON_RDPMC:
5761 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5762 case EXIT_REASON_RDTSC:
5763 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5764 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5765 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5766 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5767 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5768 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5769 /*
5770 * VMX instructions trap unconditionally. This allows L1 to
5771 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5772 */
5773 return 1;
5774 case EXIT_REASON_CR_ACCESS:
5775 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5776 case EXIT_REASON_DR_ACCESS:
5777 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5778 case EXIT_REASON_IO_INSTRUCTION:
5779 /* TODO: support IO bitmaps */
5780 return 1;
5781 case EXIT_REASON_MSR_READ:
5782 case EXIT_REASON_MSR_WRITE:
5783 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5784 case EXIT_REASON_INVALID_STATE:
5785 return 1;
5786 case EXIT_REASON_MWAIT_INSTRUCTION:
5787 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5788 case EXIT_REASON_MONITOR_INSTRUCTION:
5789 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5790 case EXIT_REASON_PAUSE_INSTRUCTION:
5791 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5792 nested_cpu_has2(vmcs12,
5793 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5794 case EXIT_REASON_MCE_DURING_VMENTRY:
5795 return 0;
5796 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5797 return 1;
5798 case EXIT_REASON_APIC_ACCESS:
5799 return nested_cpu_has2(vmcs12,
5800 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5801 case EXIT_REASON_EPT_VIOLATION:
5802 case EXIT_REASON_EPT_MISCONFIG:
5803 return 0;
5804 case EXIT_REASON_WBINVD:
5805 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5806 case EXIT_REASON_XSETBV:
5807 return 1;
5808 default:
5809 return 1;
5810 }
5811 }
5812
5813 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5814 {
5815 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5816 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5817 }
5818
5819 /*
5820 * The guest has exited. See if we can fix it or if we need userspace
5821 * assistance.
5822 */
5823 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5824 {
5825 struct vcpu_vmx *vmx = to_vmx(vcpu);
5826 u32 exit_reason = vmx->exit_reason;
5827 u32 vectoring_info = vmx->idt_vectoring_info;
5828
5829 /* If guest state is invalid, start emulating */
5830 if (vmx->emulation_required && emulate_invalid_guest_state)
5831 return handle_invalid_guest_state(vcpu);
5832
5833 /*
5834 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5835 * we did not inject a still-pending event to L1 now because of
5836 * nested_run_pending, we need to re-enable this bit.
5837 */
5838 if (vmx->nested.nested_run_pending)
5839 kvm_make_request(KVM_REQ_EVENT, vcpu);
5840
5841 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5842 exit_reason == EXIT_REASON_VMRESUME))
5843 vmx->nested.nested_run_pending = 1;
5844 else
5845 vmx->nested.nested_run_pending = 0;
5846
5847 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5848 nested_vmx_vmexit(vcpu);
5849 return 1;
5850 }
5851
5852 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5853 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5854 vcpu->run->fail_entry.hardware_entry_failure_reason
5855 = exit_reason;
5856 return 0;
5857 }
5858
5859 if (unlikely(vmx->fail)) {
5860 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5861 vcpu->run->fail_entry.hardware_entry_failure_reason
5862 = vmcs_read32(VM_INSTRUCTION_ERROR);
5863 return 0;
5864 }
5865
5866 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5867 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5868 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5869 exit_reason != EXIT_REASON_TASK_SWITCH))
5870 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5871 "(0x%x) and exit reason is 0x%x\n",
5872 __func__, vectoring_info, exit_reason);
5873
5874 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5875 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5876 get_vmcs12(vcpu), vcpu)))) {
5877 if (vmx_interrupt_allowed(vcpu)) {
5878 vmx->soft_vnmi_blocked = 0;
5879 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5880 vcpu->arch.nmi_pending) {
5881 /*
5882 * This CPU don't support us in finding the end of an
5883 * NMI-blocked window if the guest runs with IRQs
5884 * disabled. So we pull the trigger after 1 s of
5885 * futile waiting, but inform the user about this.
5886 */
5887 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5888 "state on VCPU %d after 1 s timeout\n",
5889 __func__, vcpu->vcpu_id);
5890 vmx->soft_vnmi_blocked = 0;
5891 }
5892 }
5893
5894 if (exit_reason < kvm_vmx_max_exit_handlers
5895 && kvm_vmx_exit_handlers[exit_reason])
5896 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5897 else {
5898 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5899 vcpu->run->hw.hardware_exit_reason = exit_reason;
5900 }
5901 return 0;
5902 }
5903
5904 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5905 {
5906 if (irr == -1 || tpr < irr) {
5907 vmcs_write32(TPR_THRESHOLD, 0);
5908 return;
5909 }
5910
5911 vmcs_write32(TPR_THRESHOLD, irr);
5912 }
5913
5914 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5915 {
5916 u32 exit_intr_info;
5917
5918 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5919 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5920 return;
5921
5922 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5923 exit_intr_info = vmx->exit_intr_info;
5924
5925 /* Handle machine checks before interrupts are enabled */
5926 if (is_machine_check(exit_intr_info))
5927 kvm_machine_check();
5928
5929 /* We need to handle NMIs before interrupts are enabled */
5930 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5931 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5932 kvm_before_handle_nmi(&vmx->vcpu);
5933 asm("int $2");
5934 kvm_after_handle_nmi(&vmx->vcpu);
5935 }
5936 }
5937
5938 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5939 {
5940 u32 exit_intr_info;
5941 bool unblock_nmi;
5942 u8 vector;
5943 bool idtv_info_valid;
5944
5945 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5946
5947 if (cpu_has_virtual_nmis()) {
5948 if (vmx->nmi_known_unmasked)
5949 return;
5950 /*
5951 * Can't use vmx->exit_intr_info since we're not sure what
5952 * the exit reason is.
5953 */
5954 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5955 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5956 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5957 /*
5958 * SDM 3: 27.7.1.2 (September 2008)
5959 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5960 * a guest IRET fault.
5961 * SDM 3: 23.2.2 (September 2008)
5962 * Bit 12 is undefined in any of the following cases:
5963 * If the VM exit sets the valid bit in the IDT-vectoring
5964 * information field.
5965 * If the VM exit is due to a double fault.
5966 */
5967 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5968 vector != DF_VECTOR && !idtv_info_valid)
5969 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5970 GUEST_INTR_STATE_NMI);
5971 else
5972 vmx->nmi_known_unmasked =
5973 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5974 & GUEST_INTR_STATE_NMI);
5975 } else if (unlikely(vmx->soft_vnmi_blocked))
5976 vmx->vnmi_blocked_time +=
5977 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5978 }
5979
5980 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5981 u32 idt_vectoring_info,
5982 int instr_len_field,
5983 int error_code_field)
5984 {
5985 u8 vector;
5986 int type;
5987 bool idtv_info_valid;
5988
5989 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5990
5991 vmx->vcpu.arch.nmi_injected = false;
5992 kvm_clear_exception_queue(&vmx->vcpu);
5993 kvm_clear_interrupt_queue(&vmx->vcpu);
5994
5995 if (!idtv_info_valid)
5996 return;
5997
5998 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5999
6000 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6001 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6002
6003 switch (type) {
6004 case INTR_TYPE_NMI_INTR:
6005 vmx->vcpu.arch.nmi_injected = true;
6006 /*
6007 * SDM 3: 27.7.1.2 (September 2008)
6008 * Clear bit "block by NMI" before VM entry if a NMI
6009 * delivery faulted.
6010 */
6011 vmx_set_nmi_mask(&vmx->vcpu, false);
6012 break;
6013 case INTR_TYPE_SOFT_EXCEPTION:
6014 vmx->vcpu.arch.event_exit_inst_len =
6015 vmcs_read32(instr_len_field);
6016 /* fall through */
6017 case INTR_TYPE_HARD_EXCEPTION:
6018 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6019 u32 err = vmcs_read32(error_code_field);
6020 kvm_queue_exception_e(&vmx->vcpu, vector, err);
6021 } else
6022 kvm_queue_exception(&vmx->vcpu, vector);
6023 break;
6024 case INTR_TYPE_SOFT_INTR:
6025 vmx->vcpu.arch.event_exit_inst_len =
6026 vmcs_read32(instr_len_field);
6027 /* fall through */
6028 case INTR_TYPE_EXT_INTR:
6029 kvm_queue_interrupt(&vmx->vcpu, vector,
6030 type == INTR_TYPE_SOFT_INTR);
6031 break;
6032 default:
6033 break;
6034 }
6035 }
6036
6037 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6038 {
6039 if (is_guest_mode(&vmx->vcpu))
6040 return;
6041 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6042 VM_EXIT_INSTRUCTION_LEN,
6043 IDT_VECTORING_ERROR_CODE);
6044 }
6045
6046 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6047 {
6048 if (is_guest_mode(vcpu))
6049 return;
6050 __vmx_complete_interrupts(to_vmx(vcpu),
6051 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6052 VM_ENTRY_INSTRUCTION_LEN,
6053 VM_ENTRY_EXCEPTION_ERROR_CODE);
6054
6055 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6056 }
6057
6058 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6059 {
6060 int i, nr_msrs;
6061 struct perf_guest_switch_msr *msrs;
6062
6063 msrs = perf_guest_get_msrs(&nr_msrs);
6064
6065 if (!msrs)
6066 return;
6067
6068 for (i = 0; i < nr_msrs; i++)
6069 if (msrs[i].host == msrs[i].guest)
6070 clear_atomic_switch_msr(vmx, msrs[i].msr);
6071 else
6072 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6073 msrs[i].host);
6074 }
6075
6076 #ifdef CONFIG_X86_64
6077 #define R "r"
6078 #define Q "q"
6079 #else
6080 #define R "e"
6081 #define Q "l"
6082 #endif
6083
6084 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6085 {
6086 struct vcpu_vmx *vmx = to_vmx(vcpu);
6087
6088 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6089 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6090 if (vmcs12->idt_vectoring_info_field &
6091 VECTORING_INFO_VALID_MASK) {
6092 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6093 vmcs12->idt_vectoring_info_field);
6094 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6095 vmcs12->vm_exit_instruction_len);
6096 if (vmcs12->idt_vectoring_info_field &
6097 VECTORING_INFO_DELIVER_CODE_MASK)
6098 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6099 vmcs12->idt_vectoring_error_code);
6100 }
6101 }
6102
6103 /* Record the guest's net vcpu time for enforced NMI injections. */
6104 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6105 vmx->entry_time = ktime_get();
6106
6107 /* Don't enter VMX if guest state is invalid, let the exit handler
6108 start emulation until we arrive back to a valid state */
6109 if (vmx->emulation_required && emulate_invalid_guest_state)
6110 return;
6111
6112 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6113 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6114 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6115 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6116
6117 /* When single-stepping over STI and MOV SS, we must clear the
6118 * corresponding interruptibility bits in the guest state. Otherwise
6119 * vmentry fails as it then expects bit 14 (BS) in pending debug
6120 * exceptions being set, but that's not correct for the guest debugging
6121 * case. */
6122 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6123 vmx_set_interrupt_shadow(vcpu, 0);
6124
6125 atomic_switch_perf_msrs(vmx);
6126
6127 vmx->__launched = vmx->loaded_vmcs->launched;
6128 asm(
6129 /* Store host registers */
6130 "push %%"R"dx; push %%"R"bp;"
6131 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6132 "push %%"R"cx \n\t"
6133 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6134 "je 1f \n\t"
6135 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6136 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6137 "1: \n\t"
6138 /* Reload cr2 if changed */
6139 "mov %c[cr2](%0), %%"R"ax \n\t"
6140 "mov %%cr2, %%"R"dx \n\t"
6141 "cmp %%"R"ax, %%"R"dx \n\t"
6142 "je 2f \n\t"
6143 "mov %%"R"ax, %%cr2 \n\t"
6144 "2: \n\t"
6145 /* Check if vmlaunch of vmresume is needed */
6146 "cmpl $0, %c[launched](%0) \n\t"
6147 /* Load guest registers. Don't clobber flags. */
6148 "mov %c[rax](%0), %%"R"ax \n\t"
6149 "mov %c[rbx](%0), %%"R"bx \n\t"
6150 "mov %c[rdx](%0), %%"R"dx \n\t"
6151 "mov %c[rsi](%0), %%"R"si \n\t"
6152 "mov %c[rdi](%0), %%"R"di \n\t"
6153 "mov %c[rbp](%0), %%"R"bp \n\t"
6154 #ifdef CONFIG_X86_64
6155 "mov %c[r8](%0), %%r8 \n\t"
6156 "mov %c[r9](%0), %%r9 \n\t"
6157 "mov %c[r10](%0), %%r10 \n\t"
6158 "mov %c[r11](%0), %%r11 \n\t"
6159 "mov %c[r12](%0), %%r12 \n\t"
6160 "mov %c[r13](%0), %%r13 \n\t"
6161 "mov %c[r14](%0), %%r14 \n\t"
6162 "mov %c[r15](%0), %%r15 \n\t"
6163 #endif
6164 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6165
6166 /* Enter guest mode */
6167 "jne .Llaunched \n\t"
6168 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6169 "jmp .Lkvm_vmx_return \n\t"
6170 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6171 ".Lkvm_vmx_return: "
6172 /* Save guest registers, load host registers, keep flags */
6173 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6174 "pop %0 \n\t"
6175 "mov %%"R"ax, %c[rax](%0) \n\t"
6176 "mov %%"R"bx, %c[rbx](%0) \n\t"
6177 "pop"Q" %c[rcx](%0) \n\t"
6178 "mov %%"R"dx, %c[rdx](%0) \n\t"
6179 "mov %%"R"si, %c[rsi](%0) \n\t"
6180 "mov %%"R"di, %c[rdi](%0) \n\t"
6181 "mov %%"R"bp, %c[rbp](%0) \n\t"
6182 #ifdef CONFIG_X86_64
6183 "mov %%r8, %c[r8](%0) \n\t"
6184 "mov %%r9, %c[r9](%0) \n\t"
6185 "mov %%r10, %c[r10](%0) \n\t"
6186 "mov %%r11, %c[r11](%0) \n\t"
6187 "mov %%r12, %c[r12](%0) \n\t"
6188 "mov %%r13, %c[r13](%0) \n\t"
6189 "mov %%r14, %c[r14](%0) \n\t"
6190 "mov %%r15, %c[r15](%0) \n\t"
6191 #endif
6192 "mov %%cr2, %%"R"ax \n\t"
6193 "mov %%"R"ax, %c[cr2](%0) \n\t"
6194
6195 "pop %%"R"bp; pop %%"R"dx \n\t"
6196 "setbe %c[fail](%0) \n\t"
6197 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6198 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6199 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6200 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6201 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6202 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6203 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6204 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6205 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6206 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6207 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6208 #ifdef CONFIG_X86_64
6209 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6210 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6211 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6212 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6213 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6214 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6215 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6216 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6217 #endif
6218 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6219 [wordsize]"i"(sizeof(ulong))
6220 : "cc", "memory"
6221 , R"ax", R"bx", R"di", R"si"
6222 #ifdef CONFIG_X86_64
6223 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6224 #endif
6225 );
6226
6227 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6228 | (1 << VCPU_EXREG_RFLAGS)
6229 | (1 << VCPU_EXREG_CPL)
6230 | (1 << VCPU_EXREG_PDPTR)
6231 | (1 << VCPU_EXREG_SEGMENTS)
6232 | (1 << VCPU_EXREG_CR3));
6233 vcpu->arch.regs_dirty = 0;
6234
6235 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6236
6237 if (is_guest_mode(vcpu)) {
6238 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6239 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6240 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6241 vmcs12->idt_vectoring_error_code =
6242 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6243 vmcs12->vm_exit_instruction_len =
6244 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6245 }
6246 }
6247
6248 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6249 vmx->loaded_vmcs->launched = 1;
6250
6251 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6252 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6253
6254 vmx_complete_atomic_exit(vmx);
6255 vmx_recover_nmi_blocking(vmx);
6256 vmx_complete_interrupts(vmx);
6257 }
6258
6259 #undef R
6260 #undef Q
6261
6262 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6263 {
6264 struct vcpu_vmx *vmx = to_vmx(vcpu);
6265
6266 free_vpid(vmx);
6267 free_nested(vmx);
6268 free_loaded_vmcs(vmx->loaded_vmcs);
6269 kfree(vmx->guest_msrs);
6270 kvm_vcpu_uninit(vcpu);
6271 kmem_cache_free(kvm_vcpu_cache, vmx);
6272 }
6273
6274 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6275 {
6276 int err;
6277 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6278 int cpu;
6279
6280 if (!vmx)
6281 return ERR_PTR(-ENOMEM);
6282
6283 allocate_vpid(vmx);
6284
6285 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6286 if (err)
6287 goto free_vcpu;
6288
6289 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6290 err = -ENOMEM;
6291 if (!vmx->guest_msrs) {
6292 goto uninit_vcpu;
6293 }
6294
6295 vmx->loaded_vmcs = &vmx->vmcs01;
6296 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6297 if (!vmx->loaded_vmcs->vmcs)
6298 goto free_msrs;
6299 if (!vmm_exclusive)
6300 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6301 loaded_vmcs_init(vmx->loaded_vmcs);
6302 if (!vmm_exclusive)
6303 kvm_cpu_vmxoff();
6304
6305 cpu = get_cpu();
6306 vmx_vcpu_load(&vmx->vcpu, cpu);
6307 vmx->vcpu.cpu = cpu;
6308 err = vmx_vcpu_setup(vmx);
6309 vmx_vcpu_put(&vmx->vcpu);
6310 put_cpu();
6311 if (err)
6312 goto free_vmcs;
6313 if (vm_need_virtualize_apic_accesses(kvm))
6314 err = alloc_apic_access_page(kvm);
6315 if (err)
6316 goto free_vmcs;
6317
6318 if (enable_ept) {
6319 if (!kvm->arch.ept_identity_map_addr)
6320 kvm->arch.ept_identity_map_addr =
6321 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6322 err = -ENOMEM;
6323 if (alloc_identity_pagetable(kvm) != 0)
6324 goto free_vmcs;
6325 if (!init_rmode_identity_map(kvm))
6326 goto free_vmcs;
6327 }
6328
6329 vmx->nested.current_vmptr = -1ull;
6330 vmx->nested.current_vmcs12 = NULL;
6331
6332 return &vmx->vcpu;
6333
6334 free_vmcs:
6335 free_vmcs(vmx->loaded_vmcs->vmcs);
6336 free_msrs:
6337 kfree(vmx->guest_msrs);
6338 uninit_vcpu:
6339 kvm_vcpu_uninit(&vmx->vcpu);
6340 free_vcpu:
6341 free_vpid(vmx);
6342 kmem_cache_free(kvm_vcpu_cache, vmx);
6343 return ERR_PTR(err);
6344 }
6345
6346 static void __init vmx_check_processor_compat(void *rtn)
6347 {
6348 struct vmcs_config vmcs_conf;
6349
6350 *(int *)rtn = 0;
6351 if (setup_vmcs_config(&vmcs_conf) < 0)
6352 *(int *)rtn = -EIO;
6353 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6354 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6355 smp_processor_id());
6356 *(int *)rtn = -EIO;
6357 }
6358 }
6359
6360 static int get_ept_level(void)
6361 {
6362 return VMX_EPT_DEFAULT_GAW + 1;
6363 }
6364
6365 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6366 {
6367 u64 ret;
6368
6369 /* For VT-d and EPT combination
6370 * 1. MMIO: always map as UC
6371 * 2. EPT with VT-d:
6372 * a. VT-d without snooping control feature: can't guarantee the
6373 * result, try to trust guest.
6374 * b. VT-d with snooping control feature: snooping control feature of
6375 * VT-d engine can guarantee the cache correctness. Just set it
6376 * to WB to keep consistent with host. So the same as item 3.
6377 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6378 * consistent with host MTRR
6379 */
6380 if (is_mmio)
6381 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6382 else if (vcpu->kvm->arch.iommu_domain &&
6383 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6384 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6385 VMX_EPT_MT_EPTE_SHIFT;
6386 else
6387 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6388 | VMX_EPT_IPAT_BIT;
6389
6390 return ret;
6391 }
6392
6393 static int vmx_get_lpage_level(void)
6394 {
6395 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6396 return PT_DIRECTORY_LEVEL;
6397 else
6398 /* For shadow and EPT supported 1GB page */
6399 return PT_PDPE_LEVEL;
6400 }
6401
6402 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6403 {
6404 struct kvm_cpuid_entry2 *best;
6405 struct vcpu_vmx *vmx = to_vmx(vcpu);
6406 u32 exec_control;
6407
6408 vmx->rdtscp_enabled = false;
6409 if (vmx_rdtscp_supported()) {
6410 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6411 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6412 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6413 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6414 vmx->rdtscp_enabled = true;
6415 else {
6416 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6417 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6418 exec_control);
6419 }
6420 }
6421 }
6422 }
6423
6424 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6425 {
6426 if (func == 1 && nested)
6427 entry->ecx |= bit(X86_FEATURE_VMX);
6428 }
6429
6430 /*
6431 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6432 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6433 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6434 * guest in a way that will both be appropriate to L1's requests, and our
6435 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6436 * function also has additional necessary side-effects, like setting various
6437 * vcpu->arch fields.
6438 */
6439 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6440 {
6441 struct vcpu_vmx *vmx = to_vmx(vcpu);
6442 u32 exec_control;
6443
6444 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6445 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6446 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6447 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6448 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6449 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6450 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6451 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6452 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6453 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6454 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6455 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6456 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6457 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6458 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6459 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6460 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6461 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6462 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6463 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6464 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6465 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6466 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6467 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6468 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6469 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6470 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6471 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6472 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6473 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6474 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6475 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6476 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6477 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6478 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6479 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6480
6481 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6482 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6483 vmcs12->vm_entry_intr_info_field);
6484 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6485 vmcs12->vm_entry_exception_error_code);
6486 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6487 vmcs12->vm_entry_instruction_len);
6488 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6489 vmcs12->guest_interruptibility_info);
6490 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6491 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6492 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6493 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6494 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6495 vmcs12->guest_pending_dbg_exceptions);
6496 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6497 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6498
6499 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6500
6501 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6502 (vmcs_config.pin_based_exec_ctrl |
6503 vmcs12->pin_based_vm_exec_control));
6504
6505 /*
6506 * Whether page-faults are trapped is determined by a combination of
6507 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6508 * If enable_ept, L0 doesn't care about page faults and we should
6509 * set all of these to L1's desires. However, if !enable_ept, L0 does
6510 * care about (at least some) page faults, and because it is not easy
6511 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6512 * to exit on each and every L2 page fault. This is done by setting
6513 * MASK=MATCH=0 and (see below) EB.PF=1.
6514 * Note that below we don't need special code to set EB.PF beyond the
6515 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6516 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6517 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6518 *
6519 * A problem with this approach (when !enable_ept) is that L1 may be
6520 * injected with more page faults than it asked for. This could have
6521 * caused problems, but in practice existing hypervisors don't care.
6522 * To fix this, we will need to emulate the PFEC checking (on the L1
6523 * page tables), using walk_addr(), when injecting PFs to L1.
6524 */
6525 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6526 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6527 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6528 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6529
6530 if (cpu_has_secondary_exec_ctrls()) {
6531 u32 exec_control = vmx_secondary_exec_control(vmx);
6532 if (!vmx->rdtscp_enabled)
6533 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6534 /* Take the following fields only from vmcs12 */
6535 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6536 if (nested_cpu_has(vmcs12,
6537 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6538 exec_control |= vmcs12->secondary_vm_exec_control;
6539
6540 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6541 /*
6542 * Translate L1 physical address to host physical
6543 * address for vmcs02. Keep the page pinned, so this
6544 * physical address remains valid. We keep a reference
6545 * to it so we can release it later.
6546 */
6547 if (vmx->nested.apic_access_page) /* shouldn't happen */
6548 nested_release_page(vmx->nested.apic_access_page);
6549 vmx->nested.apic_access_page =
6550 nested_get_page(vcpu, vmcs12->apic_access_addr);
6551 /*
6552 * If translation failed, no matter: This feature asks
6553 * to exit when accessing the given address, and if it
6554 * can never be accessed, this feature won't do
6555 * anything anyway.
6556 */
6557 if (!vmx->nested.apic_access_page)
6558 exec_control &=
6559 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6560 else
6561 vmcs_write64(APIC_ACCESS_ADDR,
6562 page_to_phys(vmx->nested.apic_access_page));
6563 }
6564
6565 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6566 }
6567
6568
6569 /*
6570 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6571 * Some constant fields are set here by vmx_set_constant_host_state().
6572 * Other fields are different per CPU, and will be set later when
6573 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6574 */
6575 vmx_set_constant_host_state();
6576
6577 /*
6578 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6579 * entry, but only if the current (host) sp changed from the value
6580 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6581 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6582 * here we just force the write to happen on entry.
6583 */
6584 vmx->host_rsp = 0;
6585
6586 exec_control = vmx_exec_control(vmx); /* L0's desires */
6587 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6588 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6589 exec_control &= ~CPU_BASED_TPR_SHADOW;
6590 exec_control |= vmcs12->cpu_based_vm_exec_control;
6591 /*
6592 * Merging of IO and MSR bitmaps not currently supported.
6593 * Rather, exit every time.
6594 */
6595 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6596 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6597 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6598
6599 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6600
6601 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6602 * bitwise-or of what L1 wants to trap for L2, and what we want to
6603 * trap. Note that CR0.TS also needs updating - we do this later.
6604 */
6605 update_exception_bitmap(vcpu);
6606 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6607 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6608
6609 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6610 vmcs_write32(VM_EXIT_CONTROLS,
6611 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6612 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6613 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6614
6615 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6616 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6617 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6618 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6619
6620
6621 set_cr4_guest_host_mask(vmx);
6622
6623 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6624 vmcs_write64(TSC_OFFSET,
6625 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6626 else
6627 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6628
6629 if (enable_vpid) {
6630 /*
6631 * Trivially support vpid by letting L2s share their parent
6632 * L1's vpid. TODO: move to a more elaborate solution, giving
6633 * each L2 its own vpid and exposing the vpid feature to L1.
6634 */
6635 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6636 vmx_flush_tlb(vcpu);
6637 }
6638
6639 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6640 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6641 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6642 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6643 else
6644 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6645 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6646 vmx_set_efer(vcpu, vcpu->arch.efer);
6647
6648 /*
6649 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6650 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6651 * The CR0_READ_SHADOW is what L2 should have expected to read given
6652 * the specifications by L1; It's not enough to take
6653 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6654 * have more bits than L1 expected.
6655 */
6656 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6657 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6658
6659 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6660 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6661
6662 /* shadow page tables on either EPT or shadow page tables */
6663 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6664 kvm_mmu_reset_context(vcpu);
6665
6666 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6667 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6668 }
6669
6670 /*
6671 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6672 * for running an L2 nested guest.
6673 */
6674 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6675 {
6676 struct vmcs12 *vmcs12;
6677 struct vcpu_vmx *vmx = to_vmx(vcpu);
6678 int cpu;
6679 struct loaded_vmcs *vmcs02;
6680
6681 if (!nested_vmx_check_permission(vcpu) ||
6682 !nested_vmx_check_vmcs12(vcpu))
6683 return 1;
6684
6685 skip_emulated_instruction(vcpu);
6686 vmcs12 = get_vmcs12(vcpu);
6687
6688 /*
6689 * The nested entry process starts with enforcing various prerequisites
6690 * on vmcs12 as required by the Intel SDM, and act appropriately when
6691 * they fail: As the SDM explains, some conditions should cause the
6692 * instruction to fail, while others will cause the instruction to seem
6693 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6694 * To speed up the normal (success) code path, we should avoid checking
6695 * for misconfigurations which will anyway be caught by the processor
6696 * when using the merged vmcs02.
6697 */
6698 if (vmcs12->launch_state == launch) {
6699 nested_vmx_failValid(vcpu,
6700 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6701 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6702 return 1;
6703 }
6704
6705 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6706 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6707 /*TODO: Also verify bits beyond physical address width are 0*/
6708 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6709 return 1;
6710 }
6711
6712 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6713 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6714 /*TODO: Also verify bits beyond physical address width are 0*/
6715 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6716 return 1;
6717 }
6718
6719 if (vmcs12->vm_entry_msr_load_count > 0 ||
6720 vmcs12->vm_exit_msr_load_count > 0 ||
6721 vmcs12->vm_exit_msr_store_count > 0) {
6722 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6723 __func__);
6724 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6725 return 1;
6726 }
6727
6728 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6729 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6730 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6731 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6732 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6733 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6734 !vmx_control_verify(vmcs12->vm_exit_controls,
6735 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6736 !vmx_control_verify(vmcs12->vm_entry_controls,
6737 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6738 {
6739 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6740 return 1;
6741 }
6742
6743 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6744 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6745 nested_vmx_failValid(vcpu,
6746 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6747 return 1;
6748 }
6749
6750 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6751 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6752 nested_vmx_entry_failure(vcpu, vmcs12,
6753 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6754 return 1;
6755 }
6756 if (vmcs12->vmcs_link_pointer != -1ull) {
6757 nested_vmx_entry_failure(vcpu, vmcs12,
6758 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6759 return 1;
6760 }
6761
6762 /*
6763 * We're finally done with prerequisite checking, and can start with
6764 * the nested entry.
6765 */
6766
6767 vmcs02 = nested_get_current_vmcs02(vmx);
6768 if (!vmcs02)
6769 return -ENOMEM;
6770
6771 enter_guest_mode(vcpu);
6772
6773 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6774
6775 cpu = get_cpu();
6776 vmx->loaded_vmcs = vmcs02;
6777 vmx_vcpu_put(vcpu);
6778 vmx_vcpu_load(vcpu, cpu);
6779 vcpu->cpu = cpu;
6780 put_cpu();
6781
6782 vmcs12->launch_state = 1;
6783
6784 prepare_vmcs02(vcpu, vmcs12);
6785
6786 /*
6787 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6788 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6789 * returned as far as L1 is concerned. It will only return (and set
6790 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6791 */
6792 return 1;
6793 }
6794
6795 /*
6796 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6797 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6798 * This function returns the new value we should put in vmcs12.guest_cr0.
6799 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6800 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6801 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6802 * didn't trap the bit, because if L1 did, so would L0).
6803 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6804 * been modified by L2, and L1 knows it. So just leave the old value of
6805 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6806 * isn't relevant, because if L0 traps this bit it can set it to anything.
6807 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6808 * changed these bits, and therefore they need to be updated, but L0
6809 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6810 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6811 */
6812 static inline unsigned long
6813 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6814 {
6815 return
6816 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6817 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6818 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6819 vcpu->arch.cr0_guest_owned_bits));
6820 }
6821
6822 static inline unsigned long
6823 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6824 {
6825 return
6826 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6827 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6828 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6829 vcpu->arch.cr4_guest_owned_bits));
6830 }
6831
6832 /*
6833 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6834 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6835 * and this function updates it to reflect the changes to the guest state while
6836 * L2 was running (and perhaps made some exits which were handled directly by L0
6837 * without going back to L1), and to reflect the exit reason.
6838 * Note that we do not have to copy here all VMCS fields, just those that
6839 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6840 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6841 * which already writes to vmcs12 directly.
6842 */
6843 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6844 {
6845 /* update guest state fields: */
6846 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6847 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6848
6849 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6850 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6851 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6852 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6853
6854 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6855 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6856 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6857 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6858 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6859 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6860 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6861 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6862 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6863 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6864 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6865 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6866 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6867 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6868 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6869 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6870 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6871 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6872 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6873 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6874 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6875 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6876 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6877 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6878 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6879 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6880 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6881 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6882 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6883 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6884 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6885 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6886 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6887 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6888 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6889 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6890
6891 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6892 vmcs12->guest_interruptibility_info =
6893 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6894 vmcs12->guest_pending_dbg_exceptions =
6895 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6896
6897 /* TODO: These cannot have changed unless we have MSR bitmaps and
6898 * the relevant bit asks not to trap the change */
6899 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6900 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6901 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6902 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6903 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6904 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6905
6906 /* update exit information fields: */
6907
6908 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6909 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6910
6911 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6912 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6913 vmcs12->idt_vectoring_info_field =
6914 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6915 vmcs12->idt_vectoring_error_code =
6916 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6917 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6918 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6919
6920 /* clear vm-entry fields which are to be cleared on exit */
6921 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6922 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6923 }
6924
6925 /*
6926 * A part of what we need to when the nested L2 guest exits and we want to
6927 * run its L1 parent, is to reset L1's guest state to the host state specified
6928 * in vmcs12.
6929 * This function is to be called not only on normal nested exit, but also on
6930 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6931 * Failures During or After Loading Guest State").
6932 * This function should be called when the active VMCS is L1's (vmcs01).
6933 */
6934 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6935 {
6936 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6937 vcpu->arch.efer = vmcs12->host_ia32_efer;
6938 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6939 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6940 else
6941 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6942 vmx_set_efer(vcpu, vcpu->arch.efer);
6943
6944 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6945 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6946 /*
6947 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6948 * actually changed, because it depends on the current state of
6949 * fpu_active (which may have changed).
6950 * Note that vmx_set_cr0 refers to efer set above.
6951 */
6952 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6953 /*
6954 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6955 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6956 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6957 */
6958 update_exception_bitmap(vcpu);
6959 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6960 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6961
6962 /*
6963 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6964 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6965 */
6966 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6967 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6968
6969 /* shadow page tables on either EPT or shadow page tables */
6970 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6971 kvm_mmu_reset_context(vcpu);
6972
6973 if (enable_vpid) {
6974 /*
6975 * Trivially support vpid by letting L2s share their parent
6976 * L1's vpid. TODO: move to a more elaborate solution, giving
6977 * each L2 its own vpid and exposing the vpid feature to L1.
6978 */
6979 vmx_flush_tlb(vcpu);
6980 }
6981
6982
6983 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6984 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6985 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6986 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6987 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6988 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6989 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6990 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6991 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6992 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6993 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6994 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6995 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6996 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6997 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6998
6999 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7000 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7001 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7002 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7003 vmcs12->host_ia32_perf_global_ctrl);
7004 }
7005
7006 /*
7007 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7008 * and modify vmcs12 to make it see what it would expect to see there if
7009 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7010 */
7011 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7012 {
7013 struct vcpu_vmx *vmx = to_vmx(vcpu);
7014 int cpu;
7015 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7016
7017 leave_guest_mode(vcpu);
7018 prepare_vmcs12(vcpu, vmcs12);
7019
7020 cpu = get_cpu();
7021 vmx->loaded_vmcs = &vmx->vmcs01;
7022 vmx_vcpu_put(vcpu);
7023 vmx_vcpu_load(vcpu, cpu);
7024 vcpu->cpu = cpu;
7025 put_cpu();
7026
7027 /* if no vmcs02 cache requested, remove the one we used */
7028 if (VMCS02_POOL_SIZE == 0)
7029 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7030
7031 load_vmcs12_host_state(vcpu, vmcs12);
7032
7033 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7034 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7035
7036 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7037 vmx->host_rsp = 0;
7038
7039 /* Unpin physical memory we referred to in vmcs02 */
7040 if (vmx->nested.apic_access_page) {
7041 nested_release_page(vmx->nested.apic_access_page);
7042 vmx->nested.apic_access_page = 0;
7043 }
7044
7045 /*
7046 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7047 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7048 * success or failure flag accordingly.
7049 */
7050 if (unlikely(vmx->fail)) {
7051 vmx->fail = 0;
7052 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7053 } else
7054 nested_vmx_succeed(vcpu);
7055 }
7056
7057 /*
7058 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7059 * 23.7 "VM-entry failures during or after loading guest state" (this also
7060 * lists the acceptable exit-reason and exit-qualification parameters).
7061 * It should only be called before L2 actually succeeded to run, and when
7062 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7063 */
7064 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7065 struct vmcs12 *vmcs12,
7066 u32 reason, unsigned long qualification)
7067 {
7068 load_vmcs12_host_state(vcpu, vmcs12);
7069 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7070 vmcs12->exit_qualification = qualification;
7071 nested_vmx_succeed(vcpu);
7072 }
7073
7074 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7075 struct x86_instruction_info *info,
7076 enum x86_intercept_stage stage)
7077 {
7078 return X86EMUL_CONTINUE;
7079 }
7080
7081 static struct kvm_x86_ops vmx_x86_ops = {
7082 .cpu_has_kvm_support = cpu_has_kvm_support,
7083 .disabled_by_bios = vmx_disabled_by_bios,
7084 .hardware_setup = hardware_setup,
7085 .hardware_unsetup = hardware_unsetup,
7086 .check_processor_compatibility = vmx_check_processor_compat,
7087 .hardware_enable = hardware_enable,
7088 .hardware_disable = hardware_disable,
7089 .cpu_has_accelerated_tpr = report_flexpriority,
7090
7091 .vcpu_create = vmx_create_vcpu,
7092 .vcpu_free = vmx_free_vcpu,
7093 .vcpu_reset = vmx_vcpu_reset,
7094
7095 .prepare_guest_switch = vmx_save_host_state,
7096 .vcpu_load = vmx_vcpu_load,
7097 .vcpu_put = vmx_vcpu_put,
7098
7099 .set_guest_debug = set_guest_debug,
7100 .get_msr = vmx_get_msr,
7101 .set_msr = vmx_set_msr,
7102 .get_segment_base = vmx_get_segment_base,
7103 .get_segment = vmx_get_segment,
7104 .set_segment = vmx_set_segment,
7105 .get_cpl = vmx_get_cpl,
7106 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7107 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7108 .decache_cr3 = vmx_decache_cr3,
7109 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7110 .set_cr0 = vmx_set_cr0,
7111 .set_cr3 = vmx_set_cr3,
7112 .set_cr4 = vmx_set_cr4,
7113 .set_efer = vmx_set_efer,
7114 .get_idt = vmx_get_idt,
7115 .set_idt = vmx_set_idt,
7116 .get_gdt = vmx_get_gdt,
7117 .set_gdt = vmx_set_gdt,
7118 .set_dr7 = vmx_set_dr7,
7119 .cache_reg = vmx_cache_reg,
7120 .get_rflags = vmx_get_rflags,
7121 .set_rflags = vmx_set_rflags,
7122 .fpu_activate = vmx_fpu_activate,
7123 .fpu_deactivate = vmx_fpu_deactivate,
7124
7125 .tlb_flush = vmx_flush_tlb,
7126
7127 .run = vmx_vcpu_run,
7128 .handle_exit = vmx_handle_exit,
7129 .skip_emulated_instruction = skip_emulated_instruction,
7130 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7131 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7132 .patch_hypercall = vmx_patch_hypercall,
7133 .set_irq = vmx_inject_irq,
7134 .set_nmi = vmx_inject_nmi,
7135 .queue_exception = vmx_queue_exception,
7136 .cancel_injection = vmx_cancel_injection,
7137 .interrupt_allowed = vmx_interrupt_allowed,
7138 .nmi_allowed = vmx_nmi_allowed,
7139 .get_nmi_mask = vmx_get_nmi_mask,
7140 .set_nmi_mask = vmx_set_nmi_mask,
7141 .enable_nmi_window = enable_nmi_window,
7142 .enable_irq_window = enable_irq_window,
7143 .update_cr8_intercept = update_cr8_intercept,
7144
7145 .set_tss_addr = vmx_set_tss_addr,
7146 .get_tdp_level = get_ept_level,
7147 .get_mt_mask = vmx_get_mt_mask,
7148
7149 .get_exit_info = vmx_get_exit_info,
7150
7151 .get_lpage_level = vmx_get_lpage_level,
7152
7153 .cpuid_update = vmx_cpuid_update,
7154
7155 .rdtscp_supported = vmx_rdtscp_supported,
7156
7157 .set_supported_cpuid = vmx_set_supported_cpuid,
7158
7159 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7160
7161 .set_tsc_khz = vmx_set_tsc_khz,
7162 .write_tsc_offset = vmx_write_tsc_offset,
7163 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7164 .compute_tsc_offset = vmx_compute_tsc_offset,
7165 .read_l1_tsc = vmx_read_l1_tsc,
7166
7167 .set_tdp_cr3 = vmx_set_cr3,
7168
7169 .check_intercept = vmx_check_intercept,
7170 };
7171
7172 static int __init vmx_init(void)
7173 {
7174 int r, i;
7175
7176 rdmsrl_safe(MSR_EFER, &host_efer);
7177
7178 for (i = 0; i < NR_VMX_MSR; ++i)
7179 kvm_define_shared_msr(i, vmx_msr_index[i]);
7180
7181 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7182 if (!vmx_io_bitmap_a)
7183 return -ENOMEM;
7184
7185 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7186 if (!vmx_io_bitmap_b) {
7187 r = -ENOMEM;
7188 goto out;
7189 }
7190
7191 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7192 if (!vmx_msr_bitmap_legacy) {
7193 r = -ENOMEM;
7194 goto out1;
7195 }
7196
7197 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7198 if (!vmx_msr_bitmap_longmode) {
7199 r = -ENOMEM;
7200 goto out2;
7201 }
7202
7203 /*
7204 * Allow direct access to the PC debug port (it is often used for I/O
7205 * delays, but the vmexits simply slow things down).
7206 */
7207 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7208 clear_bit(0x80, vmx_io_bitmap_a);
7209
7210 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7211
7212 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7213 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7214
7215 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7216
7217 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7218 __alignof__(struct vcpu_vmx), THIS_MODULE);
7219 if (r)
7220 goto out3;
7221
7222 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7223 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7224 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7225 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7226 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7227 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7228
7229 if (enable_ept) {
7230 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7231 VMX_EPT_EXECUTABLE_MASK);
7232 ept_set_mmio_spte_mask();
7233 kvm_enable_tdp();
7234 } else
7235 kvm_disable_tdp();
7236
7237 return 0;
7238
7239 out3:
7240 free_page((unsigned long)vmx_msr_bitmap_longmode);
7241 out2:
7242 free_page((unsigned long)vmx_msr_bitmap_legacy);
7243 out1:
7244 free_page((unsigned long)vmx_io_bitmap_b);
7245 out:
7246 free_page((unsigned long)vmx_io_bitmap_a);
7247 return r;
7248 }
7249
7250 static void __exit vmx_exit(void)
7251 {
7252 free_page((unsigned long)vmx_msr_bitmap_legacy);
7253 free_page((unsigned long)vmx_msr_bitmap_longmode);
7254 free_page((unsigned long)vmx_io_bitmap_b);
7255 free_page((unsigned long)vmx_io_bitmap_a);
7256
7257 kvm_exit();
7258 }
7259
7260 module_init(vmx_init)
7261 module_exit(vmx_exit)