zpu/hdl/example/sim_small_fpga_top.vhd

   1 -- ZPU
   2 --
   3 -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
   4 --
   5 -- The FreeBSD license
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  22 -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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  34 --------------------------------------------------------------------------------
  35
  36 library ieee;
  37 use ieee.std_logic_1164.all;
  38 use ieee.numeric_std.all;
  39
  40 library work;
  41 use work.zpu_config.all;
  42 use work.zpupkg.all;
  43
  44
  45 entity fpga_top is
  46 end fpga_top;
  47
  48
  49 architecture behave of fpga_top is
  50
  51
  52     signal clk    : std_logic;
  53
  54     signal areset : std_logic := '1';
  55
  56
  57     component  zpu_io is
  58         generic (
  59             log_file:       string  := "log.txt"
  60         );
  61         port (
  62             clk         : in  std_logic;
  63             areset      : in  std_logic;
  64             busy        : out std_logic;
  65             writeEnable : in  std_logic;
  66             readEnable  : in  std_logic;
  67             write       : in  std_logic_vector(wordSize-1 downto 0);
  68             read        : out std_logic_vector(wordSize-1 downto 0);
  69             addr        : in  std_logic_vector(maxAddrBit downto minAddrBit)
  70         );
  71     end component;
  72
  73
  74     signal mem_busy             : std_logic;
  75     signal mem_read             : std_logic_vector(wordSize-1 downto 0);
  76     signal mem_write            : std_logic_vector(wordSize-1 downto 0);
  77     signal mem_addr             : std_logic_vector(maxAddrBitIncIO downto 0);
  78     signal mem_writeEnable      : std_logic;
  79     signal mem_readEnable       : std_logic;
  80     signal mem_writeMask        : std_logic_vector(wordBytes-1 downto 0);
  81
  82     signal enable               : std_logic;
  83
  84     signal dram_mem_busy        : std_logic;
  85     signal dram_mem_read        : std_logic_vector(wordSize-1 downto 0);
  86     signal dram_mem_write       : std_logic_vector(wordSize-1 downto 0);
  87     signal dram_mem_writeEnable : std_logic;
  88     signal dram_mem_readEnable  : std_logic;
  89     signal dram_mem_writeMask   : std_logic_vector(wordBytes-1 downto 0);
  90
  91     signal io_busy              : std_logic;
  92
  93     signal io_mem_read          : std_logic_vector(wordSize-1 downto 0);
  94     signal io_mem_writeEnable   : std_logic;
  95     signal io_mem_readEnable    : std_logic;
  96
  97     signal dram_ready           : std_logic;
  98     signal io_ready             : std_logic;
  99     signal io_reading           : std_logic;
 100     signal interruptcounter     : unsigned(15 downto 0);
 101     signal interrupt            : std_logic;
 102
 103     signal break                : std_logic;
 104
 105 begin
 106
 107     zpu: zpu_core
 108     port map (
 109         clk                 => clk,
 110         reset               => areset,
 111         enable              => enable,
 112         in_mem_busy         => mem_busy,
 113         mem_read            => mem_read,
 114         mem_write           => mem_write,
 115         out_mem_addr        => mem_addr,
 116         out_mem_writeEnable => mem_writeEnable,
 117         out_mem_readEnable  => mem_readEnable,
 118         mem_writeMask       => mem_writeMask,
 119         interrupt           => interrupt,
 120         break               => break
 121     );
 122
 123
 124     ioMap: zpu_io
 125     port map (
 126         clk         => clk,
 127         areset      => areset,
 128         busy        => io_busy,
 129         writeEnable => io_mem_writeEnable,
 130         readEnable  => io_mem_readEnable,
 131         write       => mem_write,
 132         read        => io_mem_read,
 133         addr        => mem_addr(maxAddrBit downto minAddrBit)
 134     );
 135
 136     dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
 137     dram_mem_readEnable  <= mem_readEnable  and not mem_addr(ioBit);
 138     io_mem_writeEnable   <= mem_writeEnable and mem_addr(ioBit);
 139     io_mem_readEnable    <= mem_readEnable  and mem_addr(ioBit);
 140     mem_busy             <= io_busy;
 141
 142
 143     -- Memory reads either come from IO or DRAM. We need to pick the right one.
 144     memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
 145     begin
 146         mem_read <= (others => 'U');
 147         if dram_ready='1' then
 148             mem_read <= dram_mem_read;
 149         end if;
 150
 151         if io_ready='1' then
 152             mem_read <= (others => '0');
 153             mem_read <= io_mem_read;
 154         end if;
 155     end process;
 156
 157
 158     io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
 159
 160     memoryControlSync: process(clk, areset)
 161     begin
 162         if areset = '1' then
 163             enable           <= '0';
 164             io_reading       <= '0';
 165             dram_ready       <= '0';
 166
 167             interruptcounter <= to_unsigned(0, 16);
 168             interrupt        <= '0';
 169
 170         elsif rising_edge(clk) then
 171             enable     <= '1';
 172             io_reading <= io_busy or io_mem_readEnable;
 173             dram_ready <= dram_mem_readEnable;
 174
 175             -- keep interrupt signal high for 16 cycles
 176             interruptcounter <= interruptcounter + 1;
 177             if (interruptcounter < 16) then
 178                 report "Interrupt asserted!" severity note;
 179                 interrupt <='1';
 180             else
 181                 interrupt <='0';
 182             end if;
 183         end if;
 184     end process;
 185
 186     -- wiggle the clock @ 100MHz
 187     clock: process
 188        begin
 189             clk <= '0';
 190            wait for 5 ns;
 191             clk <= '1';
 192            wait for 5 ns;
 193            areset <= '0';
 194     end process clock;
 195
 196
 197 end architecture behave;