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commit	c883cd4a4e4fa1974e5d7d72a79240de88bd26da
author	Bert Lange <b.lange@hzdr.de>
	Tue, 25 Oct 2011 21:26:36 +0000 (25 23:26 +0200)
committer	Bert Lange <b.lange@hzdr.de>
	Tue, 25 Oct 2011 21:26:36 +0000 (25 23:26 +0200)
tree	ff3c0f3f7aa62f809001ea9ac9130683ab98a49e	tree \| snapshot (tar.gz zip)
parent	105f8b40509ea2657e36e13af76b7580029fd2e5	commit \| diff

add: GPIO module to zealot SoC

33 files changed:

zpu/hdl/zealot/devices/gpio.vhdl	[new file with mode: 0644]	blob
zpu/hdl/zealot/devices/phi_io.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do	[new file with mode: 0644]	blob
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/dmips_med1.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/dmips_small1.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/hello_med1.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/hello_small1.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd		diff \| blob \| blame \| history
zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd		diff \| blob \| blame \| history
zpu/hdl/zealot/helpers/zpu_med1.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/helpers/zpu_small1.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/testbenches/small1_tb.vhdl		diff \| blob \| blame \| history
zpu/hdl/zealot/zpu_pkg.vhdl		diff \| blob \| blame \| history

Zylin ZPU - the worlds smallest 32 bit CPU with GCC support

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