| blob | 915f352ccf4e56e729b20792c5a73484d5e9d585 |
1 ------------------------------------------------------------------------------\r
2 ---- ----\r
3 ---- ZPU Package ----\r
4 ---- ----\r
5 ---- http://www.opencores.org/ ----\r
6 ---- ----\r
7 ---- Description: ----\r
8 ---- ZPU is a 32 bits small stack cpu. This is the package. ----\r
9 ---- ----\r
10 ---- To Do: ----\r
11 ---- - ----\r
12 ---- ----\r
13 ---- Author: ----\r
14 ---- - Øyvind Harboe, oyvind.harboe zylin.com ----\r
15 ---- - Salvador E. Tropea, salvador inti.gob.ar ----\r
16 ---- ----\r
17 ------------------------------------------------------------------------------\r
18 ---- ----\r
19 ---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----\r
20 ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----\r
21 ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----\r
22 ---- ----\r
23 ---- Distributed under the BSD license ----\r
24 ---- ----\r
25 ------------------------------------------------------------------------------\r
26 ---- ----\r
27 ---- Design unit: zpupkg, UART (Package) ----\r
28 ---- File name: zpu_medium.vhdl ----\r
29 ---- Note: None ----\r
30 ---- Limitations: None known ----\r
31 ---- Errors: None known ----\r
32 ---- Library: zpu ----\r
33 ---- Dependencies: IEEE.std_logic_1164 ----\r
34 ---- IEEE.numeric_std ----\r
35 ---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----\r
36 ---- Language: VHDL ----\r
37 ---- Wishbone: No ----\r
38 ---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----\r
39 ---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----\r
40 ---- Text editor: SETEdit 0.5.x ----\r
41 ---- ----\r
42 ------------------------------------------------------------------------------\r
43 \r
44 library IEEE;\r
45 use IEEE.std_logic_1164.all;\r
46 use IEEE.numeric_std.all;\r
47 \r
48 package zpupkg is\r
49 constant OPCODE_W : integer:=8;\r
50 \r
51 -- Debug structure, currently only for the trace module\r
52 type zpu_dbgo_t is record\r
53 b_inst : std_logic;\r
54 opcode : unsigned(OPCODE_W-1 downto 0);\r
55 pc : unsigned(31 downto 0);\r
56 sp : unsigned(31 downto 0);\r
57 stk_a : unsigned(31 downto 0);\r
58 stk_b : unsigned(31 downto 0);\r
59 end record;\r
60 \r
61 component Trace is\r
62 generic(\r
63 LOG_FILE : string:="trace.txt"; -- Name of the trace file\r
64 ADDR_W : integer:=16; -- Address width\r
65 WORD_SIZE : integer:=32); -- 16/32\r
66 port(\r
67 clk_i : in std_logic;\r
68 dbg_i : in zpu_dbgo_t;\r
69 stop_i : in std_logic;\r
70 busy_i : in std_logic\r
71 );\r
72 end component Trace;\r
73 \r
74 component ZPUSmallCore is\r
75 generic(\r
76 WORD_SIZE : integer:=32; -- Data width 16/32\r
77 ADDR_W : integer:=16; -- Total address space width (incl. I/O)\r
78 MEM_W : integer:=15; -- Memory (prog+data+stack) width\r
79 D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits\r
80 port(\r
81 clk_i : in std_logic; -- System Clock\r
82 reset_i : in std_logic; -- Synchronous Reset\r
83 interrupt_i : in std_logic; -- Interrupt\r
84 break_o : out std_logic; -- Breakpoint opcode executed\r
85 dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)\r
86 -- BRAM (text, data, bss and stack)\r
87 a_we_o : out std_logic; -- BRAM A port Write Enable\r
88 a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address\r
89 a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port\r
90 a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port\r
91 b_we_o : out std_logic; -- BRAM B port Write Enable\r
92 b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address\r
93 b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port\r
94 b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port\r
95 -- Memory mapped I/O\r
96 mem_busy_i : in std_logic;\r
97 data_i : in unsigned(WORD_SIZE-1 downto 0);\r
98 data_o : out unsigned(WORD_SIZE-1 downto 0);\r
99 addr_o : out unsigned(ADDR_W-1 downto 0);\r
100 write_en_o : out std_logic;\r
101 read_en_o : out std_logic);\r
102 end component ZPUSmallCore;\r
103 \r
104 component ZPUMediumCore is\r
105 generic(\r
106 WORD_SIZE : integer:=32; -- Data width 16/32\r
107 ADDR_W : integer:=16; -- Total address space width (incl. I/O)\r
108 MEM_W : integer:=15; -- Memory (prog+data+stack) width\r
109 D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits\r
110 MULT_PIPE : boolean:=false; -- Pipeline multiplication\r
111 BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)\r
112 ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd\r
113 ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub\r
114 ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel\r
115 ENA_LSHR : boolean:=true; -- lshiftright\r
116 ENA_IDLE : boolean:=false; -- Enable the enable_i input\r
117 FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states\r
118 port(\r
119 clk_i : in std_logic; -- CPU Clock\r
120 reset_i : in std_logic; -- Sync Reset\r
121 enable_i : in std_logic; -- Hold the CPU (after reset)\r
122 break_o : out std_logic; -- Break instruction executed\r
123 dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)\r
124 -- Memory interface\r
125 mem_busy_i : in std_logic; -- Memory is busy\r
126 data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem\r
127 data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem\r
128 addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address\r
129 write_en_o : out std_logic; -- Memory write enable\r
130 read_en_o : out std_logic); -- Memory read enable\r
131 end component ZPUMediumCore;\r
132 \r
133 component Timer is\r
134 port(\r
135 clk_i : in std_logic;\r
136 reset_i : in std_logic;\r
137 we_i : in std_logic;\r
138 data_i : in unsigned(31 downto 0);\r
139 addr_i : in unsigned(0 downto 0);\r
140 data_o : out unsigned(31 downto 0));\r
141 end component Timer;\r
142 \r
143 component gpio is\r
144 port(\r
145 clk_i : in std_logic;\r
146 reset_i : in std_logic;\r
147 --\r
148 we_i : in std_logic;\r
149 data_i : in unsigned(31 downto 0);\r
150 addr_i : in unsigned( 0 downto 0);\r
151 data_o : out unsigned(31 downto 0);\r
152 --\r
153 port_in : in std_logic_vector(31 downto 0);\r
154 port_out : out std_logic_vector(31 downto 0);\r
155 port_dir : out std_logic_vector(31 downto 0)\r
156 );\r
157 end component gpio;\r
158 \r
159 \r
160 component ZPUPhiIO is\r
161 generic(\r
162 BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4\r
163 ENA_LOG : boolean:=true; -- Enable log\r
164 LOG_FILE : string:="log.txt"); -- Name for the log file\r
165 port(\r
166 clk_i : in std_logic; -- System Clock\r
167 reset_i : in std_logic; -- Synchronous Reset\r
168 busy_o : out std_logic; -- I/O is busy\r
169 we_i : in std_logic; -- Write Enable\r
170 re_i : in std_logic; -- Read Enable\r
171 data_i : in unsigned(31 downto 0);\r
172 data_o : out unsigned(31 downto 0);\r
173 addr_i : in unsigned(2 downto 0); -- Address bits 4-2\r
174 --\r
175 rs232_rx_i : in std_logic; -- UART Rx input\r
176 rs232_tx_o : out std_logic; -- UART Tx output\r
177 br_clk_i : in std_logic; -- UART base clock (enable)\r
178 --\r
179 gpio_in : in std_logic_vector(31 downto 0);\r
180 gpio_out : out std_logic_vector(31 downto 0);\r
181 gpio_dir : out std_logic_vector(31 downto 0)\r
182 );\r
183 end component ZPUPhiIO;\r
184 \r
185 -- Opcode decode constants\r
186 -- Note: these are the basic opcodes, always implemented using hardware.\r
187 constant OPCODE_IM : unsigned(7 downto 7):="1";\r
188 constant OPCODE_STORESP : unsigned(7 downto 5):="010";\r
189 constant OPCODE_LOADSP : unsigned(7 downto 5):="011";\r
190 constant OPCODE_EMULATE : unsigned(7 downto 5):="001";\r
191 constant OPCODE_ADDSP : unsigned(7 downto 4):="0001";\r
192 constant OPCODE_SHORT : unsigned(7 downto 4):="0000";\r
193 \r
194 constant OPCODE_BREAK : unsigned(3 downto 0):="0000";\r
195 constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";\r
196 constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010";\r
197 constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011";\r
198 \r
199 constant OPCODE_POPPC : unsigned(3 downto 0):="0100";\r
200 constant OPCODE_ADD : unsigned(3 downto 0):="0101";\r
201 constant OPCODE_AND : unsigned(3 downto 0):="0110";\r
202 constant OPCODE_OR : unsigned(3 downto 0):="0111";\r
203 \r
204 constant OPCODE_LOAD : unsigned(3 downto 0):="1000";\r
205 constant OPCODE_NOT : unsigned(3 downto 0):="1001";\r
206 constant OPCODE_FLIP : unsigned(3 downto 0):="1010";\r
207 constant OPCODE_NOP : unsigned(3 downto 0):="1011";\r
208 \r
209 constant OPCODE_STORE : unsigned(3 downto 0):="1100";\r
210 constant OPCODE_POPSP : unsigned(3 downto 0):="1101";\r
211 constant OPCODE_COMPARE : unsigned(3 downto 0):="1110";\r
212 constant OPCODE_POPINT : unsigned(3 downto 0):="1111";\r
213 \r
214 -- The following instructions are emulated in the small version and\r
215 -- implemented as hardware in the full version.\r
216 -- The constants correpond to the "emulated" instruction number.\r
217 \r
218 -- Enabled by the ENA_LEVEL0 generic:\r
219 constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6);\r
220 constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6);\r
221 constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6);\r
222 constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6);\r
223 -- Enabled by the ENA_LEVEL1 generic:\r
224 constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6);\r
225 constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6);\r
226 constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6);\r
227 constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6);\r
228 constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6);\r
229 constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6);\r
230 -- Enabled by the ENA_LEVEL2 generic:\r
231 constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6);\r
232 constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);\r
233 constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6);\r
234 constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6);\r
235 -- Enabled by the ENA_LSHR generic:\r
236 constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6);\r
237 -- The following opcodes are always emulated.\r
238 constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6);\r
239 constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6);\r
240 constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6);\r
241 constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6);\r
242 constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6);\r
243 constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6);\r
244 constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6);\r
245 constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6);\r
246 constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6);\r
247 constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6);\r
248 constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6);\r
249 constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6);\r
250 end package zpupkg;\r
251 \r
252 library IEEE;\r
253 use IEEE.std_logic_1164.all;\r
254 use IEEE.numeric_std.all;\r
255 \r
256 package UART is\r
257 ----------------------\r
258 -- Very simple UART --\r
259 ----------------------\r
260 component RxUnit is\r
261 port(\r
262 clk_i : in std_logic; -- System clock signal\r
263 reset_i : in std_logic; -- Reset input (sync)\r
264 enable_i : in std_logic; -- Enable input (rate*4)\r
265 read_i : in std_logic; -- Received Byte Read\r
266 rxd_i : in std_logic; -- RS-232 data input\r
267 rxav_o : out std_logic; -- Byte available\r
268 datao_o : out std_logic_vector(7 downto 0)); -- Byte received\r
269 end component RxUnit;\r
270 \r
271 component TxUnit is\r
272 port (\r
273 clk_i : in std_logic; -- Clock signal\r
274 reset_i : in std_logic; -- Reset input\r
275 enable_i : in std_logic; -- Enable input\r
276 load_i : in std_logic; -- Load input\r
277 txd_o : out std_logic; -- RS-232 data output\r
278 busy_o : out std_logic; -- Tx Busy\r
279 datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit\r
280 end component TxUnit;\r
281 \r
282 component BRGen is\r
283 generic(\r
284 COUNT : integer range 0 to 65535);-- Count revolution\r
285 port (\r
286 clk_i : in std_logic; -- Clock\r
287 reset_i : in std_logic; -- Reset input\r
288 ce_i : in std_logic; -- Chip Enable\r
289 o_o : out std_logic); -- Output\r
290 end component BRGen;\r
291 end package UART;\r
292 \r