zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut

   1 -w\r
   2 -g DebugBitstream:No\r
   3 -g Binary:no\r
   4 -g CRC:Enable\r
   5 -g ConfigRate:1\r
   6 -g ProgPin:PullUp\r
   7 -g DonePin:PullUp\r
   8 -g TckPin:PullUp\r
   9 -g TdiPin:PullUp\r
  10 -g TdoPin:PullUp\r
  11 -g TmsPin:PullUp\r
  12 -g UnusedPin:PullDown\r
  13 -g UserID:0xFFFFFFFF\r
  14 -g DCMShutdown:Disable\r
  15 -g StartUpClk:CClk\r
  16 -g DONE_cycle:4\r
  17 -g GTS_cycle:5\r
  18 -g GWE_cycle:6\r
  19 -g LCK_cycle:NoWait\r
  20 -g Security:None\r
  21 -g DonePipe:No\r
  22 -g DriveDone:No\r