zpu/hdl/example/sim_small_fpga_top_noint.vhd

   1 -- ZPU
   2 --
   3 -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
   4 --
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  34
  35 library ieee;
  36 use ieee.std_logic_1164.all;
  37 use ieee.numeric_std.all;
  38
  39 library work;
  40 use work.zpu_config.all;
  41 use work.zpupkg.all;
  42
  43
  44 entity fpga_top is
  45 end fpga_top;
  46
  47
  48 architecture behave of fpga_top is
  49
  50
  51     signal clk    : std_logic;
  52
  53     signal areset : std_logic := '1';
  54
  55
  56     component  zpu_io is
  57         generic (
  58             log_file:       string  := "log.txt"
  59         );
  60         port (
  61             clk         : in  std_logic;
  62             areset      : in  std_logic;
  63             busy        : out std_logic;
  64             writeEnable : in  std_logic;
  65             readEnable  : in  std_logic;
  66             write       : in  std_logic_vector(wordSize-1 downto 0);
  67             read        : out std_logic_vector(wordSize-1 downto 0);
  68             addr        : in  std_logic_vector(maxAddrBit downto minAddrBit)
  69         );
  70     end component;
  71
  72
  73     signal mem_busy             : std_logic;
  74     signal mem_read             : std_logic_vector(wordSize-1 downto 0);
  75     signal mem_write            : std_logic_vector(wordSize-1 downto 0);
  76     signal mem_addr             : std_logic_vector(maxAddrBitIncIO downto 0);
  77     signal mem_writeEnable      : std_logic;
  78     signal mem_readEnable       : std_logic;
  79     signal mem_writeMask        : std_logic_vector(wordBytes-1 downto 0);
  80
  81     signal enable               : std_logic;
  82
  83     signal dram_mem_busy        : std_logic;
  84     signal dram_mem_read        : std_logic_vector(wordSize-1 downto 0);
  85     signal dram_mem_write       : std_logic_vector(wordSize-1 downto 0);
  86     signal dram_mem_writeEnable : std_logic;
  87     signal dram_mem_readEnable  : std_logic;
  88     signal dram_mem_writeMask   : std_logic_vector(wordBytes-1 downto 0);
  89
  90     signal io_busy              : std_logic;
  91
  92     signal io_mem_read          : std_logic_vector(wordSize-1 downto 0);
  93     signal io_mem_writeEnable   : std_logic;
  94     signal io_mem_readEnable    : std_logic;
  95
  96     signal dram_ready           : std_logic;
  97     signal io_ready             : std_logic;
  98     signal io_reading           : std_logic;
  99
 100     signal break                : std_logic;
 101
 102
 103 begin
 104
 105     zpu: zpu_core
 106     port map (
 107         clk                 => clk,
 108         reset               => areset,
 109         enable              => enable,
 110         in_mem_busy         => mem_busy,
 111         mem_read            => mem_read,
 112         mem_write           => mem_write,
 113         out_mem_addr        => mem_addr,
 114         out_mem_writeEnable => mem_writeEnable,
 115         out_mem_readEnable  => mem_readEnable,
 116         mem_writeMask       => mem_writeMask,
 117         interrupt           => '0',
 118         break               => break
 119     );
 120
 121
 122     ioMap: zpu_io
 123     port map (
 124         clk         => clk,
 125         areset      => areset,
 126         busy        => io_busy,
 127         writeEnable => io_mem_writeEnable,
 128         readEnable  => io_mem_readEnable,
 129         write       => mem_write,
 130         read        => io_mem_read,
 131         addr        => mem_addr(maxAddrBit downto minAddrBit)
 132     );
 133
 134     dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
 135     dram_mem_readEnable  <= mem_readEnable  and not mem_addr(ioBit);
 136     io_mem_writeEnable   <= mem_writeEnable and mem_addr(ioBit);
 137     io_mem_readEnable    <= mem_readEnable  and mem_addr(ioBit);
 138     mem_busy             <= io_busy;
 139
 140
 141     -- Memory reads either come from IO or DRAM. We need to pick the right one.
 142     memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
 143     begin
 144         mem_read <= (others => 'U');
 145         if dram_ready='1' then
 146             mem_read <= dram_mem_read;
 147         end if;
 148
 149         if io_ready='1' then
 150             mem_read <= (others => '0');
 151             mem_read <= io_mem_read;
 152         end if;
 153     end process;
 154
 155
 156
 157     io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
 158
 159     memoryControlSync: process(clk, areset)
 160     begin
 161         if areset = '1' then
 162             enable     <= '0';
 163             io_reading <= '0';
 164             dram_ready <= '0';
 165
 166         elsif rising_edge(clk) then
 167             enable     <= '1';
 168             io_reading <= io_busy or io_mem_readEnable;
 169             dram_ready <= dram_mem_readEnable;
 170         end if;
 171     end process;
 172
 173     -- wiggle the clock @ 100MHz
 174     clock: process
 175        begin
 176             clk <= '0';
 177            wait for 5 ns;
 178             clk <= '1';
 179            wait for 5 ns;
 180            areset <= '0';
 181     end process clock;
 182
 183
 184 end architecture behave;