add: GPIO module to zealot SoC
[zpu.git] / zpu / hdl / example_medium / zpu_config_trace.vhd
bloba5b9192132b856cd935c0f2bbd7b73a813862d67
1 library ieee;
2 use ieee.std_logic_1164.all;
4 package zpu_config is
6 constant Generate_Trace : boolean := true;
7 constant wordPower : integer := 5;
8 -- during simulation, set this to '0' to get matching trace.txt
9 constant DontCareValue : std_logic := '0';
10 -- Clock frequency in MHz.
11 constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
12 constant maxAddrBitIncIO : integer := 27;
13 constant maxAddrBitDRAM : integer := 16;
14 constant maxAddrBitBRAM : integer := 16;
15 constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8";
17 end zpu_config;