mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / northbridge / intel / gm45 / acpi / gm45.asl
blob4e86092092cc0d724b36892f8005c030415cc814
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include "hostbridge.asl"
4 #include <southbridge/intel/i82801ix/i82801ix.h>
6 /* PCI Device Resource Consumption */
7 Device (PDRC)
9         Name (_HID, EISAID("PNP0C02"))
10         Name (_UID, 1)
12         // This does not seem to work correctly yet - set values statically for
13         // now.
14         Name (PDRS, ResourceTemplate() {
15                 Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
16                 Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
17                 Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
18                 Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE,  0x00001000)
19                 Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
20                 Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
21                 Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
22         })
24         // Current Resource Settings
25         Method (_CRS, 0, Serialized)
26         {
27                 Return(PDRS)
28         }
31 // PCIe graphics port 0:1.0
32 #include "peg.asl"
34 // Integrated graphics 0:2.0
35 #include <drivers/intel/gma/acpi/gfx.asl>