src/northbridge/intel/gm45/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/bootblock.h>
   4 #include <assert.h>
   5 #include <device/pci_ops.h>
   6 #include <types.h>
   7
   8 #include "gm45.h"
   9
  10 static uint32_t encode_pciexbar_length(void)
  11 {
  12         switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
  13         case 256: return 0 << 1;
  14         case 128: return 1 << 1;
  15         case  64: return 2 << 1;
  16         default:  return dead_code_t(uint32_t);
  17         }
  18 }
  19
  20 void bootblock_early_northbridge_init(void)
  21 {
  22         /*
  23          * The "io" variant of the config access is explicitly used to
  24          * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
  25          * true. That way all subsequent non-explicit config accesses use
  26          * MCFG. This code also assumes that bootblock_northbridge_init() is
  27          * the first thing called in the non-asm boot block code. The final
  28          * assumption is that no assembly code is using the
  29          * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
  30          *
  31          * The PCIEXBAR is assumed to live in the memory mapped IO space under
  32          * 4GiB.
  33          */
  34         const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
  35         pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
  36         pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
  37 }