src/northbridge/intel/haswell/haswell.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef NORTHBRIDGE_INTEL_HASWELL_HASWELL_H
   4 #define NORTHBRIDGE_INTEL_HASWELL_HASWELL_H
   5
   6 #include <device/device.h>
   7 #include <northbridge/intel/common/fixed_bars.h>
   8
   9 #include "memmap.h"
  10 #include "registers/dmibar.h"
  11 #include "registers/epbar.h"
  12 #include "registers/host_bridge.h"
  13 #include "registers/mchbar.h"
  14 #include "registers/pcie_graphics.h"
  15
  16 /* Device 0:0.0 PCI configuration space (Host Bridge) */
  17 #define HOST_BRIDGE     PCI_DEV(0, 0, 0)
  18
  19 /* Device 0:2.0 PCI configuration space (Graphics Device) */
  20
  21 #define MSAC            0x62    /* Multi Size Aperture Control */
  22
  23 #define ARCHDIS         0xff0   /* DMA Remap Engine Policy Control */
  24 #define  DMAR_LCKDN     (1 << 31)
  25 #define  SPCAPCTRL      (1 << 25)
  26 #define  L3HIT2PEND_DIS (1 << 20)
  27 #define  PRSCAPDIS      (1 << 2)
  28 #define  GLBIOTLBINV    (1 << 1)
  29 #define  GLBCTXTINV     (1 << 0)
  30
  31 void mb_late_romstage_setup(void); /* optional */
  32
  33 void haswell_early_initialization(void);
  34 void haswell_late_initialization(void);
  35 void haswell_unhide_peg(void);
  36
  37 void dmi_early_init(void);
  38 void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev);
  39
  40 void report_platform_info(void);
  41
  42 struct acpi_rsdp;
  43 unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start,
  44                                             struct acpi_rsdp *rsdp);
  45
  46 #endif /* NORTHBRIDGE_INTEL_HASWELL_HASWELL_H */