src/northbridge/intel/ironlake/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/bootblock.h>
   4 #include <assert.h>
   5 #include <device/pci_ops.h>
   6 #include <types.h>
   7
   8 #include "ironlake.h"
   9
  10 static uint32_t encode_pciexbar_length(void)
  11 {
  12         /* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */
  13         switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
  14                 case 256: return 0 << 1;
  15                 case 128: return 6 << 1;
  16                 case  64: return 7 << 1;
  17                 default:  return dead_code_t(uint32_t);
  18         }
  19 }
  20
  21 void bootblock_early_northbridge_init(void)
  22 {
  23         /*
  24          * The QuickPath bus number is the topmost bus number, as per the value
  25          * of the SAD_PCIEXBAR register. The register defaults to 256 buses on
  26          * reset. Thus, hardcode the bus number when first setting up PCIEXBAR.
  27          */
  28         const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
  29
  30         const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
  31         pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0);
  32         pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32);
  33 }