src/northbridge/intel/ironlake/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H
   4 #define NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H
   5
   6 #include <drivers/intel/gma/i915.h>
   7
   8 /*
   9  * Digital Port Hotplug Enable:
  10  *  0x04 = Enabled, 2ms short pulse
  11  *  0x05 = Enabled, 4.5ms short pulse
  12  *  0x06 = Enabled, 6ms short pulse
  13  *  0x07 = Enabled, 100ms short pulse
  14  */
  15 struct northbridge_intel_ironlake_config {
  16         u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
  17         u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
  18         u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
  19
  20         enum {
  21                 PANEL_PORT_LVDS = 0,
  22                 PANEL_PORT_DP_A = 1, /* Also known as eDP */
  23                 PANEL_PORT_DP_C = 2,
  24                 PANEL_PORT_DP_D = 3,
  25         } gpu_panel_port_select;
  26
  27         u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
  28         u16 gpu_panel_power_up_delay;            /* T1+T2 time sequence */
  29         u16 gpu_panel_power_down_delay;          /* T3 time sequence */
  30         u16 gpu_panel_power_backlight_on_delay;  /* T5 time sequence */
  31         u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
  32
  33         u32 gpu_cpu_backlight;  /* CPU Backlight PWM value */
  34         u32 gpu_pch_backlight;  /* PCH Backlight PWM value */
  35
  36         struct i915_gpu_controller_info gfx;
  37 };
  38
  39 #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */