src/northbridge/intel/ironlake/gma.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/io.h>
   4 #include <device/mmio.h>
   5 #include <console/console.h>
   6 #include <delay.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <device/pci_ops.h>
  11 #include <drivers/intel/gma/edid.h>
  12 #include <drivers/intel/gma/i915.h>
  13 #include <drivers/intel/gma/intel_bios.h>
  14 #include <drivers/intel/gma/libgfxinit.h>
  15 #include <pc80/vga.h>
  16 #include <drivers/intel/gma/opregion.h>
  17 #include <types.h>
  18
  19 #include "chip.h"
  20 #include "ironlake.h"
  21
  22 /* some vga option roms are used for several chipsets but they only have one
  23  * PCI ID in their header. If we encounter such an option rom, we need to do
  24  * the mapping ourselves
  25  */
  26
  27 u32 map_oprom_vendev(u32 vendev)
  28 {
  29         u32 new_vendev = vendev;
  30
  31         /* none currently. */
  32
  33         return new_vendev;
  34 }
  35
  36 static struct resource *gtt_res = NULL;
  37
  38 u32 gtt_read(u32 reg)
  39 {
  40         return read32(res2mmio(gtt_res, reg, 0));
  41 }
  42
  43 void gtt_write(u32 reg, u32 data)
  44 {
  45         write32(res2mmio(gtt_res, reg, 0), data);
  46 }
  47
  48 #define GTT_RETRY 1000
  49 int gtt_poll(u32 reg, u32 mask, u32 value)
  50 {
  51         unsigned int try = GTT_RETRY;
  52         u32 data;
  53
  54         while (try--) {
  55                 data = gtt_read(reg);
  56                 if ((data & mask) == value)
  57                         return 1;
  58                 udelay(10);
  59         }
  60
  61         printk(BIOS_ERR, "GT init timeout\n");
  62         return 0;
  63 }
  64
  65 static void gma_pm_init_post_vbios(struct device *dev)
  66 {
  67         struct northbridge_intel_ironlake_config *conf = dev->chip_info;
  68         u32 reg32;
  69
  70         printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
  71
  72         /* Setup Digital Port Hotplug */
  73         reg32 = gtt_read(0xc4030);
  74         if (!reg32) {
  75                 reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
  76                 reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
  77                 reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
  78                 gtt_write(0xc4030, reg32);
  79         }
  80
  81         /* Setup Panel Power On Delays */
  82         reg32 = gtt_read(0xc7208);
  83         if (!reg32) {
  84                 reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
  85                 reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
  86                 reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
  87                 gtt_write(0xc7208, reg32);
  88         }
  89
  90         /* Setup Panel Power Off Delays */
  91         reg32 = gtt_read(0xc720c);
  92         if (!reg32) {
  93                 reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
  94                 reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
  95                 gtt_write(0xc720c, reg32);
  96         }
  97
  98         /* Setup Panel Power Cycle Delay */
  99         if (conf->gpu_panel_power_cycle_delay) {
 100                 reg32 = gtt_read(0xc7210);
 101                 reg32 &= ~0xff;
 102                 reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
 103                 gtt_write(0xc7210, reg32);
 104         }
 105
 106         /* Enable Backlight if needed */
 107         if (conf->gpu_cpu_backlight) {
 108                 gtt_write(0x48250, (1 << 31));
 109                 gtt_write(0x48254, conf->gpu_cpu_backlight);
 110         }
 111         if (conf->gpu_pch_backlight) {
 112                 gtt_write(0xc8250, (1 << 31));
 113                 gtt_write(0xc8254, conf->gpu_pch_backlight);
 114         }
 115 }
 116
 117 /* Enable SCI to ACPI _GPE._L06 */
 118 static void gma_enable_swsci(void)
 119 {
 120         u16 reg16;
 121
 122         /* clear DMISCI status */
 123         reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
 124         reg16 &= DMISCI_STS;
 125         outw(reg16, DEFAULT_PMBASE + TCO1_STS);
 126
 127         /* clear acpi tco status */
 128         outl(TCOSCI_STS, DEFAULT_PMBASE + GPE0_STS);
 129
 130         /* enable acpi tco scis */
 131         reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
 132         reg16 |= TCOSCI_EN;
 133         outw(reg16, DEFAULT_PMBASE + GPE0_EN);
 134 }
 135
 136 static void gma_func0_init(struct device *dev)
 137 {
 138         intel_gma_init_igd_opregion();
 139
 140         if (!CONFIG(NO_GFX_INIT))
 141                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 142
 143         gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 144         if (!gtt_res || !gtt_res->base)
 145                 return;
 146
 147         if (!acpi_is_wakeup_s3() &&
 148             CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
 149                 struct northbridge_intel_ironlake_config *conf = dev->chip_info;
 150                 int lightup_ok;
 151                 printk(BIOS_SPEW, "Initializing VGA without OPROM.");
 152
 153                 gma_gfxinit(&lightup_ok);
 154                 /* Linux relies on VBT for panel info. */
 155                 generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
 156         } else {
 157                 /* PCI Init, will run VBIOS */
 158                 pci_dev_init(dev);
 159         }
 160
 161         /* Post VBIOS init */
 162         gma_pm_init_post_vbios(dev);
 163
 164         gma_enable_swsci();
 165 }
 166
 167 static void gma_read_resources(struct device *dev)
 168 {
 169         pci_dev_read_resources(dev);
 170
 171         struct resource *res;
 172
 173         /* Set the graphics memory to write combining. */
 174         res = probe_resource(dev, PCI_BASE_ADDRESS_2);
 175         if (!res) {
 176                 printk(BIOS_DEBUG, "gma: memory resource not found.\n");
 177                 return;
 178         }
 179         res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
 180         pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xd0000001);
 181         pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0);
 182         res->base = (resource_t)0xd0000000;
 183         res->size = (resource_t)0x10000000;
 184 }
 185
 186 static void gma_generate_ssdt(const struct device *device)
 187 {
 188         const struct northbridge_intel_ironlake_config *chip = device->chip_info;
 189
 190         drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 191 }
 192
 193 static struct device_operations gma_func0_ops = {
 194         .read_resources         = gma_read_resources,
 195         .set_resources          = pci_dev_set_resources,
 196         .enable_resources       = pci_dev_enable_resources,
 197         .acpi_fill_ssdt         = gma_generate_ssdt,
 198         .init                   = gma_func0_init,
 199         .ops_pci                = &pci_dev_ops_pci,
 200 };
 201
 202 static const unsigned short pci_device_ids[] = {
 203         0x0046, 0x0102, 0x0106, 0x010a, 0x0112,
 204         0x0116, 0x0122, 0x0126, 0x0156,
 205         0x0166,
 206         0
 207 };
 208
 209 static const struct pci_driver gma __pci_driver = {
 210         .ops     = &gma_func0_ops,
 211         .vendor  = PCI_VID_INTEL,
 212         .devices = pci_device_ids,
 213 };