src/northbridge/intel/ironlake/raminit_tables.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef RAMINIT_TABLES_H
   4 #define RAMINIT_TABLES_H
   5
   6 #include <types.h>
   7
   8 /* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */
   9 extern const u8 u8_FFFD1240[2][5][9][4][4];
  10
  11 extern const u16 u16_FFFE0EB8[2][4];
  12
  13 /* [CARD][LANE][CLOCK_SPEED] */
  14 extern const u16 u16_ffd1188[2][9][4];
  15
  16 /* [REVISION][CHANNEL][CLOCK_INDEX][?] */
  17 extern const u8 u8_FFFD1891[2][2][4][12];
  18
  19 extern const u8 u8_FFFD17E0[2][5][4][4];
  20
  21 extern const u8 u8_FFFD0C78[2][5][4][2][2][4];
  22
  23 extern const u16 u16_fffd0c68[3];
  24
  25 extern const u16 u16_fffd0c70[2][2];
  26
  27 extern const u16 u16_fffd0c50[3][2][2];
  28
  29 /* [CLOCK_INDEX] */
  30 extern const u16 min_cycletime[4];
  31
  32 /* [CLOCK_INDEX] */
  33 extern const u16 min_cas_latency_time[4];
  34
  35 /* [CHANNEL][EXT_SILICON_REVISION][?][CLOCK_INDEX] */
  36 /* On other mobos may also depend on slot and rank.  */
  37 extern const u8 u8_FFFD0EF8[2][5][4][4];
  38
  39 /* [CLOCK_SPEED] */
  40 extern const u8 u8_FFFD1218[4];
  41
  42 extern const u8 reg178_min[];
  43 extern const u8 reg178_max[];
  44 extern const u8 reg178_step[];
  45
  46 extern const u16 u16_ffd1178[2][4];
  47
  48 extern const u16 u16_fe0eb8[2][4];
  49
  50 extern const u8 lut16[4];
  51
  52 #endif // RAMINIT_TABLES_H