repo.or.cz
/
coreboot2.git
/
tree
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
log
|
graphiclog1
|
graphiclog2
|
commit
|
commitdiff
|
tree
|
refs
|
edit
|
fork
history
|
HEAD
|
snapshot (
tar.gz
zip
)
mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git]
/
src
/
northbridge
/
intel
/
haswell
/
registers
/
tree
6e38bf8813f8fc798067d611707a43d1498a7b6c
drwxr-xr-x
..
-rw-r--r--
1460
dmibar.h
blob
|
blame
|
history
|
raw
-rw-r--r--
751
epbar.h
blob
|
blame
|
history
|
raw
-rw-r--r--
2039
host_bridge.h
blob
|
blame
|
history
|
raw
-rw-r--r--
2542
mchbar.h
blob
|
blame
|
history
|
raw
-rw-r--r--
675
pcie_graphics.h
blob
|
blame
|
history
|
raw
