lib/Target/X86/X86FixupLEAs.cpp

   1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the pass that finds instructions that can be
  11 // re-written as LEA instructions in order to reduce pipeline delays.
  12 // When optimizing for size it replaces suitable LEAs with INC or DEC.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "X86.h"
  17 #include "X86InstrInfo.h"
  18 #include "X86Subtarget.h"
  19 #include "llvm/ADT/Statistic.h"
  20 #include "llvm/CodeGen/MachineFunctionPass.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/Passes.h"
  23 #include "llvm/CodeGen/TargetSchedule.h"
  24 #include "llvm/Support/Debug.h"
  25 #include "llvm/Support/raw_ostream.h"
  26 using namespace llvm;
  27
  28 namespace llvm {
  29 void initializeFixupLEAPassPass(PassRegistry &);
  30 }
  31
  32 #define FIXUPLEA_DESC "X86 LEA Fixup"
  33 #define FIXUPLEA_NAME "x86-fixup-LEAs"
  34
  35 #define DEBUG_TYPE FIXUPLEA_NAME
  36
  37 STATISTIC(NumLEAs, "Number of LEA instructions created");
  38
  39 namespace {
  40 class FixupLEAPass : public MachineFunctionPass {
  41   enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
  42
  43   /// Loop over all of the instructions in the basic block
  44   /// replacing applicable instructions with LEA instructions,
  45   /// where appropriate.
  46   bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
  47
  48
  49   /// Given a machine register, look for the instruction
  50   /// which writes it in the current basic block. If found,
  51   /// try to replace it with an equivalent LEA instruction.
  52   /// If replacement succeeds, then also process the newly created
  53   /// instruction.
  54   void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
  55                     MachineFunction::iterator MFI);
  56
  57   /// Given a memory access or LEA instruction
  58   /// whose address mode uses a base and/or index register, look for
  59   /// an opportunity to replace the instruction which sets the base or index
  60   /// register with an equivalent LEA instruction.
  61   void processInstruction(MachineBasicBlock::iterator &I,
  62                           MachineFunction::iterator MFI);
  63
  64   /// Given a LEA instruction which is unprofitable
  65   /// on Silvermont try to replace it with an equivalent ADD instruction
  66   void processInstructionForSLM(MachineBasicBlock::iterator &I,
  67                                 MachineFunction::iterator MFI);
  68
  69
  70   /// Given a LEA instruction which is unprofitable
  71   /// on SNB+ try to replace it with other instructions.
  72   /// According to Intel's Optimization Reference Manual:
  73   /// " For LEA instructions with three source operands and some specific
  74   ///   situations, instruction latency has increased to 3 cycles, and must
  75   ///   dispatch via port 1:
  76   /// - LEA that has all three source operands: base, index, and offset
  77   /// - LEA that uses base and index registers where the base is EBP, RBP,
  78   ///   or R13
  79   /// - LEA that uses RIP relative addressing mode
  80   /// - LEA that uses 16-bit addressing mode "
  81   /// This function currently handles the first 2 cases only.
  82   MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
  83                                           MachineFunction::iterator MFI);
  84
  85   /// Look for LEAs that add 1 to reg or subtract 1 from reg
  86   /// and convert them to INC or DEC respectively.
  87   bool fixupIncDec(MachineBasicBlock::iterator &I,
  88                    MachineFunction::iterator MFI) const;
  89
  90   /// Determine if an instruction references a machine register
  91   /// and, if so, whether it reads or writes the register.
  92   RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
  93
  94   /// Step backwards through a basic block, looking
  95   /// for an instruction which writes a register within
  96   /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
  97   MachineBasicBlock::iterator searchBackwards(MachineOperand &p,
  98                                               MachineBasicBlock::iterator &I,
  99                                               MachineFunction::iterator MFI);
 100
 101   /// if an instruction can be converted to an
 102   /// equivalent LEA, insert the new instruction into the basic block
 103   /// and return a pointer to it. Otherwise, return zero.
 104   MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
 105                                    MachineBasicBlock::iterator &MBBI) const;
 106
 107 public:
 108   static char ID;
 109
 110   StringRef getPassName() const override { return FIXUPLEA_DESC; }
 111
 112   FixupLEAPass() : MachineFunctionPass(ID) {
 113     initializeFixupLEAPassPass(*PassRegistry::getPassRegistry());
 114   }
 115
 116   /// Loop over all of the basic blocks,
 117   /// replacing instructions by equivalent LEA instructions
 118   /// if needed and when possible.
 119   bool runOnMachineFunction(MachineFunction &MF) override;
 120
 121   // This pass runs after regalloc and doesn't support VReg operands.
 122   MachineFunctionProperties getRequiredProperties() const override {
 123     return MachineFunctionProperties().set(
 124         MachineFunctionProperties::Property::NoVRegs);
 125   }
 126
 127 private:
 128   TargetSchedModel TSM;
 129   MachineFunction *MF;
 130   const X86InstrInfo *TII; // Machine instruction info.
 131   bool OptIncDec;
 132   bool OptLEA;
 133 };
 134 }
 135
 136 char FixupLEAPass::ID = 0;
 137
 138 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
 139
 140 MachineInstr *
 141 FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
 142                                  MachineBasicBlock::iterator &MBBI) const {
 143   MachineInstr &MI = *MBBI;
 144   switch (MI.getOpcode()) {
 145   case X86::MOV32rr:
 146   case X86::MOV64rr: {
 147     const MachineOperand &Src = MI.getOperand(1);
 148     const MachineOperand &Dest = MI.getOperand(0);
 149     MachineInstr *NewMI =
 150         BuildMI(*MF, MI.getDebugLoc(),
 151                 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
 152                                                         : X86::LEA64r))
 153             .add(Dest)
 154             .add(Src)
 155             .addImm(1)
 156             .addReg(0)
 157             .addImm(0)
 158             .addReg(0);
 159     MFI->insert(MBBI, NewMI); // Insert the new inst
 160     return NewMI;
 161   }
 162   case X86::ADD64ri32:
 163   case X86::ADD64ri8:
 164   case X86::ADD64ri32_DB:
 165   case X86::ADD64ri8_DB:
 166   case X86::ADD32ri:
 167   case X86::ADD32ri8:
 168   case X86::ADD32ri_DB:
 169   case X86::ADD32ri8_DB:
 170   case X86::ADD16ri:
 171   case X86::ADD16ri8:
 172   case X86::ADD16ri_DB:
 173   case X86::ADD16ri8_DB:
 174     if (!MI.getOperand(2).isImm()) {
 175       // convertToThreeAddress will call getImm()
 176       // which requires isImm() to be true
 177       return nullptr;
 178     }
 179     break;
 180   case X86::ADD16rr:
 181   case X86::ADD16rr_DB:
 182     if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
 183       // if src1 != src2, then convertToThreeAddress will
 184       // need to create a Virtual register, which we cannot do
 185       // after register allocation.
 186       return nullptr;
 187     }
 188   }
 189   return TII->convertToThreeAddress(MFI, MI, nullptr);
 190 }
 191
 192 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
 193
 194 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
 195   if (skipFunction(Func.getFunction()))
 196     return false;
 197
 198   MF = &Func;
 199   const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
 200   OptIncDec = !ST.slowIncDec() || Func.getFunction().optForMinSize();
 201   OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA();
 202
 203   if (!OptLEA && !OptIncDec)
 204     return false;
 205
 206   TSM.init(&Func.getSubtarget());
 207   TII = ST.getInstrInfo();
 208
 209   LLVM_DEBUG(dbgs() << "Start X86FixupLEAs\n";);
 210   // Process all basic blocks.
 211   for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
 212     processBasicBlock(Func, I);
 213   LLVM_DEBUG(dbgs() << "End X86FixupLEAs\n";);
 214
 215   return true;
 216 }
 217
 218 FixupLEAPass::RegUsageState
 219 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
 220   RegUsageState RegUsage = RU_NotUsed;
 221   MachineInstr &MI = *I;
 222
 223   for (unsigned int i = 0; i < MI.getNumOperands(); ++i) {
 224     MachineOperand &opnd = MI.getOperand(i);
 225     if (opnd.isReg() && opnd.getReg() == p.getReg()) {
 226       if (opnd.isDef())
 227         return RU_Write;
 228       RegUsage = RU_Read;
 229     }
 230   }
 231   return RegUsage;
 232 }
 233
 234 /// getPreviousInstr - Given a reference to an instruction in a basic
 235 /// block, return a reference to the previous instruction in the block,
 236 /// wrapping around to the last instruction of the block if the block
 237 /// branches to itself.
 238 static inline bool getPreviousInstr(MachineBasicBlock::iterator &I,
 239                                     MachineFunction::iterator MFI) {
 240   if (I == MFI->begin()) {
 241     if (MFI->isPredecessor(&*MFI)) {
 242       I = --MFI->end();
 243       return true;
 244     } else
 245       return false;
 246   }
 247   --I;
 248   return true;
 249 }
 250
 251 MachineBasicBlock::iterator
 252 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
 253                               MachineFunction::iterator MFI) {
 254   int InstrDistance = 1;
 255   MachineBasicBlock::iterator CurInst;
 256   static const int INSTR_DISTANCE_THRESHOLD = 5;
 257
 258   CurInst = I;
 259   bool Found;
 260   Found = getPreviousInstr(CurInst, MFI);
 261   while (Found && I != CurInst) {
 262     if (CurInst->isCall() || CurInst->isInlineAsm())
 263       break;
 264     if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
 265       break; // too far back to make a difference
 266     if (usesRegister(p, CurInst) == RU_Write) {
 267       return CurInst;
 268     }
 269     InstrDistance += TSM.computeInstrLatency(&*CurInst);
 270     Found = getPreviousInstr(CurInst, MFI);
 271   }
 272   return MachineBasicBlock::iterator();
 273 }
 274
 275 static inline bool isLEA(const int Opcode) {
 276   return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
 277          Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
 278 }
 279
 280 static inline bool isInefficientLEAReg(unsigned int Reg) {
 281   return Reg == X86::EBP || Reg == X86::RBP ||
 282          Reg == X86::R13D || Reg == X86::R13;
 283 }
 284
 285 static inline bool isRegOperand(const MachineOperand &Op) {
 286   return Op.isReg() && Op.getReg() != X86::NoRegister;
 287 }
 288 /// hasIneffecientLEARegs - LEA that uses base and index registers
 289 /// where the base is EBP, RBP, or R13
 290 // TODO: use a variant scheduling class to model the latency profile
 291 // of LEA instructions, and implement this logic as a scheduling predicate.
 292 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
 293                                             const MachineOperand &Index) {
 294   return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
 295          isRegOperand(Index);
 296 }
 297
 298 static inline bool hasLEAOffset(const MachineOperand &Offset) {
 299   return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
 300 }
 301
 302 static inline int getADDrrFromLEA(int LEAOpcode) {
 303   switch (LEAOpcode) {
 304   default:
 305     llvm_unreachable("Unexpected LEA instruction");
 306   case X86::LEA16r:
 307     return X86::ADD16rr;
 308   case X86::LEA32r:
 309     return X86::ADD32rr;
 310   case X86::LEA64_32r:
 311   case X86::LEA64r:
 312     return X86::ADD64rr;
 313   }
 314 }
 315
 316 static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) {
 317   bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
 318   switch (LEAOpcode) {
 319   default:
 320     llvm_unreachable("Unexpected LEA instruction");
 321   case X86::LEA16r:
 322     return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri;
 323   case X86::LEA32r:
 324   case X86::LEA64_32r:
 325     return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
 326   case X86::LEA64r:
 327     return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
 328   }
 329 }
 330
 331 /// isLEASimpleIncOrDec - Does this LEA have one these forms:
 332 /// lea  %reg, 1(%reg)
 333 /// lea  %reg, -1(%reg)
 334 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
 335   unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
 336   unsigned DstReg = LEA.getOperand(0).getReg();
 337   unsigned AddrDispOp = 1 + X86::AddrDisp;
 338   return SrcReg == DstReg &&
 339          LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
 340          LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
 341          LEA.getOperand(AddrDispOp).isImm() &&
 342          (LEA.getOperand(AddrDispOp).getImm() == 1 ||
 343           LEA.getOperand(AddrDispOp).getImm() == -1);
 344 }
 345
 346 bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
 347                                MachineFunction::iterator MFI) const {
 348   MachineInstr &MI = *I;
 349   int Opcode = MI.getOpcode();
 350   if (!isLEA(Opcode))
 351     return false;
 352
 353   if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
 354     int NewOpcode;
 355     bool isINC = MI.getOperand(4).getImm() == 1;
 356     switch (Opcode) {
 357     case X86::LEA16r:
 358       NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
 359       break;
 360     case X86::LEA32r:
 361     case X86::LEA64_32r:
 362       NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
 363       break;
 364     case X86::LEA64r:
 365       NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
 366       break;
 367     }
 368
 369     MachineInstr *NewMI =
 370         BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
 371             .add(MI.getOperand(0))
 372             .add(MI.getOperand(1));
 373     MFI->erase(I);
 374     I = static_cast<MachineBasicBlock::iterator>(NewMI);
 375     return true;
 376   }
 377   return false;
 378 }
 379
 380 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
 381                                       MachineFunction::iterator MFI) {
 382   // Process a load, store, or LEA instruction.
 383   MachineInstr &MI = *I;
 384   const MCInstrDesc &Desc = MI.getDesc();
 385   int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
 386   if (AddrOffset >= 0) {
 387     AddrOffset += X86II::getOperandBias(Desc);
 388     MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
 389     if (p.isReg() && p.getReg() != X86::ESP) {
 390       seekLEAFixup(p, I, MFI);
 391     }
 392     MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
 393     if (q.isReg() && q.getReg() != X86::ESP) {
 394       seekLEAFixup(q, I, MFI);
 395     }
 396   }
 397 }
 398
 399 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
 400                                 MachineBasicBlock::iterator &I,
 401                                 MachineFunction::iterator MFI) {
 402   MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
 403   if (MBI != MachineBasicBlock::iterator()) {
 404     MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
 405     if (NewMI) {
 406       ++NumLEAs;
 407       LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
 408       // now to replace with an equivalent LEA...
 409       LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
 410       MFI->erase(MBI);
 411       MachineBasicBlock::iterator J =
 412           static_cast<MachineBasicBlock::iterator>(NewMI);
 413       processInstruction(J, MFI);
 414     }
 415   }
 416 }
 417
 418 void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
 419                                             MachineFunction::iterator MFI) {
 420   MachineInstr &MI = *I;
 421   const int Opcode = MI.getOpcode();
 422   if (!isLEA(Opcode))
 423     return;
 424   if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() ||
 425       !TII->isSafeToClobberEFLAGS(*MFI, I))
 426     return;
 427   const unsigned DstR = MI.getOperand(0).getReg();
 428   const unsigned SrcR1 = MI.getOperand(1).getReg();
 429   const unsigned SrcR2 = MI.getOperand(3).getReg();
 430   if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
 431     return;
 432   if (MI.getOperand(2).getImm() > 1)
 433     return;
 434   LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
 435   LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
 436   MachineInstr *NewMI = nullptr;
 437   // Make ADD instruction for two registers writing to LEA's destination
 438   if (SrcR1 != 0 && SrcR2 != 0) {
 439     const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
 440     const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1);
 441     NewMI =
 442         BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
 443     LLVM_DEBUG(NewMI->dump(););
 444   }
 445   // Make ADD instruction for immediate
 446   if (MI.getOperand(4).getImm() != 0) {
 447     const MCInstrDesc &ADDri =
 448         TII->get(getADDriFromLEA(Opcode, MI.getOperand(4)));
 449     const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
 450     NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
 451                 .add(SrcR)
 452                 .addImm(MI.getOperand(4).getImm());
 453     LLVM_DEBUG(NewMI->dump(););
 454   }
 455   if (NewMI) {
 456     MFI->erase(I);
 457     I = NewMI;
 458   }
 459 }
 460
 461 MachineInstr *
 462 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
 463                                         MachineFunction::iterator MFI) {
 464
 465   const int LEAOpcode = MI.getOpcode();
 466   if (!isLEA(LEAOpcode))
 467     return nullptr;
 468
 469   const MachineOperand &Dst = MI.getOperand(0);
 470   const MachineOperand &Base = MI.getOperand(1);
 471   const MachineOperand &Scale = MI.getOperand(2);
 472   const MachineOperand &Index = MI.getOperand(3);
 473   const MachineOperand &Offset = MI.getOperand(4);
 474   const MachineOperand &Segment = MI.getOperand(5);
 475
 476   if (!(TII->isThreeOperandsLEA(MI) ||
 477         hasInefficientLEABaseReg(Base, Index)) ||
 478       !TII->isSafeToClobberEFLAGS(*MFI, MI) ||
 479       Segment.getReg() != X86::NoRegister)
 480     return nullptr;
 481
 482   unsigned int DstR = Dst.getReg();
 483   unsigned int BaseR = Base.getReg();
 484   unsigned int IndexR = Index.getReg();
 485   unsigned SSDstR =
 486       (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
 487   bool IsScale1 = Scale.getImm() == 1;
 488   bool IsInefficientBase = isInefficientLEAReg(BaseR);
 489   bool IsInefficientIndex = isInefficientLEAReg(IndexR);
 490
 491   // Skip these cases since it takes more than 2 instructions
 492   // to replace the LEA instruction.
 493   if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
 494     return nullptr;
 495   if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
 496       (IsInefficientIndex || !IsScale1))
 497     return nullptr;
 498
 499   const DebugLoc DL = MI.getDebugLoc();
 500   const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
 501   const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
 502
 503   LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
 504   LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
 505
 506   // First try to replace LEA with one or two (for the 3-op LEA case)
 507   // add instructions:
 508   // 1.lea (%base,%index,1), %base => add %index,%base
 509   // 2.lea (%base,%index,1), %index => add %base,%index
 510   if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
 511     const MachineOperand &Src = DstR == BaseR ? Index : Base;
 512     MachineInstr *NewMI =
 513         BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
 514     LLVM_DEBUG(NewMI->dump(););
 515     // Create ADD instruction for the Offset in case of 3-Ops LEA.
 516     if (hasLEAOffset(Offset)) {
 517       NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
 518       LLVM_DEBUG(NewMI->dump(););
 519     }
 520     return NewMI;
 521   }
 522   // If the base is inefficient try switching the index and base operands,
 523   // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
 524   // lea offset(%base,%index,scale),%dst =>
 525   // lea (%base,%index,scale); add offset,%dst
 526   if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
 527     MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
 528                               .add(Dst)
 529                               .add(IsInefficientBase ? Index : Base)
 530                               .add(Scale)
 531                               .add(IsInefficientBase ? Base : Index)
 532                               .addImm(0)
 533                               .add(Segment);
 534     LLVM_DEBUG(NewMI->dump(););
 535     // Create ADD instruction for the Offset in case of 3-Ops LEA.
 536     if (hasLEAOffset(Offset)) {
 537       NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
 538       LLVM_DEBUG(NewMI->dump(););
 539     }
 540     return NewMI;
 541   }
 542   // Handle the rest of the cases with inefficient base register:
 543   assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
 544   assert(IsInefficientBase && "efficient base should be handled already!");
 545
 546   // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
 547   if (IsScale1 && !hasLEAOffset(Offset)) {
 548     bool BIK = Base.isKill() && BaseR != IndexR;
 549     TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, BIK);
 550     LLVM_DEBUG(MI.getPrevNode()->dump(););
 551
 552     MachineInstr *NewMI =
 553         BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
 554     LLVM_DEBUG(NewMI->dump(););
 555     return NewMI;
 556   }
 557   // lea offset(%base,%index,scale), %dst =>
 558   // lea offset( ,%index,scale), %dst; add %base,%dst
 559   MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
 560                             .add(Dst)
 561                             .addReg(0)
 562                             .add(Scale)
 563                             .add(Index)
 564                             .add(Offset)
 565                             .add(Segment);
 566   LLVM_DEBUG(NewMI->dump(););
 567
 568   NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
 569   LLVM_DEBUG(NewMI->dump(););
 570   return NewMI;
 571 }
 572
 573 bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
 574                                      MachineFunction::iterator MFI) {
 575
 576   for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
 577     if (OptIncDec)
 578       if (fixupIncDec(I, MFI))
 579         continue;
 580
 581     if (OptLEA) {
 582       if (MF.getSubtarget<X86Subtarget>().slowLEA())
 583         processInstructionForSLM(I, MFI);
 584
 585       else {
 586         if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) {
 587           if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) {
 588             MFI->erase(I);
 589             I = NewMI;
 590           }
 591         } else
 592           processInstruction(I, MFI);
 593       }
 594     }
 595   }
 596   return false;
 597 }