llvm/lib/Target/RISCV/CMakeLists.txt

   1 add_llvm_component_group(RISCV)
   2
   3 set(LLVM_TARGET_DEFINITIONS RISCV.td)
   4
   5 tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
   6 tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
   7 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
   8 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
   9 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
  10 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
  11 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
  12 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
  13 tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
  14 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
  15 tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
  16 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
  17
  18 set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
  19 tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
  20 tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
  21               -combiners="RISCVO0PreLegalizerCombiner")
  22 tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
  23               -combiners="RISCVPreLegalizerCombiner")
  24 tablegen(LLVM RISCVGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
  25               -combiners="RISCVPostLegalizerCombiner")
  26
  27 add_public_tablegen_target(RISCVCommonTableGen)
  28
  29 add_llvm_target(RISCVCodeGen
  30   RISCVAsmPrinter.cpp
  31   RISCVCodeGenPrepare.cpp
  32   RISCVDeadRegisterDefinitions.cpp
  33   RISCVMakeCompressible.cpp
  34   RISCVExpandAtomicPseudoInsts.cpp
  35   RISCVExpandPseudoInsts.cpp
  36   RISCVFoldMasks.cpp
  37   RISCVFrameLowering.cpp
  38   RISCVGatherScatterLowering.cpp
  39   RISCVInsertVSETVLI.cpp
  40   RISCVInsertReadWriteCSR.cpp
  41   RISCVInstrInfo.cpp
  42   RISCVISelDAGToDAG.cpp
  43   RISCVISelLowering.cpp
  44   RISCVMachineFunctionInfo.cpp
  45   RISCVMacroFusion.cpp
  46   RISCVMergeBaseOffset.cpp
  47   RISCVOptWInstrs.cpp
  48   RISCVPostRAExpandPseudoInsts.cpp
  49   RISCVRedundantCopyElimination.cpp
  50   RISCVMoveMerger.cpp
  51   RISCVPushPopOptimizer.cpp
  52   RISCVRegisterInfo.cpp
  53   RISCVRVVInitUndef.cpp
  54   RISCVSubtarget.cpp
  55   RISCVTargetMachine.cpp
  56   RISCVTargetObjectFile.cpp
  57   RISCVTargetTransformInfo.cpp
  58   GISel/RISCVCallLowering.cpp
  59   GISel/RISCVInstructionSelector.cpp
  60   GISel/RISCVLegalizerInfo.cpp
  61   GISel/RISCVPostLegalizerCombiner.cpp
  62   GISel/RISCVO0PreLegalizerCombiner.cpp
  63   GISel/RISCVPreLegalizerCombiner.cpp
  64   GISel/RISCVRegisterBankInfo.cpp
  65
  66   LINK_COMPONENTS
  67   Analysis
  68   AsmPrinter
  69   CodeGen
  70   CodeGenTypes
  71   Core
  72   GlobalISel
  73   IPO
  74   MC
  75   RISCVDesc
  76   RISCVInfo
  77   SelectionDAG
  78   Support
  79   Target
  80   TargetParser
  81   TransformUtils
  82
  83   ADD_TO_COMPONENT
  84   RISCV
  85   )
  86
  87 add_subdirectory(AsmParser)
  88 add_subdirectory(Disassembler)
  89 add_subdirectory(MCTargetDesc)
  90 add_subdirectory(MCA)
  91 add_subdirectory(TargetInfo)