llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h

   1 //===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file provides RISC-V specific target descriptions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
  14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
  15
  16 #include "llvm/Config/config.h"
  17 #include "llvm/MC/MCTargetOptions.h"
  18 #include "llvm/Support/DataTypes.h"
  19 #include <memory>
  20
  21 namespace llvm {
  22 class MCAsmBackend;
  23 class MCCodeEmitter;
  24 class MCContext;
  25 class MCInstrInfo;
  26 class MCObjectTargetWriter;
  27 class MCRegisterInfo;
  28 class MCSubtargetInfo;
  29 class Target;
  30
  31 MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
  32                                         MCContext &Ctx);
  33
  34 MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
  35                                     const MCRegisterInfo &MRI,
  36                                     const MCTargetOptions &Options);
  37
  38 std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
  39                                                                  bool Is64Bit);
  40 }
  41
  42 // Defines symbolic names for RISC-V registers.
  43 #define GET_REGINFO_ENUM
  44 #include "RISCVGenRegisterInfo.inc"
  45
  46 // Defines symbolic names for RISC-V instructions.
  47 #define GET_INSTRINFO_ENUM
  48 #define GET_INSTRINFO_MC_HELPER_DECLS
  49 #include "RISCVGenInstrInfo.inc"
  50
  51 #define GET_SUBTARGETINFO_ENUM
  52 #include "RISCVGenSubtargetInfo.inc"
  53
  54 #endif