llvm/lib/Target/RISCV/RISCVFeatures.td

   1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10 // RISC-V subtarget features and instruction predicates.
  11 //===----------------------------------------------------------------------===//
  12
  13 def FeatureStdExtZicsr
  14     : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
  15                        "'zicsr' (CSRs)">;
  16 def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
  17                                 AssemblerPredicate<(all_of FeatureStdExtZicsr),
  18                                 "'Zicsr' (CSRs)">;
  19
  20 def FeatureStdExtM
  21     : SubtargetFeature<"m", "HasStdExtM", "true",
  22                        "'M' (Integer Multiplication and Division)">;
  23 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
  24                            AssemblerPredicate<(all_of FeatureStdExtM),
  25                            "'M' (Integer Multiplication and Division)">;
  26
  27 def FeatureStdExtZmmul
  28     : SubtargetFeature<"zmmul", "HasStdExtZmmul", "true",
  29                        "'Zmmul' (Integer Multiplication)">;
  30
  31 def HasStdExtMOrZmmul
  32     : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
  33                 AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
  34                                    "'M' (Integer Multiplication and Division) or "
  35                                    "'Zmmul' (Integer Multiplication)">;
  36
  37 def FeatureStdExtA
  38     : SubtargetFeature<"a", "HasStdExtA", "true",
  39                        "'A' (Atomic Instructions)">;
  40 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
  41                            AssemblerPredicate<(all_of FeatureStdExtA),
  42                            "'A' (Atomic Instructions)">;
  43
  44 def FeatureStdExtF
  45     : SubtargetFeature<"f", "HasStdExtF", "true",
  46                        "'F' (Single-Precision Floating-Point)",
  47                        [FeatureStdExtZicsr]>;
  48 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
  49                            AssemblerPredicate<(all_of FeatureStdExtF),
  50                            "'F' (Single-Precision Floating-Point)">;
  51
  52 def FeatureStdExtD
  53     : SubtargetFeature<"d", "HasStdExtD", "true",
  54                        "'D' (Double-Precision Floating-Point)",
  55                        [FeatureStdExtF]>;
  56 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
  57                            AssemblerPredicate<(all_of FeatureStdExtD),
  58                            "'D' (Double-Precision Floating-Point)">;
  59
  60 def FeatureStdExtH
  61     : SubtargetFeature<"h", "HasStdExtH", "true",
  62                        "'H' (Hypervisor)">;
  63
  64 def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
  65                            AssemblerPredicate<(all_of FeatureStdExtH),
  66                            "'H' (Hypervisor)">;
  67
  68 def FeatureStdExtZihintpause
  69     : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
  70                        "'Zihintpause' (Pause Hint)">;
  71 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
  72                                      AssemblerPredicate<(all_of FeatureStdExtZihintpause),
  73                                      "'Zihintpause' (Pause Hint)">;
  74
  75 def FeatureStdExtZihintntl
  76     : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true",
  77                        "'Zihintntl' (Non-Temporal Locality Hints)">;
  78 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
  79                                     AssemblerPredicate<(all_of FeatureStdExtZihintntl),
  80                                     "'Zihintntl' (Non-Temporal Locality Hints)">;
  81
  82 def FeatureStdExtZifencei
  83     : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
  84                        "'Zifencei' (fence.i)">;
  85 def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
  86                                    AssemblerPredicate<(all_of FeatureStdExtZifencei),
  87                                    "'Zifencei' (fence.i)">;
  88
  89 def FeatureStdExtZicntr
  90     : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
  91                        "'Zicntr' (Base Counters and Timers)",
  92                        [FeatureStdExtZicsr]>;
  93
  94 def FeatureStdExtZihpm
  95     : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true",
  96                        "'Zihpm' (Hardware Performance Counters)",
  97                        [FeatureStdExtZicsr]>;
  98
  99 def FeatureStdExtZfhmin
 100     : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
 101                        "'Zfhmin' (Half-Precision Floating-Point Minimal)",
 102                        [FeatureStdExtF]>;
 103 def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
 104                              AssemblerPredicate<(all_of FeatureStdExtZfhmin),
 105                              "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
 106
 107 def FeatureStdExtZfh
 108     : SubtargetFeature<"zfh", "HasStdExtZfh", "true",
 109                        "'Zfh' (Half-Precision Floating-Point)",
 110                        [FeatureStdExtF]>;
 111 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
 112                              AssemblerPredicate<(all_of FeatureStdExtZfh),
 113                              "'Zfh' (Half-Precision Floating-Point)">;
 114 def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
 115
 116 def HasStdExtZfhOrZfhmin
 117     : Predicate<"Subtarget->hasStdExtZfhOrZfhmin()">,
 118                 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin),
 119                                    "'Zfh' (Half-Precision Floating-Point) or "
 120                                    "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
 121
 122 def FeatureStdExtZfinx
 123     : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
 124                        "'Zfinx' (Float in Integer)",
 125                        [FeatureStdExtZicsr]>;
 126 def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
 127                                AssemblerPredicate<(all_of FeatureStdExtZfinx),
 128                                "'Zfinx' (Float in Integer)">;
 129
 130 def FeatureStdExtZdinx
 131     : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true",
 132                        "'Zdinx' (Double in Integer)",
 133                        [FeatureStdExtZfinx]>;
 134 def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
 135                                AssemblerPredicate<(all_of FeatureStdExtZdinx),
 136                                "'Zdinx' (Double in Integer)">;
 137
 138 def FeatureStdExtZhinxmin
 139     : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true",
 140                        "'Zhinxmin' (Half Float in Integer Minimal)",
 141                        [FeatureStdExtZfinx]>;
 142 def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
 143                                   AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
 144                                   "'Zhinxmin' (Half Float in Integer Minimal)">;
 145
 146 def FeatureStdExtZhinx
 147     : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
 148                        "'Zhinx' (Half Float in Integer)",
 149                        [FeatureStdExtZfinx]>;
 150 def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
 151                                AssemblerPredicate<(all_of FeatureStdExtZhinx),
 152                                "'Zhinx' (Half Float in Integer)">;
 153 def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
 154
 155 def HasStdExtZhinxOrZhinxmin
 156     : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
 157                 AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
 158                                    "'Zhinx' (Half Float in Integer) or "
 159                                    "'Zhinxmin' (Half Float in Integer Minimal)">;
 160
 161 def FeatureStdExtZfa
 162     : SubtargetFeature<"zfa", "HasStdExtZfa", "true",
 163                        "'Zfa' (Additional Floating-Point)",
 164                        [FeatureStdExtF]>;
 165 def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
 166                              AssemblerPredicate<(all_of FeatureStdExtZfa),
 167                              "'Zfa' (Additional Floating-Point)">;
 168
 169 def FeatureStdExtC
 170     : SubtargetFeature<"c", "HasStdExtC", "true",
 171                        "'C' (Compressed Instructions)">;
 172 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
 173                            AssemblerPredicate<(all_of FeatureStdExtC),
 174                            "'C' (Compressed Instructions)">;
 175
 176 def FeatureStdExtZba
 177     : SubtargetFeature<"zba", "HasStdExtZba", "true",
 178                        "'Zba' (Address Generation Instructions)">;
 179 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
 180                              AssemblerPredicate<(all_of FeatureStdExtZba),
 181                              "'Zba' (Address Generation Instructions)">;
 182 def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
 183
 184 def FeatureStdExtZbb
 185     : SubtargetFeature<"zbb", "HasStdExtZbb", "true",
 186                        "'Zbb' (Basic Bit-Manipulation)">;
 187 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
 188                              AssemblerPredicate<(all_of FeatureStdExtZbb),
 189                              "'Zbb' (Basic Bit-Manipulation)">;
 190
 191 def FeatureStdExtZbc
 192     : SubtargetFeature<"zbc", "HasStdExtZbc", "true",
 193                        "'Zbc' (Carry-Less Multiplication)">;
 194 def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
 195                              AssemblerPredicate<(all_of FeatureStdExtZbc),
 196                              "'Zbc' (Carry-Less Multiplication)">;
 197
 198 def FeatureStdExtZbs
 199     : SubtargetFeature<"zbs", "HasStdExtZbs", "true",
 200                        "'Zbs' (Single-Bit Instructions)">;
 201 def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
 202                              AssemblerPredicate<(all_of FeatureStdExtZbs),
 203                              "'Zbs' (Single-Bit Instructions)">;
 204
 205 def FeatureStdExtZbkb
 206     : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
 207                        "'Zbkb' (Bitmanip instructions for Cryptography)">;
 208 def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
 209                              AssemblerPredicate<(all_of FeatureStdExtZbkb),
 210                              "'Zbkb' (Bitmanip instructions for Cryptography)">;
 211
 212 def FeatureStdExtZbkx
 213     : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
 214                        "'Zbkx' (Crossbar permutation instructions)">;
 215 def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
 216                              AssemblerPredicate<(all_of FeatureStdExtZbkx),
 217                              "'Zbkx' (Crossbar permutation instructions)">;
 218
 219 def HasStdExtZbbOrZbkb
 220     : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
 221                 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
 222                                    "'Zbb' (Basic Bit-Manipulation) or "
 223                                    "'Zbkb' (Bitmanip instructions for Cryptography)">;
 224
 225 // The Carry-less multiply subextension for cryptography is a subset of basic
 226 // carry-less multiply subextension. The former should be enabled if the latter
 227 // is enabled.
 228 def FeatureStdExtZbkc
 229     : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
 230                        "'Zbkc' (Carry-less multiply instructions for "
 231                        "Cryptography)">;
 232 def HasStdExtZbkc
 233     : Predicate<"Subtarget->hasStdExtZbkc()">,
 234                 AssemblerPredicate<(all_of FeatureStdExtZbkc),
 235                 "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
 236
 237 def HasStdExtZbcOrZbkc
 238     : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
 239                 AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
 240                                    "'Zbc' (Carry-Less Multiplication) or "
 241                                    "'Zbkc' (Carry-less multiply instructions "
 242                                    "for Cryptography)">;
 243
 244 def FeatureStdExtZknd
 245     : SubtargetFeature<"zknd", "HasStdExtZknd", "true",
 246                        "'Zknd' (NIST Suite: AES Decryption)">;
 247 def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
 248                               AssemblerPredicate<(all_of FeatureStdExtZknd),
 249                               "'Zknd' (NIST Suite: AES Decryption)">;
 250
 251 def FeatureStdExtZkne
 252     : SubtargetFeature<"zkne", "HasStdExtZkne", "true",
 253                        "'Zkne' (NIST Suite: AES Encryption)">;
 254 def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
 255                               AssemblerPredicate<(all_of FeatureStdExtZkne),
 256                               "'Zkne' (NIST Suite: AES Encryption)">;
 257
 258 // Some instructions belong to both Zknd and Zkne subextensions.
 259 // They should be enabled if either has been specified.
 260 def HasStdExtZkndOrZkne
 261     : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
 262                 AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
 263                                    "'Zknd' (NIST Suite: AES Decryption) or "
 264                                    "'Zkne' (NIST Suite: AES Encryption)">;
 265
 266 def FeatureStdExtZknh
 267     : SubtargetFeature<"zknh", "HasStdExtZknh", "true",
 268                        "'Zknh' (NIST Suite: Hash Function Instructions)">;
 269 def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
 270                              AssemblerPredicate<(all_of FeatureStdExtZknh),
 271                              "'Zknh' (NIST Suite: Hash Function Instructions)">;
 272
 273 def FeatureStdExtZksed
 274     : SubtargetFeature<"zksed", "HasStdExtZksed", "true",
 275                        "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
 276 def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
 277                              AssemblerPredicate<(all_of FeatureStdExtZksed),
 278                              "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
 279
 280 def FeatureStdExtZksh
 281     : SubtargetFeature<"zksh", "HasStdExtZksh", "true",
 282                        "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
 283 def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
 284                               AssemblerPredicate<(all_of FeatureStdExtZksh),
 285                               "'Zksh' (ShangMi Suite: SM3 Hash Function "
 286                               "Instructions)">;
 287
 288 def FeatureStdExtZkr
 289     : SubtargetFeature<"zkr", "HasStdExtZkr", "true",
 290                        "'Zkr' (Entropy Source Extension)">;
 291 def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
 292                              AssemblerPredicate<(all_of FeatureStdExtZkr),
 293                              "'Zkr' (Entropy Source Extension)">;
 294
 295 def FeatureStdExtZkn
 296     : SubtargetFeature<"zkn", "HasStdExtZkn", "true",
 297                        "'Zkn' (NIST Algorithm Suite)",
 298                        [FeatureStdExtZbkb,
 299                         FeatureStdExtZbkc,
 300                         FeatureStdExtZbkx,
 301                         FeatureStdExtZkne,
 302                         FeatureStdExtZknd,
 303                         FeatureStdExtZknh]>;
 304
 305 def FeatureStdExtZks
 306     : SubtargetFeature<"zks", "HasStdExtZks", "true",
 307                        "'Zks' (ShangMi Algorithm Suite)",
 308                        [FeatureStdExtZbkb,
 309                         FeatureStdExtZbkc,
 310                         FeatureStdExtZbkx,
 311                         FeatureStdExtZksed,
 312                         FeatureStdExtZksh]>;
 313
 314 def FeatureStdExtZkt
 315     : SubtargetFeature<"zkt", "HasStdExtZkt", "true",
 316                        "'Zkt' (Data Independent Execution Latency)">;
 317
 318 def FeatureStdExtZk
 319     : SubtargetFeature<"zk", "HasStdExtZk", "true",
 320                        "'Zk' (Standard scalar cryptography extension)",
 321                        [FeatureStdExtZkn,
 322                         FeatureStdExtZkr,
 323                         FeatureStdExtZkt]>;
 324
 325 def FeatureStdExtZca
 326     : SubtargetFeature<"zca", "HasStdExtZca", "true",
 327                        "'Zca' (part of the C extension, excluding compressed "
 328                        "floating point loads/stores)">;
 329
 330 def HasStdExtCOrZca
 331     : Predicate<"Subtarget->hasStdExtCOrZca()">,
 332                 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
 333                                    "'C' (Compressed Instructions) or "
 334                                    "'Zca' (part of the C extension, excluding "
 335                                    "compressed floating point loads/stores)">;
 336
 337 def FeatureStdExtZcb
 338     : SubtargetFeature<"zcb", "HasStdExtZcb", "true",
 339                        "'Zcb' (Compressed basic bit manipulation instructions)",
 340                        [FeatureStdExtZca]>;
 341 def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
 342                              AssemblerPredicate<(all_of FeatureStdExtZcb),
 343                              "'Zcb' (Compressed basic bit manipulation instructions)">;
 344
 345 def FeatureStdExtZcd
 346     : SubtargetFeature<"zcd", "HasStdExtZcd", "true",
 347                        "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
 348                        [FeatureStdExtZca]>;
 349
 350 def HasStdExtCOrZcd
 351     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
 352                 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
 353                                    "'C' (Compressed Instructions) or "
 354                                    "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
 355
 356 def FeatureStdExtZcf
 357     : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
 358                        "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
 359                        [FeatureStdExtZca]>;
 360
 361 def FeatureStdExtZcmp
 362     : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
 363                        "'Zcmp' (sequenced instuctions for code-size reduction)",
 364                        [FeatureStdExtZca]>;
 365 def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
 366                                AssemblerPredicate<(all_of FeatureStdExtZcmp),
 367                                "'Zcmp' (sequenced instuctions for code-size reduction)">;
 368
 369 def FeatureStdExtZcmt
 370     : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
 371                        "'Zcmt' (table jump instuctions for code-size reduction)",
 372                        [FeatureStdExtZca, FeatureStdExtZicsr]>;
 373 def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
 374                            AssemblerPredicate<(all_of FeatureStdExtZcmt),
 375                            "'Zcmt' (table jump instuctions for code-size reduction)">;
 376
 377 def FeatureStdExtZce
 378     : SubtargetFeature<"zce", "HasStdExtZce", "true",
 379                        "'Zce' (Compressed extensions for microcontrollers)",
 380                        [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
 381                         FeatureStdExtZcmt]>;
 382
 383 def HasStdExtCOrZcfOrZce
 384     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
 385                 "Subtarget->hasStdExtZce()">,
 386                 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
 387                                            FeatureStdExtZce),
 388                                    "'C' (Compressed Instructions) or "
 389                                    "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
 390
 391 def FeatureNoRVCHints
 392     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
 393                        "Disable RVC Hint Instructions.">;
 394 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
 395                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
 396                                       "RVC Hint Instructions">;
 397
 398 def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
 399                                            "'Zvl' (Minimum Vector Length) 32">;
 400
 401 foreach i = { 6-16 } in {
 402   defvar I = !shl(1, i);
 403   def FeatureStdExtZvl#I#b :
 404       SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
 405                        "'Zvl' (Minimum Vector Length) "#I,
 406                        [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
 407 }
 408
 409 def FeatureStdExtZve32x
 410     : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
 411                        "'Zve32x' (Vector Extensions for Embedded Processors "
 412                        "with maximal 32 EEW)",
 413                        [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
 414
 415 def FeatureStdExtZve32f
 416     : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
 417                        "'Zve32f' (Vector Extensions for Embedded Processors "
 418                        "with maximal 32 EEW and F extension)",
 419                        [FeatureStdExtZve32x, FeatureStdExtF]>;
 420
 421 def FeatureStdExtZve64x
 422     : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
 423                        "'Zve64x' (Vector Extensions for Embedded Processors "
 424                        "with maximal 64 EEW)",
 425                        [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
 426
 427 def FeatureStdExtZve64f
 428     : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
 429                        "'Zve64f' (Vector Extensions for Embedded Processors "
 430                        "with maximal 64 EEW and F extension)",
 431                        [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
 432
 433 def FeatureStdExtZve64d
 434     : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
 435                        "'Zve64d' (Vector Extensions for Embedded Processors "
 436                        "with maximal 64 EEW, F and D extension)",
 437                        [FeatureStdExtZve64f, FeatureStdExtD]>;
 438
 439 def FeatureStdExtV
 440     : SubtargetFeature<"v", "HasStdExtV", "true",
 441                        "'V' (Vector Extension for Application Processors)",
 442                        [FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
 443
 444 def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
 445       AssemblerPredicate<
 446           (any_of FeatureStdExtZve32x),
 447           "'V' (Vector Extension for Application Processors), 'Zve32x' or "
 448           "'Zve64x' (Vector Extensions for Embedded Processors)">;
 449 def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
 450       AssemblerPredicate<
 451           (any_of FeatureStdExtZve64x),
 452           "'V' (Vector Extension for Application Processors) or 'Zve64x' "
 453           "(Vector Extensions for Embedded Processors)">;
 454 def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
 455       AssemblerPredicate<
 456           (any_of FeatureStdExtZve32f),
 457           "'V' (Vector Extension for Application Processors), 'Zve32f', "
 458           "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
 459
 460 def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;
 461
 462 def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;
 463
 464 def FeatureStdExtZfbfmin
 465     : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true",
 466                        "'Zfbfmin' (Scalar BF16 Converts)",
 467                        [FeatureStdExtF]>;
 468 def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
 469                                  AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
 470                                  "'Zfbfmin' (Scalar BF16 Converts)">;
 471
 472 def FeatureStdExtZvfbfmin
 473     : SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true",
 474                        "'Zvbfmin' (Vector BF16 Converts)",
 475                        [FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;
 476 def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
 477                                   AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
 478                                   "'Zvfbfmin' (Vector BF16 Converts)">;
 479
 480 def FeatureStdExtZvfbfwma
 481     : SubtargetFeature<"experimental-zvfbfwma", "HasStdExtZvfbfwma", "true",
 482                        "'Zvfbfwma' (Vector BF16 widening mul-add)",
 483                        [FeatureStdExtZvfbfmin]>;
 484 def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
 485                                   AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
 486                                   "'Zvfbfwma' (Vector BF16 widening mul-add)">;
 487
 488 def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">;
 489
 490 def FeatureStdExtZvfh
 491     : SubtargetFeature<"zvfh", "HasStdExtZvfh", "true",
 492                        "'Zvfh' (Vector Half-Precision Floating-Point)",
 493                        [FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
 494
 495 def FeatureStdExtZvfhmin
 496     : SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true",
 497                        "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
 498                        [FeatureStdExtZve32f]>;
 499
 500 def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
 501
 502 def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,
 503       AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
 504                          "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
 505                          "'Zvfh' (Vector Half-Precision Floating-Point)">;
 506
 507 def HasStdExtZfhOrZvfh
 508     : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
 509                 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
 510                                    "'Zfh' (Half-Precision Floating-Point) or "
 511                                    "'Zvfh' (Vector Half-Precision Floating-Point)">;
 512
 513 def FeatureStdExtZicbom
 514     : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
 515                        "'Zicbom' (Cache-Block Management Instructions)">;
 516 def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
 517                                 AssemblerPredicate<(all_of FeatureStdExtZicbom),
 518                                 "'Zicbom' (Cache-Block Management Instructions)">;
 519
 520 def FeatureStdExtZicboz
 521     : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
 522                        "'Zicboz' (Cache-Block Zero Instructions)">;
 523 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
 524                                 AssemblerPredicate<(all_of FeatureStdExtZicboz),
 525                                 "'Zicboz' (Cache-Block Zero Instructions)">;
 526
 527 def FeatureStdExtZicbop
 528     : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
 529                        "'Zicbop' (Cache-Block Prefetch Instructions)">;
 530 def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
 531                                 AssemblerPredicate<(all_of FeatureStdExtZicbop),
 532                                 "'Zicbop' (Cache-Block Prefetch Instructions)">;
 533
 534 def FeatureStdExtSvnapot
 535     : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
 536                        "'Svnapot' (NAPOT Translation Contiguity)">;
 537
 538 def FeatureStdExtSvpbmt
 539     : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
 540                        "'Svpbmt' (Page-Based Memory Types)">;
 541
 542 def FeatureStdExtSvinval
 543     : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
 544                        "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
 545 def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
 546                                 AssemblerPredicate<(all_of FeatureStdExtSvinval),
 547                                 "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
 548
 549 def FeatureStdExtZtso
 550     : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
 551                        "'Ztso' (Memory Model - Total Store Order)">;
 552 def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
 553                               AssemblerPredicate<(all_of FeatureStdExtZtso),
 554                               "'Ztso' (Memory Model - Total Store Order)">;
 555 def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
 556
 557 def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
 558                                           "'Zawrs' (Wait on Reservation Set)">;
 559 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
 560                                AssemblerPredicate<(all_of FeatureStdExtZawrs),
 561                                "'Zawrs' (Wait on Reservation Set)">;
 562
 563 def FeatureStdExtZvkb
 564     : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
 565                        "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
 566 def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
 567                               AssemblerPredicate<(all_of FeatureStdExtZvkb),
 568                               "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
 569
 570 def FeatureStdExtZvbb
 571     : SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
 572                        "'Zvbb' (Vector basic bit-manipulation instructions.)",
 573                        [FeatureStdExtZvkb]>;
 574 def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
 575                               AssemblerPredicate<(all_of FeatureStdExtZvbb),
 576                               "'Zvbb' (Vector basic bit-manipulation instructions.)">;
 577
 578 def FeatureStdExtZvbc
 579     : SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
 580                        "'Zvbc' (Vector Carryless Multiplication)">;
 581 def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
 582                               AssemblerPredicate<(all_of FeatureStdExtZvbc),
 583                               "'Zvbc' (Vector Carryless Multiplication)">;
 584
 585 def FeatureStdExtZvkg
 586     : SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true",
 587                        "'Zvkg' (Vector GCM instructions for Cryptography)">;
 588 def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
 589                               AssemblerPredicate<(all_of FeatureStdExtZvkg),
 590                               "'Zvkg' (Vector GCM instructions for Cryptography)">;
 591
 592 def FeatureStdExtZvkned
 593     : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
 594                        "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
 595 def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
 596                                 AssemblerPredicate<(all_of FeatureStdExtZvkned),
 597                                 "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
 598
 599 def FeatureStdExtZvknha
 600     : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
 601                        "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
 602
 603 def FeatureStdExtZvknhb
 604     : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
 605                        "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
 606                        [FeatureStdExtZvknha]>;
 607 def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
 608                                 AssemblerPredicate<(all_of FeatureStdExtZvknha),
 609                                 "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
 610
 611 def FeatureStdExtZvksed
 612     : SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
 613                        "'Zvksed' (SM4 Block Cipher Instructions)">;
 614 def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
 615                                 AssemblerPredicate<(all_of FeatureStdExtZvksed),
 616                                 "'Zvksed' (SM4 Block Cipher Instructions)">;
 617
 618 def FeatureStdExtZvksh
 619     : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
 620                        "'Zvksh' (SM3 Hash Function Instructions)">;
 621 def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
 622                                AssemblerPredicate<(all_of FeatureStdExtZvksh),
 623                                "'Zvksh' (SM3 Hash Function Instructions)">;
 624
 625 def FeatureStdExtZvkt
 626     : SubtargetFeature<"experimental-zvkt", "HasStdExtZvkt", "true",
 627                        "'Zvkt' (Vector Data-Independent Execution Latency)">;
 628
 629 // Zvk short-hand extensions
 630
 631 def FeatureStdExtZvkn
 632     : SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
 633                        "This extension is shorthand for the following set of "
 634                        "other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.",
 635                        [FeatureStdExtZvkned, FeatureStdExtZvknhb,
 636                         FeatureStdExtZvkb, FeatureStdExtZvkt]>;
 637
 638 def FeatureStdExtZvknc
 639     : SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
 640                        "This extension is shorthand for the following set of "
 641                        "other extensions: Zvkn and Zvbc.",
 642                        [FeatureStdExtZvkn, FeatureStdExtZvbc]>;
 643
 644 def FeatureStdExtZvkng
 645     : SubtargetFeature<"experimental-zvkng", "HasStdExtZvkng", "true",
 646                        "This extension is shorthand for the following set of "
 647                        "other extensions: Zvkn and Zvkg.",
 648                        [FeatureStdExtZvkn, FeatureStdExtZvkg]>;
 649
 650 def FeatureStdExtZvks
 651     : SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
 652                        "This extension is shorthand for the following set of "
 653                        "other extensions: Zvksed, Zvksh, Zvkb and Zvkt.",
 654                        [FeatureStdExtZvksed, FeatureStdExtZvksh,
 655                         FeatureStdExtZvkb, FeatureStdExtZvkt]>;
 656
 657 def FeatureStdExtZvksc
 658     : SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",
 659                        "This extension is shorthand for the following set of "
 660                        "other extensions: Zvks and Zvbc.",
 661                        [FeatureStdExtZvks, FeatureStdExtZvbc]>;
 662
 663 def FeatureStdExtZvksg
 664     : SubtargetFeature<"experimental-zvksg", "HasStdExtZvksg", "true",
 665                        "This extension is shorthand for the following set of "
 666                        "other extensions: Zvks and Zvkg.",
 667                        [FeatureStdExtZvks, FeatureStdExtZvkg]>;
 668
 669 def FeatureStdExtZicfilp
 670     : SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true",
 671                        "'Zicfilp' (Landing pad)">;
 672 def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
 673                                  AssemblerPredicate<(all_of FeatureStdExtZicfilp),
 674                                  "'Zicfilp' (Landing pad)">;
 675
 676 def FeatureStdExtZicond
 677     : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
 678                        "'Zicond' (Integer Conditional Operations)">;
 679 def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
 680                                 AssemblerPredicate<(all_of FeatureStdExtZicond),
 681                                 "'Zicond' (Integer Conditional Operations)">;
 682
 683 def FeatureStdExtSmaia
 684     : SubtargetFeature<"experimental-smaia", "HasStdExtSmaia", "true",
 685                        "'Smaia' (Smaia encompasses all added CSRs and all "
 686                        "modifications to interrupt response behavior that the "
 687                        "AIA specifies for a hart, over all privilege levels.)",
 688                        []>;
 689
 690 def FeatureStdExtSsaia
 691     : SubtargetFeature<"experimental-ssaia", "HasStdExtSsaia", "true",
 692                        "'Ssaia' (Ssaia is essentially the same as Smaia except "
 693                        "excluding the machine-level CSRs and behavior not "
 694                        "directly visible to supervisor level.)", []>;
 695
 696 def HasHalfFPLoadStoreMove
 697     : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
 698                 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
 699                                     FeatureStdExtZfbfmin),
 700                                     "'Zfh' (Half-Precision Floating-Point) or "
 701                                     "'Zfhmin' (Half-Precision Floating-Point Minimal) or "
 702                                     "'Zfbfmin' (Scalar BF16 Converts)">;
 703
 704 def FeatureStdExtZacas
 705     : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true",
 706                        "'Zacas' (Atomic Compare-And-Swap Instructions)">;
 707 def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
 708                                AssemblerPredicate<(all_of FeatureStdExtZacas),
 709                                "'Zacas' (Atomic Compare-And-Swap Instructions)">;
 710
 711 //===----------------------------------------------------------------------===//
 712 // Vendor extensions
 713 //===----------------------------------------------------------------------===//
 714
 715 def FeatureVendorXVentanaCondOps
 716     : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
 717                        "'XVentanaCondOps' (Ventana Conditional Ops)">;
 718 def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
 719                                 AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
 720                                 "'XVentanaCondOps' (Ventana Conditional Ops)">;
 721
 722 def FeatureVendorXTHeadBa
 723     : SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true",
 724                        "'xtheadba' (T-Head address calculation instructions)">;
 725 def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
 726                                   AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
 727                                   "'xtheadba' (T-Head address calculation instructions)">;
 728
 729 def FeatureVendorXTHeadBb
 730     : SubtargetFeature<"xtheadbb", "HasVendorXTHeadBb", "true",
 731                        "'xtheadbb' (T-Head basic bit-manipulation instructions)">;
 732 def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
 733                                   AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
 734                                   "'xtheadbb' (T-Head basic bit-manipulation instructions)">;
 735
 736 def FeatureVendorXTHeadBs
 737     : SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true",
 738                        "'xtheadbs' (T-Head single-bit instructions)">;
 739 def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
 740                                   AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
 741                                   "'xtheadbs' (T-Head single-bit instructions)">;
 742
 743 def FeatureVendorXTHeadCondMov
 744     : SubtargetFeature<"xtheadcondmov", "HasVendorXTHeadCondMov", "true",
 745                        "'xtheadcondmov' (T-Head conditional move instructions)">;
 746 def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,
 747                                        AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),
 748                                        "'xtheadcondmov' (T-Head conditional move instructions)">;
 749
 750 def FeatureVendorXTHeadCmo
 751     : SubtargetFeature<"xtheadcmo", "HasVendorXTHeadCmo", "true",
 752                        "'xtheadcmo' (T-Head cache management instructions)">;
 753 def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
 754                                    AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
 755                                    "'xtheadcmo' (T-Head cache management instructions)">;
 756
 757 def FeatureVendorXTHeadFMemIdx
 758     : SubtargetFeature<"xtheadfmemidx", "HasVendorXTHeadFMemIdx", "true",
 759                        "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
 760                        [FeatureStdExtF]>;
 761 def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
 762                                        AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),
 763                                        "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;
 764
 765 def FeatureVendorXTHeadMac
 766     : SubtargetFeature<"xtheadmac", "HasVendorXTHeadMac", "true",
 767                        "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
 768 def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
 769                                    AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
 770                                    "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
 771
 772 def FeatureVendorXTHeadMemIdx
 773     : SubtargetFeature<"xtheadmemidx", "HasVendorXTHeadMemIdx", "true",
 774                        "'xtheadmemidx' (T-Head Indexed Memory Operations)">;
 775 def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,
 776                                       AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),
 777                                       "'xtheadmemidx' (T-Head Indexed Memory Operations)">;
 778
 779 def FeatureVendorXTHeadMemPair
 780     : SubtargetFeature<"xtheadmempair", "HasVendorXTHeadMemPair", "true",
 781                        "'xtheadmempair' (T-Head two-GPR Memory Operations)">;
 782 def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,
 783                                     AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),
 784                                     "'xtheadmempair' (T-Head two-GPR Memory Operations)">;
 785
 786 def FeatureVendorXTHeadSync
 787     : SubtargetFeature<"xtheadsync", "HasVendorXTHeadSync", "true",
 788                        "'xtheadsync' (T-Head multicore synchronization instructions)">;
 789 def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,
 790                                     AssemblerPredicate<(all_of FeatureVendorXTHeadSync),
 791                                     "'xtheadsync' (T-Head multicore synchronization instructions)">;
 792
 793 def FeatureVendorXTHeadVdot
 794     : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
 795                        "'xtheadvdot' (T-Head Vector Extensions for Dot)",
 796                        [FeatureStdExtV]>;
 797 def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
 798                                     AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
 799                                     "'xtheadvdot' (T-Head Vector Extensions for Dot)">;
 800
 801 def FeatureVendorXSfvcp
 802     : SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true",
 803                        "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
 804                        [FeatureStdExtZve32x]>;
 805 def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
 806                                 AssemblerPredicate<(all_of FeatureVendorXSfvcp),
 807                                 "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
 808
 809 def FeatureVendorXSfcie
 810     : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
 811                        "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
 812 def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
 813                         AssemblerPredicate<(all_of FeatureVendorXSfcie),
 814                         "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
 815
 816 def FeatureVendorXSfvqmaccdod
 817     : SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true",
 818                        "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
 819                        [FeatureStdExtZve32x]>;
 820 def HasVendorXSfvqmaccdod : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">,
 821                          AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod),
 822                          "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">;
 823
 824 def FeatureVendorXSfvqmaccqoq
 825     : SubtargetFeature<"xsfvqmaccqoq", "HasVendorXSfvqmaccqoq", "true",
 826                        "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
 827                        [FeatureStdExtZve32x]>;
 828 def HasVendorXSfvqmaccqoq : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">,
 829                          AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq),
 830                          "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">;
 831
 832 def FeatureVendorXCVbitmanip
 833     : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
 834                        "'XCVbitmanip' (CORE-V Bit Manipulation)">;
 835 def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
 836                                 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
 837                                 "'XCVbitmanip' (CORE-V Bit Manipulation)">;
 838
 839 def FeatureVendorXCVmac
 840     : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
 841                        "'XCVmac' (CORE-V Multiply-Accumulate)">;
 842 def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
 843                                 AssemblerPredicate<(all_of FeatureVendorXCVmac),
 844                                 "'XCVmac' (CORE-V Multiply-Accumulate)">;
 845
 846 def FeatureVendorXCValu
 847     : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
 848                        "'XCValu' (CORE-V ALU Operations)">;
 849 def HasVendorXCValu : Predicate<"Subtarget->hasVendorXCValu()">,
 850                                 AssemblerPredicate<(all_of FeatureVendorXCValu),
 851                                 "'XCValu' (CORE-V ALU Operations)">;
 852
 853 def FeatureVendorXCVsimd
 854     : SubtargetFeature<"xcvsimd", "HasVendorXCvsimd", "true",
 855                        "'XCVsimd' (CORE-V SIMD ALU)">;
 856 def HasVendorXCVsimd
 857     : Predicate<"Subtarget->hasVendorXCVsimd()">,
 858                 AssemblerPredicate<(any_of FeatureVendorXCVsimd),
 859                 "'XCVsimd' (CORE-V SIMD ALU)">;
 860
 861 def FeatureVendorXCVbi
 862     : SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true",
 863                        "'XCVbi' (CORE-V Immediate Branching)">;
 864 def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">,
 865                                AssemblerPredicate<(all_of FeatureVendorXCVbi),
 866                                "'XCVbi' (CORE-V Immediate Branching)">;
 867
 868 //===----------------------------------------------------------------------===//
 869 // LLVM specific features and extensions
 870 //===----------------------------------------------------------------------===//
 871
 872 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 873 // tuning CPU names.
 874 def Feature32Bit
 875     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
 876 def Feature64Bit
 877     : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
 878 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
 879                        AssemblerPredicate<(all_of Feature64Bit),
 880                                          "RV64I Base Instruction Set">;
 881 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
 882                        AssemblerPredicate<(all_of (not Feature64Bit)),
 883                                           "RV32I Base Instruction Set">;
 884
 885 defvar RV32 = DefaultMode;
 886 def RV64           : HwMode<"+64bit", [IsRV64]>;
 887
 888 def FeatureRVE
 889     : SubtargetFeature<"e", "IsRVE", "true",
 890                        "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
 891 def IsRVE : Predicate<"Subtarget->isRVE()">,
 892                         AssemblerPredicate<(all_of FeatureRVE)>;
 893
 894 def FeatureRelax
 895     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
 896                        "Enable Linker relaxation.">;
 897
 898 foreach i = {1-31} in
 899   def FeatureReserveX#i :
 900       SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
 901                        "true", "Reserve X"#i>;
 902
 903 def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
 904                                           "true", "Enable save/restore.">;
 905
 906 def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
 907                                           "EnableSeqCstTrailingFence",
 908                                           "true",
 909                                           "Enable trailing fence for seq-cst store.">;
 910
 911 def FeatureUnalignedScalarMem
 912    : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
 913                       "true", "Has reasonably performant unaligned scalar "
 914                       "loads and stores">;
 915
 916 def FeatureUnalignedVectorMem
 917    : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",
 918                       "true", "Has reasonably performant unaligned vector "
 919                       "loads and stores">;
 920
 921 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
 922     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 923
 924 def TuneNoOptimizedZeroStrideLoad
 925    : SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
 926                       "false", "Hasn't optimized (perform fewer memory operations)"
 927                       "zero-stride vector load">;
 928
 929 // Some vector hardware implementations do not process all VLEN bits in parallel
 930 // and instead split over multiple cycles. DLEN refers to the datapath width
 931 // that can be done in parallel.
 932 def TuneDLenFactor2
 933    : SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
 934                       "Vector unit DLEN(data path width) is half of VLEN">;
 935
 936 def TuneLUIADDIFusion
 937     : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
 938                        "true", "Enable LUI+ADDI macrofusion">;
 939
 940 def TuneNoDefaultUnroll
 941     : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
 942                        "Disable default unroll preference.">;
 943
 944 // SiFive 7 is able to fuse integer ALU operations with a preceding branch
 945 // instruction.
 946 def TuneShortForwardBranchOpt
 947     : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt",
 948                        "true", "Enable short forward branch optimization">;
 949 def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">;
 950 def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
 951
 952 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
 953                                    "SiFive 7-Series processors",
 954                                    [TuneNoDefaultUnroll,
 955                                     TuneShortForwardBranchOpt]>;
 956
 957 def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
 958                                          "Ventana-Veyron Series processors",
 959                                          [TuneLUIADDIFusion]>;
 960
 961 // Assume that lock-free native-width atomics are available, even if the target
 962 // and operating system combination would not usually provide them. The user
 963 // is responsible for providing any necessary __sync implementations. Code
 964 // built with this feature is not ABI-compatible with code built without this
 965 // feature, if atomic variables are exposed across the ABI boundary.
 966 def FeatureForcedAtomics : SubtargetFeature<
 967     "forced-atomics", "HasForcedAtomics", "true",
 968     "Assume that lock-free native-width atomics are available">;
 969 def HasAtomicLdSt
 970     : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
 971
 972 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
 973     "AllowTaggedGlobals",
 974     "true", "Use an instruction sequence for taking the address of a global "
 975     "that allows a memory tag in the upper address bits">;