llvm/lib/Target/RISCV/RISCVProcessors.td

   1 //===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10 // RISC-V processors supported.
  11 //===----------------------------------------------------------------------===//
  12
  13 class RISCVTuneInfo {
  14   bits<8> PrefFunctionAlignment = 1;
  15   bits<8> PrefLoopAlignment = 1;
  16 }
  17
  18 def RISCVTuneInfoTable : GenericTable {
  19   let FilterClass = "RISCVTuneInfo";
  20   let CppTypeName = "RISCVTuneInfo";
  21   let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment"];
  22 }
  23
  24 def getRISCVTuneInfo : SearchIndex {
  25   let Table = RISCVTuneInfoTable;
  26   let Key = ["Name"];
  27 }
  28
  29 class GenericTuneInfo: RISCVTuneInfo;
  30
  31 class RISCVProcessorModel<string n,
  32                           SchedMachineModel m,
  33                           list<SubtargetFeature> f,
  34                           list<SubtargetFeature> tunef = [],
  35                           string default_march = "">
  36       :  ProcessorModel<n, m, f, tunef> {
  37   string DefaultMarch = default_march;
  38 }
  39
  40 class RISCVTuneProcessorModel<string n,
  41                               SchedMachineModel m,
  42                               list<SubtargetFeature> tunef = [],
  43                               list<SubtargetFeature> f = []>
  44       : ProcessorModel<n, m, f,tunef>;
  45
  46 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
  47                                        NoSchedModel,
  48                                        [Feature32Bit]>,
  49                    GenericTuneInfo;
  50 def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
  51                                        NoSchedModel,
  52                                        [Feature64Bit]>,
  53                    GenericTuneInfo;
  54 // Support generic for compatibility with other targets. The triple will be used
  55 // to change to the appropriate rv32/rv64 version.
  56 def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo;
  57
  58 def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
  59                                       RocketModel,
  60                                       [Feature32Bit,
  61                                        FeatureStdExtZifencei,
  62                                        FeatureStdExtZicsr]>;
  63 def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
  64                                       RocketModel,
  65                                       [Feature64Bit,
  66                                        FeatureStdExtZifencei,
  67                                        FeatureStdExtZicsr]>;
  68 def ROCKET : RISCVTuneProcessorModel<"rocket",
  69                                      RocketModel>;
  70
  71 def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
  72                                        SiFive7Model,
  73                                        [TuneSiFive7]>;
  74
  75 def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
  76                                      RocketModel,
  77                                      [Feature32Bit,
  78                                       FeatureStdExtZicsr,
  79                                       FeatureStdExtZifencei,
  80                                       FeatureStdExtM,
  81                                       FeatureStdExtC]>;
  82
  83 def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
  84                                      RocketModel,
  85                                      [Feature32Bit,
  86                                       FeatureStdExtZicsr,
  87                                       FeatureStdExtZifencei,
  88                                       FeatureStdExtM,
  89                                       FeatureStdExtA,
  90                                       FeatureStdExtC]>;
  91
  92 def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
  93                                      RocketModel,
  94                                      [Feature32Bit,
  95                                       FeatureStdExtZifencei,
  96                                       FeatureStdExtM,
  97                                       FeatureStdExtA,
  98                                       FeatureStdExtF,
  99                                       FeatureStdExtC]>;
 100
 101 def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
 102                                      RocketModel,
 103                                      [Feature32Bit,
 104                                       FeatureStdExtZifencei,
 105                                       FeatureStdExtZicsr,
 106                                       FeatureStdExtM,
 107                                       FeatureStdExtA,
 108                                       FeatureStdExtC]>;
 109
 110 def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
 111                                      RocketModel,
 112                                      [Feature32Bit,
 113                                       FeatureStdExtZifencei,
 114                                       FeatureStdExtM,
 115                                       FeatureStdExtA,
 116                                       FeatureStdExtF,
 117                                       FeatureStdExtC]>;
 118
 119 def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
 120                                      SiFive7Model,
 121                                      [Feature32Bit,
 122                                       FeatureStdExtZifencei,
 123                                       FeatureStdExtM,
 124                                       FeatureStdExtA,
 125                                       FeatureStdExtF,
 126                                       FeatureStdExtC],
 127                                      [TuneSiFive7]>;
 128
 129 def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
 130                                      RocketModel,
 131                                      [Feature64Bit,
 132                                       FeatureStdExtZicsr,
 133                                       FeatureStdExtZifencei,
 134                                       FeatureStdExtM,
 135                                       FeatureStdExtA,
 136                                       FeatureStdExtC]>;
 137
 138 def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
 139                                      RocketModel,
 140                                      [Feature64Bit,
 141                                       FeatureStdExtZicsr,
 142                                       FeatureStdExtZifencei,
 143                                       FeatureStdExtM,
 144                                       FeatureStdExtA,
 145                                       FeatureStdExtC]>;
 146
 147 def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
 148                                       RocketModel,
 149                                       [Feature64Bit,
 150                                        FeatureStdExtZifencei,
 151                                        FeatureStdExtM,
 152                                        FeatureStdExtA,
 153                                        FeatureStdExtF,
 154                                        FeatureStdExtD,
 155                                        FeatureStdExtC]>;
 156
 157 def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
 158                                      SiFive7Model,
 159                                      [Feature64Bit,
 160                                       FeatureStdExtZifencei,
 161                                       FeatureStdExtM,
 162                                       FeatureStdExtA,
 163                                       FeatureStdExtF,
 164                                       FeatureStdExtD,
 165                                       FeatureStdExtC,
 166                                       FeatureStdExtZihintpause,
 167                                       FeatureVendorXSfcie],
 168                                      [TuneSiFive7]>;
 169
 170 def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
 171                                      RocketModel,
 172                                      [Feature64Bit,
 173                                       FeatureStdExtZifencei,
 174                                       FeatureStdExtM,
 175                                       FeatureStdExtA,
 176                                       FeatureStdExtF,
 177                                       FeatureStdExtD,
 178                                       FeatureStdExtC]>;
 179
 180 def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
 181                                      SiFive7Model,
 182                                      [Feature64Bit,
 183                                       FeatureStdExtZifencei,
 184                                       FeatureStdExtM,
 185                                       FeatureStdExtA,
 186                                       FeatureStdExtF,
 187                                       FeatureStdExtD,
 188                                       FeatureStdExtC],
 189                                      [TuneSiFive7]>;
 190
 191 def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
 192                                       [Feature64Bit,
 193                                        FeatureStdExtZifencei,
 194                                        FeatureStdExtM,
 195                                        FeatureStdExtA,
 196                                        FeatureStdExtF,
 197                                        FeatureStdExtD,
 198                                        FeatureStdExtC,
 199                                        FeatureStdExtV,
 200                                        FeatureStdExtZvl512b,
 201                                        FeatureStdExtZfh,
 202                                        FeatureStdExtZvfh,
 203                                        FeatureStdExtZba,
 204                                        FeatureStdExtZbb],
 205                                       [TuneSiFive7,
 206                                        TuneDLenFactor2]>;
 207
 208 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
 209                                               SyntacoreSCR1Model,
 210                                               [Feature32Bit,
 211                                                FeatureStdExtZicsr,
 212                                                FeatureStdExtZifencei,
 213                                                FeatureStdExtC],
 214                                               [TuneNoDefaultUnroll]>;
 215
 216 def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
 217                                              SyntacoreSCR1Model,
 218                                              [Feature32Bit,
 219                                               FeatureStdExtZicsr,
 220                                               FeatureStdExtZifencei,
 221                                               FeatureStdExtM,
 222                                               FeatureStdExtC],
 223                                              [TuneNoDefaultUnroll]>;
 224
 225 def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
 226                                             NoSchedModel,
 227                                             [Feature64Bit,
 228                                              FeatureStdExtZifencei,
 229                                              FeatureStdExtZicsr,
 230                                              FeatureStdExtZicntr,
 231                                              FeatureStdExtZihpm,
 232                                              FeatureStdExtZihintpause,
 233                                              FeatureStdExtM,
 234                                              FeatureStdExtA,
 235                                              FeatureStdExtF,
 236                                              FeatureStdExtD,
 237                                              FeatureStdExtC,
 238                                              FeatureStdExtZba,
 239                                              FeatureStdExtZbb,
 240                                              FeatureStdExtZbc,
 241                                              FeatureStdExtZbs,
 242                                              FeatureStdExtZicbom,
 243                                              FeatureStdExtZicbop,
 244                                              FeatureStdExtZicboz,
 245                                              FeatureVendorXVentanaCondOps],
 246                                              [TuneVentanaVeyron]>;