llvm/test/MC/AMDGPU/gfx10_err_pos.s

   1 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
   2
   3 //==============================================================================
   4 // operands are not valid for this GPU or mode
   5
   6 image_atomic_add v252, v2, s[8:15]
   7 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
   8 // CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15]
   9 // CHECK-NEXT:{{^}}^
  10
  11 //==============================================================================
  12 // duplicate data format
  13
  14 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]
  15 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate data format
  16 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]
  17 // CHECK-NEXT:{{^}}                                                                                ^
  18
  19 //==============================================================================
  20 // duplicate numeric format
  21
  22 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT]
  23 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate numeric format
  24 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT]
  25 // CHECK-NEXT:{{^}}                                                                                 ^
  26
  27 //==============================================================================
  28 // expected ')' in parentheses expression
  29
  30 v_bfe_u32 v0, 1+(100, v1, v2
  31 // CHECK: :[[#@LINE-1]]:21: error: expected ')'
  32 // CHECK-NEXT:{{^}}v_bfe_u32 v0, 1+(100, v1, v2
  33 // CHECK-NEXT:{{^}}                    ^
  34
  35 //==============================================================================
  36 // expected a 12-bit signed offset
  37
  38 global_load_dword v1, v[3:4] off, offset:-4097
  39 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 12-bit signed offset
  40 // CHECK-NEXT:{{^}}global_load_dword v1, v[3:4] off, offset:-4097
  41 // CHECK-NEXT:{{^}}                                  ^
  42
  43 scratch_load_dword v0, v1, off offset:-2049 glc slc
  44 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 12-bit signed offset
  45 // CHECK-NEXT:{{^}}scratch_load_dword v0, v1, off offset:-2049 glc slc
  46 // CHECK-NEXT:{{^}}                               ^
  47
  48 //==============================================================================
  49 // expected a 16-bit signed jump offset
  50
  51 s_branch 0x10000
  52 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 16-bit signed jump offset
  53 // CHECK-NEXT:{{^}}s_branch 0x10000
  54 // CHECK-NEXT:{{^}}         ^
  55
  56 //==============================================================================
  57 // expected a 2-bit lane id
  58
  59 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)
  60 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit lane id
  61 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)
  62 // CHECK-NEXT:{{^}}                                                ^
  63
  64 //==============================================================================
  65 // expected a 20-bit unsigned offset
  66
  67 s_atc_probe_buffer 0x1, s[8:11], -1
  68 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset
  69 // CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], -1
  70 // CHECK-NEXT:{{^}}                                 ^
  71
  72 s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
  73 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset
  74 // CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
  75 // CHECK-NEXT:{{^}}                                 ^
  76
  77 s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF
  78 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset
  79 // CHECK-NEXT:{{^}}s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF
  80 // CHECK-NEXT:{{^}}                                 ^
  81
  82 //==============================================================================
  83 // expected a 21-bit signed offset
  84
  85 s_atc_probe 0x7, s[4:5], 0x1FFFFF
  86 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 21-bit signed offset
  87 // CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], 0x1FFFFF
  88 // CHECK-NEXT:{{^}}                         ^
  89
  90 s_atomic_swap s5, s[2:3], 0x1FFFFF
  91 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 21-bit signed offset
  92 // CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF
  93 // CHECK-NEXT:{{^}}                          ^
  94
  95 //==============================================================================
  96 // expected a 2-bit value
  97
  98 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0
  99 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit value
 100 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0
 101 // CHECK-NEXT:{{^}}                                      ^
 102
 103 v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0
 104 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit value
 105 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0
 106 // CHECK-NEXT:{{^}}                                  ^
 107
 108 //==============================================================================
 109 // expected a 3-bit value
 110
 111 v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
 112 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 3-bit value
 113 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
 114 // CHECK-NEXT:{{^}}                           ^
 115
 116 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
 117 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 3-bit value
 118 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
 119 // CHECK-NEXT:{{^}}                                 ^
 120
 121 //==============================================================================
 122 // expected a 5-character mask
 123
 124 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
 125 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 5-character mask
 126 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
 127 // CHECK-NEXT:{{^}}                                                   ^
 128
 129 //==============================================================================
 130 // expected a closing parentheses
 131
 132 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3
 133 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses
 134 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3
 135 // CHECK-NEXT:{{^}}                                                          ^
 136
 137 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)
 138 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses
 139 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)
 140 // CHECK-NEXT:{{^}}                                                          ^
 141
 142 //==============================================================================
 143 // expected a closing parenthesis
 144
 145 s_sendmsg sendmsg(2, 2, 0, 0)
 146 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parenthesis
 147 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 0, 0)
 148 // CHECK-NEXT:{{^}}                         ^
 149
 150 s_waitcnt vmcnt(0
 151 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parenthesis
 152 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0
 153 // CHECK-NEXT:{{^}}                 ^
 154
 155 //==============================================================================
 156 // expected a closing square bracket
 157
 158 s_mov_b32 s1, s[0 1
 159 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 160 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 1
 161 // CHECK-NEXT:{{^}}                  ^
 162
 163 s_mov_b32 s1, s[0 s0
 164 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 165 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 s0
 166 // CHECK-NEXT:{{^}}                  ^
 167
 168 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8]
 169 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 170 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8]
 171 // CHECK-NEXT:{{^}}                                                                                                    ^
 172
 173 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT
 174 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 175 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT
 176 // CHECK-NEXT:{{^}}                                                                                ^
 177
 178 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1
 179 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 180 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1
 181 // CHECK-NEXT:{{^}}                                          ^
 182
 183 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1,
 184 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 185 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1,
 186 // CHECK-NEXT:{{^}}                                         ^
 187
 188 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[
 189 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 190 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[
 191 // CHECK-NEXT:{{^}}                                         ^
 192
 193 v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
 194 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 195 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
 196 // CHECK-NEXT:{{^}}                                       ^
 197
 198 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
 199 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 200 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
 201 // CHECK-NEXT:{{^}}                                          ^
 202
 203 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0
 204 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 205 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0
 206 // CHECK-NEXT:{{^}}                                       ^
 207
 208 //==============================================================================
 209 // expected a colon
 210
 211 ds_swizzle_b32 v8, v2 offset
 212 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a colon
 213 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset
 214 // CHECK-NEXT:{{^}}                            ^
 215
 216 ds_swizzle_b32 v8, v2 offset-
 217 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a colon
 218 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset-
 219 // CHECK-NEXT:{{^}}                            ^
 220
 221 //==============================================================================
 222 // expected a comma
 223
 224 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM
 225 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 226 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM
 227 // CHECK-NEXT:{{^}}                                              ^
 228
 229 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)
 230 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 231 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)
 232 // CHECK-NEXT:{{^}}                                                       ^
 233
 234 s_setreg_b32  hwreg(1,2 3), s2
 235 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 236 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(1,2 3), s2
 237 // CHECK-NEXT:{{^}}                        ^
 238
 239 v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
 240 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 241 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
 242 // CHECK-NEXT:{{^}}                                  ^
 243
 244 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
 245 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 246 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
 247 // CHECK-NEXT:{{^}}                                        ^
 248
 249 v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0
 250 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 251 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0
 252 // CHECK-NEXT:{{^}}                                   ^
 253
 254 //==============================================================================
 255 // expected a comma or a closing parenthesis
 256
 257 s_setreg_b32  hwreg(1 2,3), s2
 258 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing parenthesis
 259 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(1 2,3), s2
 260 // CHECK-NEXT:{{^}}                      ^
 261
 262 //==============================================================================
 263 // expected a comma or a closing square bracket
 264
 265 s_mov_b64 s[10:11], [s0
 266 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket
 267 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0
 268 // CHECK-NEXT:{{^}}                       ^
 269
 270 s_mov_b64 s[10:11], [s0,s1
 271 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket
 272 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s1
 273 // CHECK-NEXT:{{^}}                          ^
 274
 275 image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
 276 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket
 277 // CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
 278 // CHECK-NEXT:{{^}}                                       ^
 279
 280 image_load_mip v[253:255], [v255, v254
 281 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket
 282 // CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254
 283 // CHECK-NEXT:{{^}}                                      ^
 284
 285 //==============================================================================
 286 // expected a counter name
 287
 288 s_waitcnt vmcnt(0) & expcnt(0) & 1
 289 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
 290 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & 1
 291 // CHECK-NEXT:{{^}}                                 ^
 292
 293 s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)&
 294 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
 295 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)&
 296 // CHECK-NEXT:{{^}}                                            ^
 297
 298 s_waitcnt vmcnt(0) & expcnt(0) 1
 299 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
 300 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) 1
 301 // CHECK-NEXT:{{^}}                               ^
 302
 303 s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0),
 304 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
 305 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0),
 306 // CHECK-NEXT:{{^}}                                          ^
 307
 308 //==============================================================================
 309 // expected a format string
 310
 311 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[]
 312 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a format string
 313 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[]
 314 // CHECK-NEXT:{{^}}                                                             ^
 315
 316 //==============================================================================
 317 // expected a left parenthesis
 318
 319 s_waitcnt vmcnt(0) & expcnt(0) & x
 320 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis
 321 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & x
 322 // CHECK-NEXT:{{^}}                                  ^
 323
 324 //==============================================================================
 325 // expected a left square bracket
 326
 327 v_pk_add_u16 v1, v2, v3 op_sel:
 328 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left square bracket
 329 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:
 330 // CHECK-NEXT:{{^}}                               ^
 331
 332 //==============================================================================
 333 // expected a register
 334
 335 image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
 336 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register
 337 // CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
 338 // CHECK-NEXT:{{^}}                            ^
 339
 340 image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
 341 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register
 342 // CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
 343 // CHECK-NEXT:{{^}}                            ^
 344
 345 //==============================================================================
 346 // expected a register or a list of registers
 347
 348 s_mov_b32 s1, [s0, 1
 349 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register or a list of registers
 350 // CHECK-NEXT:{{^}}s_mov_b32 s1, [s0, 1
 351 // CHECK-NEXT:{{^}}                   ^
 352
 353 //==============================================================================
 354 // expected a single 32-bit register
 355
 356 s_mov_b64 s[10:11], [s0,s[2:3]]
 357 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a single 32-bit register
 358 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s[2:3]]
 359 // CHECK-NEXT:{{^}}                        ^
 360
 361 //==============================================================================
 362 // expected a string
 363
 364 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)
 365 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a string
 366 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)
 367 // CHECK-NEXT:{{^}}                                                   ^
 368
 369 //==============================================================================
 370 // expected a swizzle mode
 371
 372 ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
 373 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a swizzle mode
 374 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
 375 // CHECK-NEXT:{{^}}                                     ^
 376
 377 //==============================================================================
 378 // expected absolute expression
 379
 380 s_waitcnt vmcnt(x)
 381 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 382 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(x)
 383 // CHECK-NEXT:{{^}}                ^
 384
 385 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]
 386 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 387 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]
 388 // CHECK-NEXT:{{^}}                                                         ^
 389
 390 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52
 391 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 392 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52
 393 // CHECK-NEXT:{{^}}                                                             ^
 394
 395 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
 396 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 397 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
 398 // CHECK-NEXT:{{^}}                                                            ^
 399
 400 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
 401 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 402 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
 403 // CHECK-NEXT:{{^}}                                 ^
 404
 405 v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0
 406 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 407 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0
 408 // CHECK-NEXT:{{^}}                                  ^
 409
 410 v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0
 411 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 412 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0
 413 // CHECK-NEXT:{{^}}                               ^
 414
 415 //==============================================================================
 416 // expected a message name or an absolute expression
 417
 418 s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)
 419 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a message name or an absolute expression
 420 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)
 421 // CHECK-NEXT:{{^}}                  ^
 422
 423 //==============================================================================
 424 // expected a register name or an absolute expression
 425
 426 s_setreg_b32  hwreg(HW_REG_WRONG), s2
 427 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register name or an absolute expression
 428 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(HW_REG_WRONG), s2
 429 // CHECK-NEXT:{{^}}                    ^
 430
 431 //==============================================================================
 432 // expected a sendmsg macro or an absolute expression
 433
 434 s_sendmsg undef
 435 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a sendmsg macro or an absolute expression
 436 // CHECK-NEXT:{{^}}s_sendmsg undef
 437 // CHECK-NEXT:{{^}}          ^
 438
 439 //==============================================================================
 440 // expected a swizzle macro or an absolute expression
 441
 442 ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
 443 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a swizzle macro or an absolute expression
 444 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
 445 // CHECK-NEXT:{{^}}                             ^
 446
 447 //==============================================================================
 448 // expected a hwreg macro or an absolute expression
 449
 450 s_setreg_b32 undef, s2
 451 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a hwreg macro or an absolute expression
 452 // CHECK-NEXT:{{^}}s_setreg_b32 undef, s2
 453 // CHECK-NEXT:{{^}}             ^
 454
 455 //==============================================================================
 456 // expected an 11-bit unsigned offset
 457
 458 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
 459 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 11-bit unsigned offset
 460 // CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
 461 // CHECK-NEXT:{{^}}                                       ^
 462
 463 //==============================================================================
 464 // expected an absolute expression
 465
 466 v_ceil_f32 v1, abs(u)
 467 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression
 468 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(u)
 469 // CHECK-NEXT:{{^}}                   ^
 470
 471 v_ceil_f32 v1, neg(u)
 472 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression
 473 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(u)
 474 // CHECK-NEXT:{{^}}                   ^
 475
 476 v_ceil_f32 v1, |u|
 477 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression
 478 // CHECK-NEXT:{{^}}v_ceil_f32 v1, |u|
 479 // CHECK-NEXT:{{^}}                ^
 480
 481 v_mov_b32_sdwa v1, sext(u)
 482 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression
 483 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, sext(u)
 484 // CHECK-NEXT:{{^}}                        ^
 485
 486 //==============================================================================
 487 // expected an identifier
 488
 489 v_mov_b32_sdwa v5, v1 dst_sel:
 490 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an identifier
 491 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:
 492 // CHECK-NEXT:{{^}}                              ^
 493
 494 v_mov_b32_sdwa v5, v1 dst_sel:0
 495 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an identifier
 496 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:0
 497 // CHECK-NEXT:{{^}}                              ^
 498
 499 v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]
 500 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an identifier
 501 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]
 502 // CHECK-NEXT:{{^}}                                               ^
 503
 504 //==============================================================================
 505 // expected an opening square bracket
 506
 507 v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
 508 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an opening square bracket
 509 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
 510 // CHECK-NEXT:{{^}}                          ^
 511
 512 v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0
 513 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an opening square bracket
 514 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0
 515 // CHECK-NEXT:{{^}}                               ^
 516
 517 //==============================================================================
 518 // expected an operation name or an absolute expression
 519
 520 s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 521 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an operation name or an absolute expression
 522 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 523 // CHECK-NEXT:{{^}}                          ^
 524
 525 //==============================================================================
 526 // failed parsing operand.
 527
 528 v_ceil_f16 v0, abs(neg(1))
 529 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand.
 530 // CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1))
 531 // CHECK-NEXT:{{^}}                   ^
 532
 533 //==============================================================================
 534 // first register index should not exceed second index
 535
 536 s_mov_b64 s[10:11], s[1:0]
 537 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: first register index should not exceed second index
 538 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], s[1:0]
 539 // CHECK-NEXT:{{^}}                      ^
 540
 541 //==============================================================================
 542 // group size must be a power of two
 543
 544 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
 545 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two
 546 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
 547 // CHECK-NEXT:{{^}}                                               ^
 548
 549 ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
 550 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two
 551 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
 552 // CHECK-NEXT:{{^}}                                             ^
 553
 554 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
 555 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two
 556 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
 557 // CHECK-NEXT:{{^}}                                          ^
 558
 559 //==============================================================================
 560 // group size must be in the interval [1,16]
 561
 562 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)
 563 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be in the interval [1,16]
 564 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)
 565 // CHECK-NEXT:{{^}}                                          ^
 566
 567 //==============================================================================
 568 // group size must be in the interval [2,32]
 569
 570 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)
 571 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be in the interval [2,32]
 572 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)
 573 // CHECK-NEXT:{{^}}                                               ^
 574
 575 //==============================================================================
 576 // image address size does not match dim and a16
 577
 578 image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
 579 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: image address size does not match dim and a16
 580 // CHECK-NEXT:{{^}}image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
 581 // CHECK-NEXT:{{^}}^
 582
 583 //==============================================================================
 584 // image data size does not match dmask, d16 and tfe
 585
 586 image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
 587 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: image data size does not match dmask, d16 and tfe
 588 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
 589 // CHECK-NEXT:{{^}}^
 590
 591 //==============================================================================
 592 // instruction must use glc
 593
 594 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047
 595 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must use glc
 596 // CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047
 597 // CHECK-NEXT:{{^}}^
 598
 599 //==============================================================================
 600 // instruction not supported on this GPU
 601
 602 s_cbranch_join 1
 603 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 604 // CHECK-NEXT:{{^}}s_cbranch_join 1
 605 // CHECK-NEXT:{{^}}^
 606
 607 //==============================================================================
 608 // invalid bit offset: only 5-bit values are legal
 609
 610 s_getreg_b32  s2, hwreg(3,32,32)
 611 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid bit offset: only 5-bit values are legal
 612 // CHECK-NEXT:{{^}}s_getreg_b32  s2, hwreg(3,32,32)
 613 // CHECK-NEXT:{{^}}                          ^
 614
 615 //==============================================================================
 616 // invalid bitfield width: only values from 1 to 32 are legal
 617
 618 s_setreg_b32  hwreg(3,0,33), s2
 619 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid bitfield width: only values from 1 to 32 are legal
 620 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(3,0,33), s2
 621 // CHECK-NEXT:{{^}}                        ^
 622
 623 //==============================================================================
 624 // invalid code of hardware register: only 6-bit values are legal
 625
 626 s_setreg_b32  hwreg(0x40), s2
 627 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid code of hardware register: only 6-bit values are legal
 628 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(0x40), s2
 629 // CHECK-NEXT:{{^}}                    ^
 630
 631 //==============================================================================
 632 // invalid counter name x
 633
 634 s_waitcnt vmcnt(0) & expcnt(0) x(0)
 635 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid counter name x
 636 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) x(0)
 637 // CHECK-NEXT:{{^}}                               ^
 638
 639 //==============================================================================
 640 // invalid dim value
 641
 642 image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
 643 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value
 644 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
 645 // CHECK-NEXT:{{^}}                                            ^
 646
 647 image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
 648 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value
 649 // CHECK-NEXT:{{^}}image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
 650 // CHECK-NEXT:{{^}}                                                  ^
 651
 652 image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D
 653 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value
 654 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D
 655 // CHECK-NEXT:{{^}}                                            ^
 656
 657 //==============================================================================
 658 // invalid dst_sel value
 659
 660 v_mov_b32_sdwa v5, v1 dst_sel:WORD
 661 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_sel value
 662 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:WORD
 663 // CHECK-NEXT:{{^}}                              ^
 664
 665 //==============================================================================
 666 // invalid dst_unused value
 667
 668 v_mov_b32_sdwa v5, v1 dst_unused:UNUSED
 669 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value
 670 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_unused:UNUSED
 671 // CHECK-NEXT:{{^}}                                 ^
 672
 673 //==============================================================================
 674 // invalid exp target
 675
 676 exp invalid_target_10 v3, v2, v1, v0
 677 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid exp target
 678 // CHECK-NEXT:{{^}}exp invalid_target_10 v3, v2, v1, v0
 679 // CHECK-NEXT:{{^}}    ^
 680
 681 exp pos00 v3, v2, v1, v0
 682 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid exp target
 683 // CHECK-NEXT:{{^}}exp pos00 v3, v2, v1, v0
 684 // CHECK-NEXT:{{^}}    ^
 685
 686 //==============================================================================
 687 // invalid immediate: only 16-bit values are legal
 688
 689 s_setreg_b32  0x1f803, s2
 690 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid immediate: only 16-bit values are legal
 691 // CHECK-NEXT:{{^}}s_setreg_b32  0x1f803, s2
 692 // CHECK-NEXT:{{^}}              ^
 693
 694 //==============================================================================
 695 // invalid instruction
 696
 697 v_dot_f32_f16 v0, v1, v2
 698 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid instruction
 699 // CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2
 700 // CHECK-NEXT:{{^}}^
 701
 702 //==============================================================================
 703 // invalid interpolation attribute
 704
 705 v_interp_p2_f32 v0, v1, att
 706 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid interpolation attribute
 707 // CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, att
 708 // CHECK-NEXT:{{^}}                        ^
 709
 710 //==============================================================================
 711 // invalid interpolation slot
 712
 713 v_interp_mov_f32 v8, p1, attr0.x
 714 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid interpolation slot
 715 // CHECK-NEXT:{{^}}v_interp_mov_f32 v8, p1, attr0.x
 716 // CHECK-NEXT:{{^}}                     ^
 717
 718 //==============================================================================
 719 // invalid mask
 720
 721 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")
 722 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid mask
 723 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")
 724 // CHECK-NEXT:{{^}}                                                   ^
 725
 726 //==============================================================================
 727 // invalid message id
 728
 729 s_sendmsg sendmsg(-1)
 730 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message id
 731 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(-1)
 732 // CHECK-NEXT:{{^}}                  ^
 733
 734 //==============================================================================
 735 // invalid message stream id
 736
 737 s_sendmsg sendmsg(2, 2, 4)
 738 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message stream id
 739 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 4)
 740 // CHECK-NEXT:{{^}}                        ^
 741
 742 s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)
 743 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message stream id
 744 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)
 745 // CHECK-NEXT:{{^}}                                     ^
 746
 747 //==============================================================================
 748 // invalid mul value.
 749
 750 v_cvt_f64_i32 v[5:6], s1 mul:3
 751 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid mul value.
 752 // CHECK-NEXT:{{^}}v_cvt_f64_i32 v[5:6], s1 mul:3
 753 // CHECK-NEXT:{{^}}                         ^
 754
 755 //==============================================================================
 756 // invalid or missing interpolation attribute channel
 757
 758 v_interp_p2_f32 v0, v1, attr0.q
 759 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or missing interpolation attribute channel
 760 // CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr0.q
 761 // CHECK-NEXT:{{^}}                        ^
 762
 763 //==============================================================================
 764 // invalid or missing interpolation attribute number
 765
 766 v_interp_p2_f32 v7, v1, attr.x
 767 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or missing interpolation attribute number
 768 // CHECK-NEXT:{{^}}v_interp_p2_f32 v7, v1, attr.x
 769 // CHECK-NEXT:{{^}}                        ^
 770
 771 //==============================================================================
 772 // invalid op_sel operand
 773
 774 v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
 775 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
 776 // CHECK-NEXT:{{^}}v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
 777 // CHECK-NEXT:{{^}}                                ^
 778
 779 //==============================================================================
 780 // invalid op_sel value.
 781
 782 v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
 783 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel value.
 784 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
 785 // CHECK-NEXT:{{^}}                                ^
 786
 787 //==============================================================================
 788 // invalid operand (violates constant bus restrictions)
 789
 790 v_ashrrev_i64 v[0:1], 0x100, s[0:1]
 791 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 792 // CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], 0x100, s[0:1]
 793 // CHECK-NEXT:{{^}}                             ^
 794
 795 v_ashrrev_i64 v[0:1], s3, s[0:1]
 796 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 797 // CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], s3, s[0:1]
 798 // CHECK-NEXT:{{^}}                          ^
 799
 800 v_bfe_u32 v0, s1, 0x3039, s2
 801 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 802 // CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, 0x3039, s2
 803 // CHECK-NEXT:{{^}}                          ^
 804
 805 v_bfe_u32 v0, s1, s2, s3
 806 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 807 // CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, s2, s3
 808 // CHECK-NEXT:{{^}}                      ^
 809
 810 v_div_fmas_f32 v5, s3, 0x123, v3
 811 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 812 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, 0x123, v3
 813 // CHECK-NEXT:{{^}}                       ^
 814
 815 v_div_fmas_f32 v5, s3, v3, 0x123
 816 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 817 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, v3, 0x123
 818 // CHECK-NEXT:{{^}}                           ^
 819
 820 v_div_fmas_f32 v5, 0x123, v3, s3
 821 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 822 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, 0x123, v3, s3
 823 // CHECK-NEXT:{{^}}                              ^
 824
 825 v_div_fmas_f32 v5, s3, s4, v3
 826 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 827 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, s4, v3
 828 // CHECK-NEXT:{{^}}                       ^
 829
 830 //==============================================================================
 831 // invalid operand for instruction
 832
 833 buffer_load_dword v[5:6], off, s[8:11], s3 tfe lds
 834 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 835 // CHECK-NEXT:{{^}}buffer_load_dword v[5:6], off, s[8:11], s3 tfe lds
 836 // CHECK-NEXT:{{^}}                                               ^
 837
 838 exp mrt0 0x12345678, v0, v0, v0
 839 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 840 // CHECK-NEXT:{{^}}exp mrt0 0x12345678, v0, v0, v0
 841 // CHECK-NEXT:{{^}}         ^
 842
 843 v_cmp_eq_f32 s[0:1], private_base, s0
 844 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 845 // CHECK-NEXT:{{^}}v_cmp_eq_f32 s[0:1], private_base, s0
 846 // CHECK-NEXT:{{^}}             ^
 847
 848 //==============================================================================
 849 // invalid operation id
 850
 851 s_sendmsg sendmsg(15, -1)
 852 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id
 853 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(15, -1)
 854 // CHECK-NEXT:{{^}}                      ^
 855
 856 //==============================================================================
 857 // invalid or unsupported register size
 858
 859 s_mov_b64 s[0:17], -1
 860 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or unsupported register size
 861 // CHECK-NEXT:{{^}}s_mov_b64 s[0:17], -1
 862 // CHECK-NEXT:{{^}}          ^
 863
 864 //==============================================================================
 865 // invalid register alignment
 866
 867 s_load_dwordx4 s[1:4], s[2:3], s4
 868 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register alignment
 869 // CHECK-NEXT:{{^}}s_load_dwordx4 s[1:4], s[2:3], s4
 870 // CHECK-NEXT:{{^}}               ^
 871
 872 //==============================================================================
 873 // invalid register index
 874
 875 s_mov_b32 s1, s[0:-1]
 876 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register index
 877 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0:-1]
 878 // CHECK-NEXT:{{^}}                  ^
 879
 880 v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]
 881 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register index
 882 // CHECK-NEXT:{{^}}v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]
 883 // CHECK-NEXT:{{^}}                            ^
 884
 885 //==============================================================================
 886 // invalid register name
 887
 888 s_mov_b64 s[10:11], [x0,s1]
 889 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register name
 890 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [x0,s1]
 891 // CHECK-NEXT:{{^}}                     ^
 892
 893 //==============================================================================
 894 // invalid row_share value
 895
 896 v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0
 897 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid row_share value
 898 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0
 899 // CHECK-NEXT:{{^}}                               ^
 900
 901 v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0
 902 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid row_share value
 903 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0
 904 // CHECK-NEXT:{{^}}                               ^
 905
 906 //==============================================================================
 907 // invalid syntax, expected 'neg' modifier
 908
 909 v_ceil_f32 v0, --1
 910 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid syntax, expected 'neg' modifier
 911 // CHECK-NEXT:{{^}}v_ceil_f32 v0, --1
 912 // CHECK-NEXT:{{^}}               ^
 913
 914 //==============================================================================
 915 // lane id must be in the interval [0,group size - 1]
 916
 917 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
 918 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lane id must be in the interval [0,group size - 1]
 919 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
 920 // CHECK-NEXT:{{^}}                                                 ^
 921
 922 //==============================================================================
 923 // lds_direct cannot be used with this instruction
 924
 925 v_ashrrev_i16 v0, lds_direct, v0
 926 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction
 927 // CHECK-NEXT:{{^}}v_ashrrev_i16 v0, lds_direct, v0
 928 // CHECK-NEXT:{{^}}                  ^
 929
 930 v_ashrrev_i16 v0, v1, lds_direct
 931 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction
 932 // CHECK-NEXT:{{^}}v_ashrrev_i16 v0, v1, lds_direct
 933 // CHECK-NEXT:{{^}}                      ^
 934
 935 v_mov_b32_sdwa v1, src_lds_direct dst_sel:DWORD
 936 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction
 937 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, src_lds_direct dst_sel:DWORD
 938 // CHECK-NEXT:{{^}}                   ^
 939
 940 v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD
 941 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction
 942 // CHECK-NEXT:{{^}}v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD
 943 // CHECK-NEXT:{{^}}                       ^
 944
 945 //==============================================================================
 946 // lds_direct may be used as src0 only
 947
 948 v_add_f32 v5, v1, lds_direct
 949 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct may be used as src0 only
 950 // CHECK-NEXT:{{^}}v_add_f32 v5, v1, lds_direct
 951 // CHECK-NEXT:{{^}}                  ^
 952
 953 //==============================================================================
 954 // message does not support operations
 955
 956 s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)
 957 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: message does not support operations
 958 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)
 959 // CHECK-NEXT:{{^}}                                    ^
 960
 961 //==============================================================================
 962 // message operation does not support streams
 963
 964 s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 965 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: message operation does not support streams
 966 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 967 // CHECK-NEXT:{{^}}                                          ^
 968
 969 //==============================================================================
 970 // missing message operation
 971
 972 s_sendmsg sendmsg(MSG_SYSMSG)
 973 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing message operation
 974 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_SYSMSG)
 975 // CHECK-NEXT:{{^}}                  ^
 976
 977 //==============================================================================
 978 // missing register index
 979
 980 s_mov_b64 s[10:11], [s
 981 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing register index
 982 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s
 983 // CHECK-NEXT:{{^}}                      ^
 984
 985 s_mov_b64 s[10:11], [s,s1]
 986 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing register index
 987 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s,s1]
 988 // CHECK-NEXT:{{^}}                      ^
 989
 990 //==============================================================================
 991 // not a valid operand.
 992
 993 s_branch offset:1
 994 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
 995 // CHECK-NEXT:{{^}}s_branch offset:1
 996 // CHECK-NEXT:{{^}}         ^
 997
 998 v_mov_b32 v0, v0 row_bcast:0
 999 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
1000 // CHECK-NEXT:{{^}}v_mov_b32 v0, v0 row_bcast:0
1001 // CHECK-NEXT:{{^}}                 ^
1002
1003 //==============================================================================
1004 // only one unique literal operand is allowed
1005
1006 s_and_b32 s2, 0x12345678, 0x12345679
1007 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1008 // CHECK-NEXT:{{^}}s_and_b32 s2, 0x12345678, 0x12345679
1009 // CHECK-NEXT:{{^}}                          ^
1010
1011 v_add_f64 v[0:1], 1.23456, -abs(1.2345)
1012 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1013 // CHECK-NEXT:{{^}}v_add_f64 v[0:1], 1.23456, -abs(1.2345)
1014 // CHECK-NEXT:{{^}}                                ^
1015
1016 v_min3_i16 v5, 0x5678, 0x5678, 0x5679
1017 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1018 // CHECK-NEXT:{{^}}v_min3_i16 v5, 0x5678, 0x5678, 0x5679
1019 // CHECK-NEXT:{{^}}                               ^
1020
1021 v_pk_add_f16 v1, 25.0, 25.1
1022 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1023 // CHECK-NEXT:{{^}}v_pk_add_f16 v1, 25.0, 25.1
1024 // CHECK-NEXT:{{^}}                       ^
1025
1026 v_fma_mix_f32 v5, 0x7c, 0x7b, 1
1027 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1028 // CHECK-NEXT:{{^}}v_fma_mix_f32 v5, 0x7c, 0x7b, 1
1029 // CHECK-NEXT:{{^}}                        ^
1030
1031 v_pk_add_i16 v5, 0x7c, 0x4000
1032 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1033 // CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x7c, 0x4000
1034 // CHECK-NEXT:{{^}}                       ^
1035
1036 v_pk_add_i16 v5, 0x4400, 0x4000
1037 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1038 // CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x4400, 0x4000
1039 // CHECK-NEXT:{{^}}                         ^
1040
1041 v_bfe_u32 v0, v2, 123, undef
1042 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1043 // CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, 123, undef
1044 // CHECK-NEXT:{{^}}                       ^
1045
1046 v_bfe_u32 v0, v2, undef, 123
1047 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1048 // CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, undef, 123
1049 // CHECK-NEXT:{{^}}                         ^
1050
1051 //==============================================================================
1052 // out of bounds interpolation attribute number
1053
1054 v_interp_p1_f32 v0, v1, attr64.w
1055 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: out of bounds interpolation attribute number
1056 // CHECK-NEXT:{{^}}v_interp_p1_f32 v0, v1, attr64.w
1057 // CHECK-NEXT:{{^}}                        ^
1058
1059 //==============================================================================
1060 // out of range format
1061
1062 tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0
1063 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: out of range format
1064 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0
1065 // CHECK-NEXT:{{^}}                                           ^
1066
1067 //==============================================================================
1068 // register does not fit in the list
1069
1070 s_mov_b64 s[10:11], [exec,exec_lo]
1071 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register does not fit in the list
1072 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec,exec_lo]
1073 // CHECK-NEXT:{{^}}                          ^
1074
1075 s_mov_b64 s[10:11], [exec_lo,exec]
1076 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register does not fit in the list
1077 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec_lo,exec]
1078 // CHECK-NEXT:{{^}}                             ^
1079
1080 //==============================================================================
1081 // register index is out of range
1082
1083 s_add_i32 s106, s0, s1
1084 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
1085 // CHECK-NEXT:{{^}}s_add_i32 s106, s0, s1
1086 // CHECK-NEXT:{{^}}          ^
1087
1088 s_load_dwordx16 s[100:115], s[2:3], s4
1089 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
1090 // CHECK-NEXT:{{^}}s_load_dwordx16 s[100:115], s[2:3], s4
1091 // CHECK-NEXT:{{^}}                ^
1092
1093 s_mov_b32 ttmp16, 0
1094 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
1095 // CHECK-NEXT:{{^}}s_mov_b32 ttmp16, 0
1096 // CHECK-NEXT:{{^}}          ^
1097
1098 v_add_nc_i32 v256, v0, v1
1099 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
1100 // CHECK-NEXT:{{^}}v_add_nc_i32 v256, v0, v1
1101 // CHECK-NEXT:{{^}}             ^
1102
1103 //==============================================================================
1104 // register not available on this GPU
1105
1106 s_and_b32     ttmp9, tma_hi, 0x0000ffff
1107 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
1108 // CHECK-NEXT:{{^}}s_and_b32     ttmp9, tma_hi, 0x0000ffff
1109 // CHECK-NEXT:{{^}}                     ^
1110
1111 s_mov_b32 flat_scratch, -1
1112 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
1113 // CHECK-NEXT:{{^}}s_mov_b32 flat_scratch, -1
1114 // CHECK-NEXT:{{^}}          ^
1115
1116 //==============================================================================
1117 // registers in a list must be of the same kind
1118
1119 s_mov_b64 s[10:11], [a0,v1]
1120 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must be of the same kind
1121 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,v1]
1122 // CHECK-NEXT:{{^}}                        ^
1123
1124 //==============================================================================
1125 // registers in a list must have consecutive indices
1126
1127 s_mov_b64 s[10:11], [a0,a2]
1128 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices
1129 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,a2]
1130 // CHECK-NEXT:{{^}}                        ^
1131
1132 s_mov_b64 s[10:11], [s0,s0]
1133 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices
1134 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s0]
1135 // CHECK-NEXT:{{^}}                        ^
1136
1137 s_mov_b64 s[10:11], [s2,s1]
1138 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices
1139 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s2,s1]
1140 // CHECK-NEXT:{{^}}                        ^
1141
1142 //==============================================================================
1143 // source operand must be a VGPR
1144
1145 v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
1146 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
1147 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
1148 // CHECK-NEXT:{{^}}                       ^
1149
1150 v_movrels_b32_sdwa v0, s0
1151 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
1152 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, s0
1153 // CHECK-NEXT:{{^}}                       ^
1154
1155 v_movrels_b32_sdwa v0, shared_base
1156 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
1157 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, shared_base
1158 // CHECK-NEXT:{{^}}                       ^
1159
1160 //==============================================================================
1161 // specified hardware register is not supported on this GPU
1162
1163 s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)
1164 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: specified hardware register is not supported on this GPU
1165 // CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)
1166 // CHECK-NEXT:{{^}}                       ^
1167
1168 //==============================================================================
1169 // too few operands for instruction
1170
1171 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
1172 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
1173 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
1174 // CHECK-NEXT:{{^}}^
1175
1176 v_add_f32_e64 v0, v1
1177 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
1178 // CHECK-NEXT:{{^}}v_add_f32_e64 v0, v1
1179 // CHECK-NEXT:{{^}}^
1180
1181 buffer_load_dword off, s[8:11], s3
1182 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
1183 // CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3
1184 // CHECK-NEXT:{{^}}^
1185
1186 buffer_load_dword off, s[8:11], s3 offset:1
1187 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
1188 // CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3 offset:1
1189 // CHECK-NEXT:{{^}}^
1190
1191 //==============================================================================
1192 // too large value for expcnt
1193
1194 s_waitcnt expcnt(8)
1195 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for expcnt
1196 // CHECK-NEXT:{{^}}s_waitcnt expcnt(8)
1197 // CHECK-NEXT:{{^}}                 ^
1198
1199 //==============================================================================
1200 // too large value for lgkmcnt
1201
1202 s_waitcnt lgkmcnt(64)
1203 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for lgkmcnt
1204 // CHECK-NEXT:{{^}}s_waitcnt lgkmcnt(64)
1205 // CHECK-NEXT:{{^}}                  ^
1206
1207 //==============================================================================
1208 // too large value for vmcnt
1209
1210 s_waitcnt vmcnt(64)
1211 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for vmcnt
1212 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(64)
1213 // CHECK-NEXT:{{^}}                ^
1214
1215 //==============================================================================
1216 // unknown token in expression
1217
1218 ds_swizzle_b32 v8, v2 offset:
1219 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1220 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:
1221 // CHECK-NEXT:{{^}}                             ^
1222
1223 s_sendmsg sendmsg(1 -)
1224 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1225 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(1 -)
1226 // CHECK-NEXT:{{^}}                     ^
1227
1228 tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0
1229 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1230 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0
1231 // CHECK-NEXT:{{^}}                                                    ^
1232
1233 tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0
1234 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1235 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0
1236 // CHECK-NEXT:{{^}}                                                   ^
1237
1238 v_pk_add_u16 v1, v2, v3 op_sel:[
1239 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1240 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[
1241 // CHECK-NEXT:{{^}}                                ^
1242
1243 v_pk_add_u16 v1, v2, v3 op_sel:[,0]
1244 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1245 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,0]
1246 // CHECK-NEXT:{{^}}                                ^
1247
1248 v_pk_add_u16 v1, v2, v3 op_sel:[,]
1249 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1250 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,]
1251 // CHECK-NEXT:{{^}}                                ^
1252
1253 v_pk_add_u16 v1, v2, v3 op_sel:[0,]
1254 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1255 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,]
1256 // CHECK-NEXT:{{^}}                                  ^
1257
1258 v_pk_add_u16 v1, v2, v3 op_sel:[]
1259 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1260 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[]
1261 // CHECK-NEXT:{{^}}                                ^
1262
1263 //==============================================================================
1264 // unsupported format
1265
1266 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT]
1267 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unsupported format
1268 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT]
1269 // CHECK-NEXT:{{^}}                                                             ^
1270
1271 //==============================================================================
1272 // expected vertical bar
1273
1274 v_ceil_f32 v1, |1+1|
1275 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected vertical bar
1276 // CHECK-NEXT:{{^}}v_ceil_f32 v1, |1+1|
1277 // CHECK-NEXT:{{^}}                 ^
1278
1279 //==============================================================================
1280 // expected left paren after neg
1281
1282 v_ceil_f32 v1, neg-(v2)
1283 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after neg
1284 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg-(v2)
1285 // CHECK-NEXT:{{^}}                  ^
1286
1287 //==============================================================================
1288 // expected left paren after abs
1289
1290 v_ceil_f32 v1, abs-(v2)
1291 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after abs
1292 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs-(v2)
1293 // CHECK-NEXT:{{^}}                  ^
1294
1295 //==============================================================================
1296 // expected left paren after sext
1297
1298 v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD
1299 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after sext
1300 // CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD
1301 // CHECK-NEXT:{{^}}                      ^
1302
1303 //==============================================================================
1304 // expected closing parentheses
1305
1306 v_ceil_f32 v1, abs(v2]
1307 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses
1308 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(v2]
1309 // CHECK-NEXT:{{^}}                     ^
1310
1311 v_ceil_f32 v1, neg(v2]
1312 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses
1313 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(v2]
1314 // CHECK-NEXT:{{^}}                     ^
1315
1316 v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD
1317 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses
1318 // CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD
1319 // CHECK-NEXT:{{^}}                         ^
1320
1321 //==============================================================================
1322 // expected a left parentheses
1323
1324 ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3]
1325 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parentheses
1326 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3]
1327 // CHECK-NEXT:{{^}}                                    ^
1328
1329 //==============================================================================
1330 // expected an absolute expression or a label
1331
1332 s_branch 1+x
1333 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression or a label
1334 // CHECK-NEXT:{{^}}s_branch 1+x
1335 // CHECK-NEXT:{{^}}         ^
1336
1337 //==============================================================================
1338 // expected a 16-bit offset
1339
1340 ds_swizzle_b32 v8, v2 offset:0x10000
1341 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 16-bit offset
1342 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:0x10000
1343 // CHECK-NEXT:{{^}}                             ^
1344
1345 //==============================================================================
1346 // not a valid operand
1347
1348 v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
1349 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
1350 // CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
1351 // CHECK-NEXT:{{^}}                           ^
1352
1353 //==============================================================================
1354 // TFE modifier has no meaning for store instructions
1355
1356 buffer_store_dword v[1:2], off, s[12:15], s4 tfe
1357 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: TFE modifier has no meaning for store instructions
1358 // CHECK-NEXT:{{^}}buffer_store_dword v[1:2], off, s[12:15], s4 tfe
1359 // CHECK-NEXT:{{^}}                                             ^