| commit | 580eedab5247e0bbcce870522333bd8f885280fa | |
| author | Sam Parker <sam.parker@arm.com> | |
| Tue, 25 Jun 2019 10:45:51 +0000 (25 10:45 +0000) | ||
| committer | Sam Parker <sam.parker@arm.com> | |
| Tue, 25 Jun 2019 10:45:51 +0000 (25 10:45 +0000) | ||
| tree | 427c95149aef9a1108db2039d6197ba2b31afdbe | treesnapshot (tar.gz zip) |
| parent | 9762cf4df3c90ac740ba115a19f7387847c02b86 | commitdiff |
[ARM] DLS/LE low-overhead loop code generation
Introduce three pseudo instructions to be used during DAG ISel to
represent v8.1-m low-overhead loops. One maps to set_loop_iterations
while loop_decrement_reg is lowered to two, so that we can separate
the decrement and branching operations. The pseudo instructions are
expanded pre-emission, where we can still decide whether we actually
want to generate a low-overhead loop, in a new pass:
ARMLowOverheadLoops. The pass currently bails, reverting to an sub,
icmp and br, in the cases where a call or stack spill/restore happens
between the decrement and branching instructions, or if the loop is
too large.
Differential Revision: https://reviews.llvm.org/D63476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364288 91177308-0d34-0410-b5e6-96231b3b80d8
Introduce three pseudo instructions to be used during DAG ISel to
represent v8.1-m low-overhead loops. One maps to set_loop_iterations
while loop_decrement_reg is lowered to two, so that we can separate
the decrement and branching operations. The pseudo instructions are
expanded pre-emission, where we can still decide whether we actually
want to generate a low-overhead loop, in a new pass:
ARMLowOverheadLoops. The pass currently bails, reverting to an sub,
icmp and br, in the cases where a call or stack spill/restore happens
between the decrement and branching instructions, or if the loop is
too large.
Differential Revision: https://reviews.llvm.org/D63476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364288 91177308-0d34-0410-b5e6-96231b3b80d8
17 files changed: